Analog-to-Digital Converter

1. Field of the Invention

This invention relates to an analog-to-digital converter (hereinafter referred to as an ADC), and more particularly to an integrated ADC as used in the field of welfare electric equipments, home electric apparatus, etc.

2. Description of the Prior Art

In a prior art, an ADC comprises an input terminal to which an analog input signal is applied, a capacitor connected to the input terminal through a switch, for storing the analog input signal, a discharging circuit for discharging the charge stored in the capacitor, a level detection circuit connected to the input terminal of the capacitor and a counter connected to the output terminal of the level detection circuit for counting the number of clock pulses. An example of the prior ADC is shown in G. Smarandoin, et al. "An All MOS Analog to Digital Converter Using a Constant Slope Approach", IEEE Journal of Solid-State Circuits, June 1976.

In this ADC, however, if an input signal voltage is lower than the detection level voltage V.sub.TH, the discharge time T cannot be detected, so that an analog to digital conversion (called A-D conversion hereinafter) is not performed.

In order to perform the A-D conversion over a wide range of the input signal, some of the inventors of this invention previously developed a new type ADC, for which a patent application was filed as U.S. patent application Ser. No. 887,966 on Mar. 20, 1978. The above new type ADC has a bias voltage supply means connected to the capacitive element, which shifts the potential at the input terminal of the capacitor during the discharge time T.

But, in this circuit, when the bias voltage V.sub.B is larger than the detection level voltage V.sub.TH and the potential of the output terminal of the capacitor changes from the bias voltage V.sub.B to the ground voltage, a negative voltage (generally reverse polarity of the input signal one) is produced on the input terminal of the capacitor. Therefore, if the new type ADC is constructed with n-channel MOSIC, the circuit may be broken or may have an extraordinary action.

An object of this invention is to provide an analog to digital converter wherein an input level can be converted over a wide range.

Another object of this invention is to provide an analog to digital converter which is suitable for the formation of an IC.

In order to achieve the above objects, an ADC of the present invention comprises a storage means with an input terminal for storing an analog input signal which is applied to the input terminal, a discharging circuit coupled with the storage means for discharging the charge stored in said storage means, a level detection means connected to the input terminal of said storage means for detecting the time when a voltage at the input terminal of said storage means becomes equal to a detection level, a counter means for counting the number of clock pulses, a bias supply means connected in series with said storage means for shifting the voltage at said input terminal of said storage means above said detection level, and a short-circuiting means connected in parallel with said storage means for short-circuiting said storage means.

According to the ADC of this invention, the measurement of a very small input signal voltage or the A-D conversion of such an input signal becomes possible, even if the input signal voltage is below the detection level. Moreover, no negative voltage is generated in any part of the circuit, regardless of the magnitude of the bias voltage.

FIG. 1 shows a schematic construction of a prior art ADC of U.S. patent application Ser. No. 887,966.

FIG. 2 shows waveform diagrams for explaining the operation of the circuit shown in FIG. 1.

FIG. 3 shows a schematic circuit of an embodiment of this invention.

FIG. 4 shows waveform diagrams for explaining the operation of the circuit shown in FIG. 3.

FIG. 5 shows the schematic circuit of another embodiment of this invention.

FIGS. 6A and 6B show circuit diagrams of the constant current discharging circuits shown in FIGS. 3 and 5.

FIG. 7 shows a circuit diagram applying to a bias voltage supply means shown in FIGS. 3 and 5.

FIG. 8 shows a part of a circuit diagram of another embodiment of this invention.

Prior to a detailed description of this invention, the construction and the operation of a conventional ADC will be explained with FIGS. 1 and 2.

Referring to FIG. 1, reference numerals 101 and 100 denote input terminals, to which an analog input signal and a reference voltage are applied, respectively. As will be described later, the reference voltage together with the ground voltage is used to eliminate any influence of the circuit component elements upon the value of a digital signal corresponding to an analog input signal. Reference numerals 102, 103 and 104 denote switches for applying to a capacitor 105 the reference voltage, analog input signal and ground voltage, respectively. A bias voltage supply means generally denoted by 106 functions to connect a bias voltage V.sub.B to the capacitor 105 and includes a switch 107, a switch 108 and a bias voltage source 109. Reference numeral 110 denotes a discharging circuit for discharging the charge stored in the capacitor 105. The discharging circuit 110 is of a constant current type. Reference numeral 111 denotes a level detecting circuit for detecting the time when a voltage at the input terminal of the capacitor 105 reaches a predetermined value, and 112 a counter. The counter 112 counts up clock pulses for the time ranging from the initiation of discharging the capacitor 105 to a time representative of the predetermined value of the capacitor input terminal voltage and delivers the number of the counted clock pulses. Reference numeral 113 denotes the output of the counter 112. Generally, this output 113 is sent to a processor circuit (not shown as having no direct relation to this invention).

Referring to FIG. 2, an operational description will be given herein of the ADC shown in FIG. 1. FIG. 2(a) illustrates an input terminal voltage V of the capacitor 105, FIG. 2(b) illustrates pulses applied to the gate terminals 124, 123 and 122 of the respective switches 104, 103 and 102, FIG. 2(c) illustrates the operation period of the discharging circuit 110, FIG. 2(d) illustrates pulses applied to the gate terminal 127 of the switch 107, FIG. 2(e) illustrates pulses applied to the gate terminal 128 of the switch 108 for connecting the bias voltage V.sub.B to the capacitor 105, FIG. 2(f) illustrates the output signal of the level detection circuit 111, and FIG. 2(g) illustrates the counting period of the counter 112.

Consider the storage of the analog input signal received at the input terminal 101 into the capacitor 105 when the switch 103 is turned on as shown in FIG. 2(b). During this storage period, the switch 107 in the bias voltage supply means 106 maintains its ON state as shown in FIG. 2(d) so that the other end (not input terminal) of the capacitor 105 is grounded. Since the switch 103 maintains its ON state for a predetermined period, the capacitor 105 will be saturated with a voltage value V.sub.I of the analog input signal as shown in FIG. 2(a). Subsequently, as the switches 103 and 107 are turned off and the discharging circuit 110 and switch 108 are turned on, the input terminal voltage V of the capacitor 105 rises up to (V.sub.I +V.sub.B), initiating the simultaneous discharging of the capacitor 15. The input terminal voltage V of the capacitor 105 then decreases gradually until it reaches a detection level voltage V.sub.TH of the level detection circuit 111 with simultaneous turning off of the discharging circuit 110 and switch 108 as well as simultaneous turning on of the switch 107. As a result, for a period ranging from the initiation of operation of the discharging circuit 110 to the arrival of input terminal voltage V at the detection level voltage V.sub.TH determined by the level detection circuit 111, as shown in FIG. 2(g), the counter 112 counts up clock pulses to complete the A-D conversion of the analog input signal.

It is to be noted that FIG. 1 is not illustrative of a control circuit for the switches 103, 107 and 108, discharging circuit 110 and counter 112. It is also to be noted that the detection level voltage V.sub.TH of level detection circuit 111 has been preset in compliance with the voltage range of analog input signal V.sub.I and that the bias voltage V.sub.B has been selected to be larger than the detection level voltage V.sub.TH.

As apparent from FIG. 2(a), in the ADC of FIG. 1, the voltage V at the input terminal of the capacitor 105 becomes negative, when the SW108 is turned off and the SW107 is turned on, because the bias voltage V.sub.B is larger than the detection level voltage V.sub.TH. Assume that the circuit is formed by n-channel MOSIC, the pn junctions between the drain regions of the OFF state switches 102, 103, 104 and the substrate have a forward bias, when the voltage V at the input terminal of the capacitor 105 is negative. Consequently, the circuit may be broken or may have an extraordinary action.

In order to avoid this phenomenon, the switches 104 and 107 may be simultaneously turned on to put both the terminals of the capacitor 105 at the zero potential, or ground voltage after the switch 108 is turned off. However, the possibility of IC break down is still high, since it is difficult to obtain such a conincidence.

A detailed description of this invention, hereinafter, will be made with reference to the drawings.

In FIG. 3, the same reference numerals as in FIG. 1 denote the same elements. Reference numeral 301 denotes an input terminal, to which an analog input signal is applied, numeral 303 denotes a switch, from which the analog input signal is applied to a storage means 305, and 306 denotes a bias voltage supply means, which is constructed by a switch 307, a switch 308 and a bias voltage source 309. Reference numeral 315 denotes a switch which is newly added in parallel with the storage means 305, for short-circuiting both the terminals of the storage means 305.

In this embodiment, the switch 315 is turned on to recover the voltage V at the input terminal of the storage means 305 to the bias voltage V.sub.B, when the voltage V drops to the detection level voltage V.sub.TH of the level detecting circuit 111.

This operation is minutely explained with reference to FIG. 4. FIG. 4(a) shows the voltage V at the input terminal of the storage means 305, FIG. 4(b) shows the ON and OFF states of the switch 303, FIG. 4(c) shows the operational state of the discharging circuit 110, FIGS. 4(d), 4(e) and 4(f) show the ON and OFF states of the switches 307, 308 and 315, respectively, and FIG. 4(g) shows clock pluses counted by the counter 112.

Firstly, a charge corresponding to the analog input signal is stored in the storage means 305 and the voltage V at the input terminal thereof becomes the voltage V.sub.I under the ON states of the switches 303 and 307. Subsequently, concurrently with turning off the switches 303 and 307, the switch 308 is turned on, the operation of the discharge circuit 110 of a constant current type is initiated to discharge the change stored in the storage means 305, and the counter 112 is set. At the beginning of discharging, the voltage V at the input terminal of the storage means 305 is V.sub.I +V.sub.B. At the same time, the condition that bias voltage V.sub.B > detection level voltage V.sub.TH permits the level detecting circuit 111 to deliver the output of "1" level which causes the counter 112 to count clock pulses for a period. This period varies with the magnitude of voltage V.sub.I. After the initiation of discharging, the voltage V at the input terminal of the storage means 305 gradually decreases from V.sub.I +V.sub.B to the detection level voltage V.sub.TH and eventually, at V.sub.TH, the output of level detecting circuit 111 is inverted from "1" level to "0" level. Concurrently therewith, the discharging circuit 110 is turned off, causing the counter 112 to terminate its counting of the clock pulses as shown in FIG. 4(g). At the termination, according to the invention, the switch 315 is turned on to recover the voltage V at the input terminal of the storage means 305 up to V.sub.B. In other words, the switch 315 short-circuits both the terminals of the storage means 305. After a lapse of time, the switch 307 is turned on along with simultaneous turning off of the switch 308 so that the voltage V at the input terminal of the storage means 305 falls to zero, thus completing one cycle of the A-D conversion according to the invention. As will be seen from FIG. 4(a), according to the invention, the voltage V at the input terminal of the storage means 305 never falls below zero voltage. Accordingly, even when the invention is materialized in the form of an IC by using n-channel MOSFET's, it is completely freed from the breakdown of the IC. When considering the inversion of the voltage polarity, the above advantage is valid for the formation of IC by using p-channel MOSFET's.

While the foregoing embodiment was explained by way of the constant current type discharging circuit 110, a discharging circuit of an exponential slope type may obviously be used.

A concrete example of V.sub.B, V.sub.TH, and V.sub.I will be briefly described here. When the level detection circuit 111 is constituted by multistage connections of inverters, V.sub.TH may be set at 0.5 V to 1.5 V. If V.sub.TH is set around 1.3 V and the bias voltage V.sub.B is set around 2.0 V, all the input signal voltage V.sub.I above 0 (zero) V can be A-D converted.

FIG. 5 shows another embodiment of this invention. In this Figure, the same reference numerals as in FIG. 1 and FIG. 3 denote the same elements. Referring to FIG. 5, reference numerals 501 and 500 denote input terminals, to which an analog input signal and a reference voltage are applied, respectively. Reference numerals 502, 503 and 504 denote switches made of MOSFET's for connecting the reference voltage, analog input signal and ground voltage. A bias voltage supply means generally denoted by 506 includes MOSFET switches 507 and 508 and a source 509 of bias voltage V.sub.B. A MOSFET switch 515 is adapted to short-circuit the capacitor 505. Control terminals 522, 523, 524, 527, 528 and 525 are supplied with pulses for controlling the gates of MOSFET switches 502, 503, 504, 507, 508 and 515, respectively.

In this embodiment, assuming that the count values of counter 112 are N.sub.RC, N.sub.IC and N.sub.OC for the reference voltage V.sub.R, the input signal voltage V.sub.I and the zero voltage V.sub.O respectively the following equation holds.

It is seen that the capacitance C of the capacitor 505 and the bias voltage V.sub.B do not appear in the above equation.

Accordingly, it is possible to obtain accurate digital values which are immune to variations in the capacitance C and bias voltage V.sub.B.

FIGS. 6A and 6B show examples of the constant current type discharge circuit. The construction of FIG. 6A is described in detail in the specification of Japanese patent application No. 87417/77. In FIG. 6A, 601 denotes a voltage V.sub.DD supply terminal, 602 a control terminal for applying a control pulse to switch 603 for the ON-OFF operation of the constant current circuit, 604 a constant current output circuit, and 605 a bias circuit for the constant current output circuit 604.

The constant current output circuit 604 comprises two enhancement type MOSFET's 606 and 607 connected in series between the output terminal and the ground. The bias circuit 605 serves to operate the enhancement type MOSFET's 606, and 607 in the saturation region, and is formed by a first voltage divider circuit comprising a depletion type MOSFET 608 and an enhancement type MOSFET 609 and a second voltage divider circuit comprising a depletion type MOSFET 610 and an enhancement type MOSFET 611.

The constant voltage of the first voltage divider circuit is applied to the gate of MOSFET 607, while that of the second voltage divider circuit is applied to the gate of MOSFET 606.

This constant current circuit utilizes basically the fact that the drain currents in the saturation region of the enhancement type MOSFET's 606 and 607 are substantially constant independent of the drain voltage. Furthermore, the fact that the drain currents of the MOSFET's 606 and 607 varies in the opposite direction to that of the voltage variation at the connection point of these MOSFET's to stabilize the drain voltage of MOSFET 607 always at a constant value, is also appreciated.

FIG. 6B shows another construction of the constant current discharging circuit. The gate voltage of an enhancement type MOSFET 607 is maintained constant by a bias circuit 613. Another enhancement type MOSFET 606 has an ON-OFF switch function for the constant current discharging circuit, in other words, is the discharging switch. 612 denotes a terminal for supplying the control pulse.

FIG. 7 shows another construction of the bias voltage supply means in FIG. 3 and FIG. 5. The bias voltage supply means 701 is realized by a conventional inverter of MOSFET's 704 and 705, with 702 and 703 being V.sub.DD supply and control terminals respectively. The potential difference between the low and high levels of the inverter corresponds to the bias voltage V.sub.B. Namely, the inverter is at the low level at the charging period, while it is at the high level at the discharging period. Usually, the low level is grounded.

Furthermore, the level detection circuit 111 in FIGS. 3 and 5 is suitably built in an IC by a multiconnection of inverters, but analog comparators and operational amplifiers are also suitable.

Moreover, as the connection position of the bias voltage supply means, such a position as shown in FIG. 8 is also allowed. In FIG. 8, 806 denotes a bias voltage supply means, which is constructed by MOSFET's switches 807 and 808, and a bias voltage source 809, 805 denotes a capacitor, and 815 denotes a MOSFET's switch for short-circuiting both terminals of the capacitor 805. When taking the junction between MOSFET's switches 807 and 808 for the input terminal of the storage means, the foregoing descriptions of the embodiments with reference to FIGS. 3, 4 and 5 are also exactly descriptive of this circuit.

Well, some embodiments of this invention have been described in detail above. The methods and the constructions for solving the problem of fluctuation or long term variation of the bias voltage V.sub.B are mentioned in the afore-mentioned specification of U.S. patent application Ser. No. 887,966. Those methods and constructions can be also applied to the ADC of this invention.

Although not described in the above explanation, according to this invention, it is possible to control the operation of the bias voltage supply means depending on the characters of analog input signal to be A-D converted in such a way that the bias voltage supply means operates if the analog input signal voltage V.sub.I is smaller than the detection level voltage V.sub.TH, while it does not operate if V.sub.I is larger than V.sub.TH.

Furthermore, for constructing the ADC of this invention in an IC, a storage means or a capacitor and a bias voltage source may be external components of the IC.