Communication Processor Apparatus for Use in a TDM Switching System

1. Integrated Transmission and Switching System, Ser. No. 874,521, filed Feb. 2, 1978, invented by John C. McDonald et al, and assigned to the same assignee as the present invention.

2. Integrated Message Accounting System, Ser. No. 781,348, filed Mar. 25, 1977, invented by John C. McDonald and James R. Baichtal and assigned to the same assignee as the present invention.

3. Dial Pulse Register/Sender For A TDM Switching System, Ser. No. 762,801, filed Jan. 26, 1976, now U.S. Pat. 4,133,980, issued Jan. 9, 1979, invented by Johannes A. R. Moed and assigned to the same assignee as the present invention.

The present invention relates to integrated transmission and switching systems and more particularly to a communications processor.

It is desirable in telephone switching systems to incorporate sophisticated integrated switching techniques to enable switching of telephone calls at a "local" level thereby enabling connections of a local subscriber line to the outside world.

Referring to the cross-referenced application entitled "Integrated Transmission and Switching System", a pulse code modulated (PCM) switching system is disclosed, having a base switch and one or more subscriber switches to enable connections between a plurality of local subscriber lines and the outside world, utilizing a plurality of multitime slot digital data buses commonly known as a T-1 line. In PCM switching techniques analog data is sampled at 8 Khz and the resultant sampled data are multiplexed within a periodic time frame. One PCM switching technique utilizes a multi-frame format of 12 frames where each frame includes 24 time slots at a periodic frame rate of 125 .mu.sec.

Each time slot utilizes 8 bits of sampled information to digitally represent the analog information. In a multi-frame format of 12 frames, each frame includes 193 bits per frame and frames 6 and 12 are the signaling frames where the sixth frame is called the A frame and the twelfth frame is called the B frame. During the sixth and twelfth frames of the multi-frame format, the eighth bit (the least significant bit) is utilized for supervisory signaling purposes such as indicating on-hook, off-hook and dial pulsing conditions. Generally, there is no signal degradation if only one of the frames is to be utilized for signaling purposes. It is, therefore, desirable to utilize the signaling bit in the B frame (frame 12) for other purposes, such as a common data channel. This would provide a data channel comprising 24 bits.

Alternatively, another data channel could be utilized by using the framing bit which occurs at the beginning of each frame in a multi-frame format, which identifies the beginning of a particular frame. Odd frames in the multi-frame format (F1, F3, F5, F7, F9, F11) are indicated by framing bit code of alternating "1" and "0". The framing code for odd frames is, therefore, 101010. To identify the signaling frames in a multi-frame format (F6 and F12), the even frames in a multi-frame format utilize a different code to identify the signaling frame. Whenever there is a transition from one frame to a signaling frame in the even frame format, the framing bit changes state. Therefore, the even frame code for frames F2, F4, F6, F8, F10, F12, is 001110. The transition between frame 4 and frame 6 is a change of state to indicate a signaling frame. Similarly, the transition between frame F10 and F12 is a change of state from "1" to "0". The entire framing code is 100011011100. The even frame pattern can be seen as a 000111 code which is required to check the sixth and twelfth frame for desired signaling purposes. It is desirable to utilize the framing code to establish a data channel by periodically removing the 000111 even framing pattern and substituting, therefore, a data channel.

The cross referenced application entitled "Integrated Message Accounting System" utilizes a signal processor to detect dial pulsing, on-hook and off-hook conditions and to send supervisory signaling bits to specified time slots during the signaling frames. In order to enable the connections between a subscriber line and the outside world, there is a need for a communications system between a central office base switch and a local subscriber switch to provide the necessary communications link. This results in the desirable feature of utilizing existing equipment while providing a communications link between a subscriber switch and the central office base switch.

In view of the above background, it is an object of the present invention to provide a communications processor for establishing a communications link between a central office base switch and a local subscriber switch.

The present invention relates to a communications processor apparatus for use in an integrated telephone transmission and switching system for establishing a communications link between a central office and a digital local subscriber switch.

The system operates in a multiframe format consisting of a plurality of frames including signaling frames where each frame consists of a plurality of time slots having a time slot rate and where the plurality of frames includes signaling frames having supervisory signals where the supervisory signals occur as a signaling bit during each time slot in the signaling frame. The system includes a base switch connected to a plurality of multitime slot buses and subscriber switch means connected to a pair of the buses for connecting a plurality of local subscriber lines to specified time slots on the buses.

The communication processor apparatus includes means connected to receive the signaling bits during the signaling frames and multiplexer means connected to the buffer means for selecting in alternate signaling frames the sequential signaling bits which are in the form of a message on one of the buses from the subscriber switch means. A channel selector connected to the multiplexer means specifies the pair of data buses, thereby enabling the multiplexer means to pass the message signaling bits to the apparatus.

A receiver means is connected to the multiplexer means for receiving the message signaling bits and transmitter means are connected to the multiplexer means for transmitting sequential signaling bits in the form of a message during the alternate signaling frames. A processor is provided for controlling the operation of the apparatus.

In another embodiment, the communications processor could utilize the framing bit code in a manner similar to the reception and transmission of the signaling bits.

In accordance with the above summary, the present invention achieves the objective of providing a communication processor for establishing a communication link between a central office base switch and a subscriber switch.

Additional objects and features of the invention will appear from the following description in which the preferred embodiments of the invention have been set forth in dtail in conjunction with the drawings.

FIG. 1 depicts a block diagram of an integrated transmission and switching system in accordance with the present invention.

FIG. 2 depicts a block diagram of a base switch, which forms a portion of FIG. 1.

FIG. 3 depicts a block diagram of a communication processor and signal processor according to the present invention, which forms a portion of FIG. 2.

FIG. 4 depicts a block diagram of a communication processor transmitter, which forms a portion of FIG. 3.

FIG. 5 depicts a block diagram of a communication processor receiver, which forms a portion of FIG. 3.

FIG. 6 depicts a timing diagram for the communication processor of FIG. 3.

Referring to FIG. 1, a block diagram of one embodiment of an integrated digital transmission and switching system (local digital switch) is shown which provides Class 5 central office switching functions. It includes a base switch 10 and one or more subscriber switches such as local subscriber switches 20, 25 and remote subscriber switches 21, 30. The subscriber switches such as switch 20 concentrate and connect a plurality of subscriber lines to the base switch 10. For example, local subscriber switch 20 concentrates and connects up to 336 subscriber lines to the base switch via buses 22, 23.

In one approach for a digital telephone switching system, a multiplicity of conversations are multiplexed serially along a two-wire digitally multiplexed line commonly known as a T-1 line, such as buses 22, 23 in FIG. 1. Each T-1 line has 24 pulse code modulated (PCM) time slots operating in a basic time frame of 125 .mu.sec. Each time slot is allocated 8 bits in which sampled data between a calling party and a called party is digitally represented in PCM format. Each frame of 125 .mu.sec includes one frame bit plus 24 time slots of 8 bits each or a total of 193 bits per frame, with the frame rate based upon a sampling rate of 8 KHZ (the reciprocal of 125 .mu.sec). A typical frame structure known in the art includes a multi-frame format of 12 frames of 193 bits each, in which the eighth bit of each time slot in frames 6 and 12 carries a signaling bit. The signaling bits are used by signal processing circuitry to detect supervisory signals such as on hook, off hook and dial pulse.

In FIG. 1, the base switch 10 is connected to a voice bank 11 via T-1 line 16. Voice bank 11 is well-known equipment which interfaces to 24 trunks, which thereby allows for trunk termination directly on the base switch 10. In one embodiment, the base switch 10 interfaces to the world on 64 T-1 lines (a total of 1536 time slots) and can switch non-blocking between any of its time slots. The base switch 10 is described in the cross-referenced application entitled "An Integrated Message Accounting System".

Each of the 24 or 48 channels between a switch such as subscriber switch 20 and the base switch 10 is referred to as a junctor. The subscriber switches may be collocated with the base switch 10 such as switches 20, 25 or located at a remote site such as remote subscriber switches 21, 30. A remote subscriber switch can interconnect the 336 subscriber lines within the switch. The subscriber carrier terminals (SCT) 26, 31 connect 24 subscriber lines to T-1 lines 27, 32, which provides connections to particular subscriber switches. Equipment remotely located is connected to the various switches through repeaters 13. In one embodiment, a local (LSS) or remote (RSS) subscriber switch can handle up to 336 local loops for connection to the 48 time slots on the T-1 lines. Each subscriber switch, whether local or remote, uses two T-1 lines for connection to the base switch 10. Therefore, in a local subscriber line system with 6384 terminations, the RSS and LSS would require 38 of the available 64 base switch 10 ports available. This leaves 26 ports or 624 channels (26.times.24) for multi-frequency senders, receivers and trunks.

Various termination examples for the switching system described herein are as follows:

Before describing FIGS. 1-14 in further detail, a brief overview discussing the routing of a telephone call will be given. When a subscriber goes off hook, this condition is detected by a subscriber switch such as switch 20 and a message is sent to the base switch 10. The message contains the subscriber line number and state of the subscriber originating the call. The base switch 10 finds an idle junctor to the associated subscriber switch and sends a message to the subscriber switch commanding it to connect the subscriber line to the idle junctor. The subscriber switch will make the connection and perform a path test to determine if a path was set up correctly. The base switch 10 will connect dial tone by sending a message to an internal service generator commanding it to attach dial tone to the associated time slot. Dial tone is removed when the first digit is received. The called number is translated in the base switch by an internal system controller to determine how to route the call. For a local call, the base switch system controller checks if the called party is idle and determines the identity of the called party's particular subscriber switch. Ring back tone is applied to the calling party's line and message is sent to the called party's subscriber switch to command it to ring the appropriate line. When the called party answers, the ringing is stopped, the ring back tone is dropped and a path is established between the two junctors through the base switch. An idle junctor to that subscriber switch is selected and it is commanded to set up a connection between that junctor and the called party. No further action occurs until the call terminates and then the path in the base switch is dropped and messages are sent to the associated subscriber switches to command them to drop their connections and restore the lines to the idle condition.

Referring to FIG. 2, the base switch 10 is shown and is described in more detail in the cross referenced application entitled "Integrated Message Accounting System". The base switch 10 provides switching functions and interfaces directly to 64 T-1 lines. T-1 interfaces are used to connect either local or remote subscriber switches via T-1 lines such as 22, 23 of FIG. 1. Switching functions are provided to connect calls between subscriber switches, either local or remote, and between subscriber switches and trunks. The base switch 10 incorporates redundancy features for each subsystem (primary and secondary) and for simplicity will generally be described herein for only the primary subsystems.

Briefly, the subsystems within base switch 10 include a signal processor 40, line groups 41, time slot interchanger 42, service generator 43, multi-frequency sender/receiver 44, and master clock 45, all of which are controlled by system controller 50. In addition, a communication processor 46 is connected with the signal processor 40 and to the system controller 50 to provide a communications link between subscriber switches and the base switch. The communications link is over associated T-1 lines between the subscriber switch and the base switch, such as lines 22, 23 of FIG. 1, which form a part of buses 53 or 54 of FIG. 2.

With a sampling frequency of 8,000 Hz for encoding PCM data, one timing frame equals 125 microseconds with 24 time slots per frame per T-1 line. Each channel of information is in the form of 8 bit channel words. A framing bit is added every 24 channels to form and define a frame. Each frame of 125 microseconds equals one frame bit plus the 24 time slots of 8 bits each and therefore there are 193 bits per frame.

In a multiframe format of twelve frames, the frame bit occurs once at the start of each frame, with a framing code that takes 12 frames to repeat.

In each time slot there is an 8 bit speech code to digitally represent a quantized value of a particular portion of an analog signal. Once each six frames the eighth bit of each time slot carries a signaling bit to indicate on-hook or off-hook status of that particular channel or time slot.

In PCM systems like that of FIG. 2, quantizing a message signal by certain discrete levels or steps inherently introduces an initial error in the amplitude of the samples, giving rise to quantization noise. Quantization noise can be reduced by the use of nonuniform spacing of levels, to provide smaller steps for weaker signals and coarser quantization near the peak of large signals. The .mu.-255 companding law utilizes this concept of encoding PCM data in which the coding magnitude range is divided into 8 segments, and 16 levels are equally spaced within each of the 8 segments. From one segment to the next higher, the level spacing (step size) increases by a factor of 2. In the 8 bit code word representing any sample, the first bit gives the sign, the next 3 bits describe which of the 8 segments contain the sample, and the last 4 bits specify the nearest of the 16 possible levels within the segment.

In FIG. 2, data on T-1 lines 53 are applied to both the primary and secondary line groups 41. For example, data is input to primary line group 41-1 and secondary line group 41-2.

As seen in FIG. 2, primary and secondary interface redundancy is employed in all major subsystems to prevent a signal point failure which could cause the system to go down. Faulty subsystems are automatically switched off line to provide minimum interruption to service.

A line group 41 interfaces any T-1 line pairs 53 with time slot interchangers (TSI) 42, designated TSI 1-2. A line group 41 also interfaces multifrequency sender (MFS) and receiver (MFR) 44 with the TSI 42. A group such as line group 41 accepts bipolar PCM data from a T-1 line, which is converted by the line group to 9-bit parallel (includes parity bit) and sent to the time slot interchanger (TSI) 42. Error signals and signal bits are sent to the signal processor (SP) 40 for further analysis.

It is possible to operate 16 T-1 interfaces for each primary and secondary subsystem per line group. Each interface accommodates one T-1 line and up to four line groups per base switch may be used.

A line group organizes the data from 16 T-1 lines or 15 T-1 lines and the MFS onto a 384 time slot data bus 58 to the TSI's 42.

Referring to FIG. 2, the TSI 42 switch channel time slot data (8 bits plus parity) from any of the four line groups to any other channel time slot of any other of the four line groups. For example, data from line group 1 could be sent to TSI and switched out to line group 4. When it is available from a line group data bus, the TSI's hold it until the proper time for output in the next frame and transmit the data to the line group data bus such as bus 59 for output. The TSI 42 contains control and data memory for all time slots and communicate with both the primary and secondary system controllers (SC) 50-1, 50-2.

In FIG. 2, the service generator (SG) 43 provides capability to connect one of several standard tones in PCM format to any of the channel time slots. These tones include 1,000 Hz, 120 IPM busy, 60 IPM busy, dial tone, ring back tone and internal tones for the system. The SG 43 receives control signals from the respective system controller (SC 50).

The signal processor (SP) 40 monitors all the input channels for changes of state and dialed digits. Each time a channel is seized or released, or a digit is dialed, a message is sent to the respective SC 50 containing the channel number and the event. All the information needed to determine the changes of state or dial digits is time division multiplexed over several leads originating from the line group on bus 56.

The SP 40 also has the capability to seize or release channels or dial digits on these channels. Frames 6 and 12 are signaling frames. During these frames, the least significant bit of the 8 bit PCM byte is replaced with a signaling bit. Frame 6 is used for an "A" signaling bit and frame 12 is used for a "B" signaling bit. The signal processor uses the A signaling bit for seizure, release and dial digit detection. The B signaling bit is used for state change detection only.

The signal processor 40 receives and transmits "A" and "B" bits from and to the line groups 41 for on/off hooks and digits. The communication processor 46 performs the control and communication functions for the signal processor.

In one embodiment, the "B" signaling bits, which occur every twelve frames in a multi-frame format, are used to formulate a 24-bit message. All signaling bits are extracted from the T-1 lines by the line groups 41 and routed to the signal processor 40, which will process the signaling bits and route the messages to the system controller 50.

The communication processor 46 also performs the functions of "B" bit receivers and transmitters, interfacing and control, and channel selecting. The communication processor 46 receives and transmits the "B" bits that form the messages to and from the subscriber switches. "B" bits from all of the 64 T-1 ports are received and stored by processor 46. When a message is to be transmitted from the base switch 10 to a subscriber switch, the 24 bits are transferred to the processor 46 which then transmits them to the appropriate line group 41 at the correct time, as will be described.

In one embodiment, a message consists of four bytes of data where the first byte is a control byte and the last three bytes form the message to be sent or received. The CP 46 also scans its internal receivers to check if any messages have been received. If there is a message, it will be sent to the system controller 50. Messages received from the system controller are transferred to the appropriate line group.

In FIG. 2, the Master Clock 45 is a conventional device for generating all basic clock signals used by the base switch.

Should a single point failure occur somewhere in the primary system, the primary system controller 50-1 will de-activate the on-line system by de-activating an "Active" signal. The off-line system will go on-line by the secondary system controller 50-2 activating the secondary master clock 45-2, thereby switching the secondary (redundant) system on-line to process data.

The MF senders (MFS) 44 generate and output MF tone pairs onto a line group data bus 58 for switching through the time slot interchangers 42 to an outgoing path such as bus 59 and communicate directly with system controllers 50. The MF receivers (MFR) detects MF tones in PCM digital input form on bus 58 and send them to the SC 50.

The MFS and MFR jointly share one group of 24 time slots and associated control facilities. A minimum of 8 time slots and a maximum of 16 time slots for each sender and each receiver are available to traffic at any time subject to a total maximum of 24 time slots. Systems with more than one line group may be equipped with the above capacity per line group as required by traffic.

The dual tone multifrequency receivers (DTMF) 47 are connected to the service generator for detecting dual tone multifrequency tones at a local level and operate in a manner similar to the MFR 44.

The primary and secondary system controllers (SC) 50 are typically INTEL 8080A stored program microprocessors surrounded by a number of peripheral I/O devices 51 and interfaced to each subsystem.

The System Controllers 50 provide the following functions:

(1) call processing including routing, ANI (Automatic Number Identification), ONI, recorded announcement control and creation of billing records;

(2) SC self test; and

(3) system test and maintenance data outputs for accumulation of traffic monitoring data and generation of traffic monitoring reports. The secondary (redundant) SC 50-2 is updated continuously so that it can assume control of the system with a minimum disruption to service should primary SC 50 experience a failure.

To enable the secondary system controller to come on line and start processing calls should the primary system controller experience a failure, portions of the memory containing the states of all calls in progress are periodically copied into the memory of the secondary system controller through direct memory access techniques which are well known in the art.

Each system controller is equipped with 64K bits of memory addressable by a 16-bit address bus. Further details of the operation of the Intel 8080A microprocessor are described in the Intel 8080A System User's Manual.

Referring to FIG. 3, a block diagram of the communication processor 46 is shown. For simplicity, the communication processor 46 is shown connected to one line group, but it is to be understood that processor 46 is also connected to the other line groups in the systems. Data is input on T-1 lines 54 to line group 41 and the A & B signaling bits are gated out on bus 56-1 at the appropriate time into a buffer 201 (S201 RAM) which forms a part of the signal processor 40, the details of which are described in more detail in the cross-referenced application entitled DIAL PULSE REGISTER/SENDER FOR A TDM SWITCHING SYSTEM. The A & B signaling bits are then gated on bus 57 into the dial pulse register sender (DPRS) 202 of the signal processor 40, or into a multiplexer 203 (LS157). Timing signals provided from the signal processor control circuit 204, as seen in FIG. 6, are the DPRS CLK, F1, F2 on buses 264-66. The DP1-DP256 signals on bus 267 provide addressing for up to 386 time slots. The F1 and F2 signals identify frames 1-5, 6, 7-11, and 12, and DPRS CLK provides appropriate clocking during those periods.

The channel selector 205 includes a conventional selector (74150) connected to each line group for identifying which T-1 lines are connected to a subscriber switch. In one embodiment, there are four selectors, one each for the four line groups. The selectors are addressed by the DP1 DP8 signals on bus 267 from the SP control 204. Selector 205 identifies which of the T-1 lines are connected to the subscriber switches, and when ANDed with the F2 signal, will inform the communication processor 46 at which time transmitting and receiving signals to and from a particular subscriber switch can be effected.

The communication processor 46 also includes a CP receiver 207, CP transmitter 208, and central processing unit (CPU) 209, which typically is an Intel 8080A microprocessor and storage circuitry. The program for controlling the operation of the communication processor 46 is set forth in Appendix I.

The communication processor 46 communicates with the base switch system controller 50 of FIG. 2 via buses 210. In order to manipulate the B signaling bit for data communications between the base switch 10 and a subscriber switch the B signaling bits are input from line group 41 into buffer 201 for connecting the signaling bits to either the DPRS 202 or the communication processor 40. If the communication processor 40 is waiting for data from the line group, the selector 203 will connect the B signaling bit into the communication processor. The message is shifted via bus 260 into the CP receiver 207 and connected to the CPU 209 for transmission to the base switch system controller 50. In order to transmit data from the processor 40 to a particular line group, data is loaded from the system controller to the CPU 209, loaded into the CP transmitter 208 and gated out through MUX 203 into buffer 201 and to the line group 41 at the appropriate time.

Referring to FIG. 4, the transmitter 208 of FIG. 3 is shown in more detail. The message to be transmitted to a particular subscriber switch is loaded into shift registers 212, 213, 214, via the data bus 215 from the CPU 209 of FIG. 3. The writing of the messages into shift registers 212-214 is controlled by a typical write decode circuit 216 (LS138), which is loaded with control signals from the CPU.

The CPU also loads address register 217 with a 6 bit address in which the two high-order bits identify the particular line group and four low-order bits identify to which of 16 T-1 lines in a line group the message is to be transmitted. The 2 high-order bits on bus 273 address decoder circuit 218 (LS155), which appropriately connects the message to the particular line group on one of buses 275.

Comparator 219 is continuously comparing addresses DP1-DP8 on bus 267, which provide up to 16 T1 addresses per line group, with the address from address register 217, and when they are equal comparator 219 informs via bus 223 transmit controller 222, a typical logic circuit for enabling the shift registers 212-214 and decoder 218. The data is then output from registers 212-214 and decoder 218 to the appropriate MUX 203 (one LS157 per line group) via bus 275. MUX 203 is enabled by the appropriate signals F2 on bus 266 and the signal on bus 269 from the channel selector 205 of FIG. 3. MUX 203 receives signaling bits on bus 57-3 from DPRS 202 of FIG. 3, and depending upon whether a message is to be sent from the CP, the MUX 203 is appropriately enabled to send a message out to the buffer from the 1Y output on bus 57-2.

The other inputs to the MUX 203 are the 3A input on bus 278, which is a hard-wired "1" to indicate no message; signaling bits from the DPRS 202 into the 1A connection, which are switched out to the buffer through the 1Y connection; data on bus 57-1 from the buffer 201 into the 3B connection and switched out through the 3Y connection on bus 260-1 to the receiver 207.

The transmitter circuit 208 also puts a "busy" bit into busy register 226, which will retain that "busy" state for transmission purposes until reset by the transmit controller 222 (under control of the CPU 209). Thus, the transmitter is only transmitting one message at a time to a particular line group.

Referring to FIG. 5, the CP receiver 207 is shown in more detail. In order to receive messages from a line group, the data occurring during the "B" signaling bit time is gated from the selector 203 of FIG. 3 to latch 230 of FIG. 5. The receiver 207 may receive up to four different messages, one per line group. The data received is input via bus 282 into a message memory 231, a 1 K.times.4 bit memory for storing messages, and detect memory 232, a 4.times.16 bit memory for storing the first bit of each of the 64 T-1 lines incoming into the line groups. In order to detect the presence of an incoming message, the first bit of the B signaling bits on the 64 T-1 lines is set to "1" when there is no message, and the first bit on a particular T-1 line is set to a "0" when a message is present, which is then stored in the memory 232, as addressed by address lines DP1-DP8 on bus 267. The presence of the message is input to message flag store circuit 233, in which the set or flag bit is input on bus 295-1 through OR gate 234, AND gate 235 to flag store 236, a 4.times.16 bit memory for storing the message flag bit for each of the 64 T-1 lines. The gating logic 234, 235, 247 is duplicated for each line group, but is shown for simplicity for one line group.

The flag memory 236 stores the message flag bit and is addressed either by addresses DP1-DP8 or the address from the scan address register 241. The respective addresses are selected by selector 243 through the occurrence of signal F1 on bus 265 which is identifying the framing cycle along with clock F2 during the multiframe format, as previously described. When a message flag bit is detected, the information is sent to the CPU 209 through latches 247, 248 and bus 215. The CPU 209 sequentially scans the 64 T-1 lines by loading the scan address register 241 with four bits for identifying a particular set of 4 T-1 lines (one from each line group). Also, a message flag bit state is gated back to memory 231 on bus 284 to prevent overwriting messages in memory 231.

The CPU reads a message stored in message memory 231 by loading receive address register 240 with the proper address. Four bit address comparator 249, which also receives address DP1-DP8 on bus 267, enables receive controller 250, a typical logic circuit, at the appropriate address time. Two bits from register 240 address MUX 237 for selecting the appropriate line group. Receive controller 250 then enables the three shift registers 256-258 at the proper time for loading the data from message memory 231 onto the 8-bit data bus 215 to the CPU 209.

The flag bit from message detect memory 232 is also input to an overrun circuit 251 (identical to circuit 253) which enables the system to store additional message bits in the event that one message happens to overrun another.

The scan controller 252 enables latch 248 at the appropriate time for sending the message detect flag bits to the CPU. The write controller 253 enables the data to be written into latch 247 and corresponding latches in the overrun circuit 251 during the first 16 channel times of the multiframe format, which is the time in which the message flag bits occur.

The F1 and F2 signals on buses 265, 266 ar ANDed with the DPRS clock signal on bus 267, which when ANDed with the occurrence of the message bit signal from flag store 236 on bus 285 enable the data to be written into message memory 231.

The reset decode circuit 254 (LS155) provides appropriate resetting of the message bits under control of the CPU 209.

The scan controller 252 and receive controller 250 also connect "busy" bits via buses 280, 281 to the busy register 226 of FIG. 4 to indicate that a scan or receive cycle is currently in operation, and is reset upon control completion.

The receive and scanning cycles are briefly described as follows. The B bits are loaded into memory 231 and 232 during frames 7-11 of the multiframe format. During frame 12, the data is shifted from memory 232 to flag store 236 and to the overrun circuit 251. Scanning takes place during frames 1-5, in which the CPU 209 is loading a scan address into scan address register 241. The scanning process is looking for a flag bit in memory 236.

Data is stored during frame 12 at the appropriate addresses generated by DPRS clock 1-16. The scanning addresses are loaded into register 241 and selected by selector 243. The read or receiving cycle is also performed during frames 1-5 by addressing memory 231 by DP1-DP256 on bus 267. The data from message memory 231 is loaded into shift registers 256, 257, 258 and connected to the CPU data bus 215.

The present invention could utilize the framing bit code previously described in order to transmit and receive messages. The communication processor apparatus would then establish communications by utilizing the framing bit code signals rather than the "B" signaling bit format described herein. ##SPC1## ##SPC2## ##SPC3##