Burn-in Test System for Electronic Apparatus

This invention relates to an electronic apparatus responsive to input signals for repetitively actuating an output device for testing the apparatus and the output device. More particularly, this invention relates to a modification to a calculator or microprocessor, in which the calculator or microprocessor is responsive to input signals for repetitively actuating an output device such as a printer when the calculator or microprocessor is placed in a test mode.

Electronic microprocessor or calculator integrated circuits are frequently used with output devices, such as thermal or mechanical printers, visual displays, typewriters and the like. During the manufacturing process for such equipment it is desirable that the output devices, as well as the integrated circuits, be tested to assure proper operation thereof before the equipment is delivered to the ultimate purchaser. Electronic calculators, and especially electronic printing calculators, are preferably tested while still in the manufacturers plant. The testing may include a "burn in" test, that is, a test over a prolonged period of time, because electronic components sometimes fail not immediately, but rather after a short period of operation. Electronic printing calculators utilizing thermal printing units may fail not immediately but rather after several minutes to several hours of operation. Thus, such electronic printing calculators are tested over a prolonged period of time, usually 24 hours or longer.

To conserve the amount the paper tape used this "burn in" test is generally accomplished by intermittently actuating the calculators' printer units rather than by continuously printing during a long period of time. Originally this testing was manually performed by employees of the manufacturer of the calculator who would periodically cause each calculator tested to print out a line of characters. Subsequently, in order to lessen the amount of human labor involved, racks were provided for testing the calculators, the racks being provided with power supplies for the calculators (if required) as well as two or more electrical contact pins for each calculator to be tested. Preferably, the bottom case of each calculator was provided with a connector mating with the contact pins on the rack; the contacts in the calculators' connector were coupled to the calculator's keyboard and the contact pins on the rack were coupled to one or more switches or relays. The connections were arranged such that when the switches or relays were closed (in the proper sequence, if need be), the calculators were caused to print a line of characters (such as a line of the numeral eight). By providing appropriated timing apparatus for periodically closing the switches or relays, the calculators installed in the rack would intermittently perform the desired printing operation. While this equipment overcame inefficiencies involved with manual testing the calculators, it raised other problems, such as (1) the manual labor associated with requiring each calculator tested to be mated with the pins on the test racks, (2) breakage of either the pins or calculator connectors during use of the test rack, (3) the expense of the rack and testing apparatus and (4) the need to either standardize the test connectors or to alter the testing apparatus for a calculator model change.

It is therefore one object of this invention to eliminate the need for such special testing apparatus. It was another object of this invention that the calculators be easily tested without the need either for special connections between the calculator and some testing apparatus or for manual inputting of the line of characters to be printed for such printing operation. It was therefore another object of this invention that a calculator be provided with a self-testing mode of operation.

By eliminating the connections between the test racks and the calculators, the cost of test racks is significantly reduced, as well as the cost of maintenance thereof, the yield of calculators from an assembly line is improved and any need for redesigning the test rack upon changing the design of the calculator is avoided.

The foregoing objects are achieved as is now described. Microprocessor integrated circuits used in calculators and other equipment normally have an instruction word memory for storing a plurality of instruction words which are addressed by the contents of an address register. The instruction words read from the instruction word memory are decoded, such as by an instruction word decoder circuit, and are used to control the operations performed by the calculator in response to depression of keys at the calculator's keyboard. By loading the instruction word memory with appropriate instructions, the calculator may be made to perform many different and useful data handling and printing operations in response to different inputs at the calculator's keyboard. The microprocessor integrated circuit is caused to enter a self-testing program in response to appropriate input signals such as those caused by depression of a preselected sequence of keys at the calculator's keyboard. During the self-testing program, a memory in the microprocessor is loaded with a preselected multi-digit alphanumeric code and the preselected multi-digit alphanumeric code is automatically and repetitively transferred to the calculator's printing unit for printing thereat. Preferably, a timer circuit is also provided for timing period between printing operations, which period may be selectively controlled by an input at the keyboard; thus the timer circuit controls the rate at which the printer unit is actuated by the contents of the memory. Accordingly, the printer unit is repetitively and automatically actuated, the period of time occurring between actuations thereof either being a function of the data entered at the calculator's keyboard in one embodiment or being of a preselected duration in another embodiment.

Still further objects and advantages of the invention will be apparent from the detailed description and claims when read in conjunction with the accompanying drawings wherein:

FIG. 1 is a top view of a printing calculator of the type which may embody the present invention;

FIG. 2 is a block diagram of a microprocessor which may be implemented with the present invention;

FIG. 3 is a flow chart of operations which may be performed by a microprocessor when implemented with the present invention; and

FIG. 4 is a flow chart of operations which may be performed by another microprocessor when implemented with the present invention.

Prior to describing the structure and operation of the invention in connection with the accompanying drawings, it is to be noted that for convenience of explanation, certain embodiments of the invention are described in conjunction with an electronic printing calculator. However, it will be appreciated by those skilled in the art that the invention itself may also be used in conjunction with other electronic apparatus, and may find particular use in applications using microprocessor technology in conjunction with some output device which is preferably repetitively tested during "burn in" testing prior to delivery of the equipment to either commercial or consumer purchasers. We have described our invention in conjunction with an electronic printing calculator inasmuch as such is our preferred mode of employing our invention.

Referring now to FIG. 1, there is shown a perspective view of a desk model electronic printing calculator of the type which may embody the present invention. The calculator includes a case 1, a printer unit 2 and a keyboard 3 as well as at least one integrated circuit disposed inside case 1. By design choice, of course, the calculator may be a desk model or portable, larger or smaller, operated on alternating current (AC) or battery operated and further may be provided with a visual display, if desired. When practicing the present invention, we prefer to use a non-impact, thermal printer for printer unit 2; however, conventional mechanically impact type printers may be used if desired. Thermal printers include an array of printing mesas which are disposed adjacent to thermally sensitive paper tape. Reference may be made to U.S. patent application Ser. No. 680,835 for a typical thermal printing unit used in electronic printing calculators. The thermal printer usually includes a platten 2.1 and printing head 2.2 upon which the thermal printing mesas are disposed. Between the platten 2.1 and printing head 2.2 is carried the thermally sensitive paper which changes color or darkens in respose to heating of the printing mesas. The mesas increase in temperature in response to an electrical current passing therethrough.

Referring now to FIG. 2, there is shown a block diagram of a microprocessor chip or integrated circuit of the type which may employ the present invention. The microprocessor of FIG. 2 is a digit processor, as opposed to a word oriented processor and uses parallel data paths for transmission of data. It will become evident to those skilled in the art, however, that the present invention may be used with word or serially organized processor or calculator chips, if desired. The digit processor of FIG. 2 includes two Read-Only-Memories (ROMs) 24a and 24b and a Random Access Memory (RAM) 25 and may be used in calculator applications as described in U.S. Pat. No. 3,988,604. Each ROM stores a plurality of instruction words which are outputted in response to a ROM page address in register 46 and a program counter address in counter 36. The instruction words are outputted from either ROM 24a or 24b on bus 33 and are provided to various circuits in the microprocessor for controlling the operation thereof in response to the instruction word on bus 33. The instruction words on bus 33 are derived from a particular ROM 24a or 24b according to the setting of chapter latch 33a. Chapter latch 33a preferentially enters a zero state when the microprocessor is energized. The state of the chapter latch is changed by controls 46 in response to a branch instruction occurring after a complement chapter latch instruction. RAM 25 contains 256 memory cells which are software organized into four 16 digit registers with four bits per digit. Numerical data entered by the calculator's keyboard 3 (FIG. 1) is stored in RAM 25, along with intermediate and final results of calculations as well as status information or flags, decimal point position and other working data.

Numerical data and other information is operated on in the system by a binary adder 50 which is a bit parallel adder operating in binary with BCD software correction. The input to adder 50 is determined by an input selector 51 which receives four bit parallel inputs from several sources and selects from these what inputs are applied to the adder. First the memory read or recall lines 32 from RAM 25 provide one of the alternatives. Two registers receive the adder output, these being the "RAM Y" register 40 and an accumulator 52. Each of these has output lines separately connected as inputs 53 and 54 of selector 51. A fourth input 55 receives an output from "CKB" logic 56. The output from the adder 50 is applied to either or both the RAM Y register 40 or the accumulator 52 via lines 59. All of the operations of adder 50 and its input selector 51 etc., are controlled by a data path control PLA 60 which is responsive to the instruction words on bus 33 from ROM 24. The four bit output from the accumulator can be applied via lines 53 to an accumulator output buffer 62 and thus to a segment decoder 63 for output from the system. The segment decoder 63 is a Programmable Logical Array (PLA) and produces up to eight segment outputs on line 64 which are applied to a set of eight output buffers 65. The output arrangement contains a memory in buffer 62 so that an output digit can be held for more than one machine instruction cycle. Output is under control of the data control logic PLA 60 which is responsive to the instruction words on bus 33 from ROM 24. Line 17 from buffer 65 may then be coupled to the thermal printing mesas in thermal printer 2. Of course, if the microprocessor of FIG. 2 is fabricated using MOS integrated circuits then line 17 may be coupled to bipolar drivers since conventional MOS circuits are presently not capable of directly driving conventional semiconductor printing mesas. However, using mesas of the type taught in U.S. Pat. No. 3,982,093, may be directly driven from MOS integrated circuits the need for such bipolar drivers may be eliminated.

Output register 84 is loaded under control of line 61 as addressed by RAM word lines 26. The output from register 84 is connected via lines 85 to a set of output buffers 86. Sixteen outputs are possible, but perhaps only nine to thirteen would be provided as outputs in a typical calculator design. Thus, the outputs on lines 81 may be used to control the various digits of the printer unit such as eight digits for mantissa, two for exponents, two for annotators such as minus signs for mantissa and exponent. For a fuller discussion of a the microprocessor of FIG. 2, the reader is directed to U.S. Pat. No. 3,988,604 which issued Oct. 26, 1976 to Joseph H. Ramond, Jr. and which is assigned to the assignee of this invention. It should be noted that the microprocessor of FIG. 2 differs from the microprocessor of U.S. Pat. No. 3,988,604 in that there is twice as much ROM and ram in FIG. 2. The added Chapter Latch permits the additional ROM area to be addressed and RAM page register is three bits long in lieu of two bits to permit having eight sixteen digit pages in RAM 25. The microprocessor of FIG. 2 is currently available from Texas Instruments Incorporated by the designation TMS1100. U.S. Pat. No. 3,988,604 is hereby incorporated herein by reference.

Referring now to FIG. 3, there is shown a flow diagram of operations which may be performed by a microprocessor to practice the current invention. At block 100, the microprocessor decodes a unique sequence of key actuations at keyboard 3. Upon decoding such unique sequence of key actuations, the calculator is caused to enter the loop shown in FIG. 3 and comprising blocks 101-106 and line 107. Until this unique sequence of keys depressions is decoded by the calculator, the calculator operates in a conventional manner (assuming it has not malfunctioned, of course), and thus can add, subtract, divide and multiply numbers inputted at the calculator's keyboard 2.

In the embodiment disclosed, the key sequence which is decoded by the microprocessor before entering the self test burn in mode, comprises the steps of (1) depressing the F/A key, (2) depressing a number key and holding it down while subsequently depressing the paper advance (PAP ADV), F/A, percent (%) and C/CE keys all at once, (3) releasing the number key while still holding down the paper advance, F/A, percent (%) and C/CE keys, (4) depressing the plus (+) key while still holding down the paper advance, F/A, percent and C/CE keys and (5) releasing all keys. It will be appreciated by those familiar with electronic calculators that this key sequence is highly unusual and was selected as a matter of design choice as one which will be very unlikely to occur during the normal use of the calculator, so that the eventual purchaser of the calculator will unlikely cause the calculator to inadvertently enter this mode. It will be readily appreciated that other such sequences of key depressions could be used. Further, it should be appreciated that the microprocessor of FIG. 2 can accomodate the simultaneous depression of several keys; however, not all microprocessor or calculator chips are capable of properly decoding the simultaneous depression of several keys and thus, in that case, with such microprocessor or calculator chips, some unusual sequence of single key depressions would preferably be selected. However when using a microprocessor or calculator chip capable of decoding multiple simultaneous key depressions, we prefer that the unique sequence include such simultaneous depressions inasmuch as such depressions are usually not intentionally made when operating a calculator. This is especially true in the foregoing example which includes the simultaneous depression of five keys.

In the foregoing unique key sequence, there is included the depression of a number key. In this embodiment of our invention, the period of time between the repetitive actuations of the printer or other output device may be selectively controlled; that is, inputting a zero results in minimum delay between actuations of the output device while inputting the number nine results in a delay of several minutes with several steps in between corresponding to the depression of other number keys in this sequence. Of course, those practicing the present invention may desire that the delay between the repeative actuations of the output device be at some fixed, predetermined delay (or no delay) as opposed to being selectable according to the number inputted during the unique key sequence.

At block 101 in flow chart of FIG. 3, the printing or output register, which is located in a predetermined portion of RAM 25, is loaded with a plurality of numerals 8's. Thus, when the calculator is caused to enter its self-exerciser mode (that is, its "burn-in" testing mode) the output device or printer is caused to print the contents of the printing register, which, in this case, causes the printing of a plurality of numeral 8's each time it is actuated. Of course, the printing register may alternatively be loaded with other preselected numerals or with alphabetic character information or with characters entered at keyboard 3, if desired. However, we load the printing register in RAM 25 with a plurality of numeral 8's inasmuch as an eight is a symmetrical character (thereby simplifying the observation of faulty printing) and results in energization of all thermal printing mesas when arranged as a linear array.

At block 102, a key code for the self-exerciser program is loaded into the next location in the key stack memory. The key stack memory is a first-in, first-out type memory which stores a plurality of two digit key codes. Each key at the calculator's keyboard has a unique two digit key code associated therewith and, in addition, the burn-in subroutine program has its own two digit code which is different from that of any of the key codes associated with the keys on the calculator's keyboard. The use of first-in, first-out key stack permits the calculator to remember a series of key depressions occurring faster than the calculator can respond to the key depressions. This is useful in printing calculators where the operator of the calculator may tend to input data via the keyboard when the calculator is in a printing mode for instance.

The code in the next location in the first-in, first-out key stack is then transferred either directly or indirectly to program counter 36 for accessing a subroutine in ROM 24 when the subroutine associated with the previous key code has been completed. When, the code for the burn-in subroutine is subsequently read from the first-in, first-out key stack, then the program will automatically branch to the point between blocks 100 and 101. As will be seen, making use of the first-in, first-out key stack for repetitively calling this subroutine permits the calculator to make convenient use of its normal supervisor or operating system.

At block 103, a test is made of whether or not the first line has been printed. This is preferably done by setting (or resetting) a flag and branching around block 104 only if the first line has not yet been printed in response to decoding the unique key sequence at block 100. During the unusual key sequence of block 100, it is previously indicated that a numeral key may be depressed to indicate the length of time to occur between actuations of the printer. This is accomplished, for instance, at block 104, by loading the numeral depressed during the unique key sequence into the most significant digit location of a counter and then decrementing that counter until it reaches zero. Upon reaching zero, then printing may occur. Of course, if the number inserted is zero then the delay will be zero. Alternatively, of course, the delay may be of a preselected value (including zero) rather than corresponding to some numeral entered during the unique key sequence.

The test made at step 103 is used in conjunction with the delay associated at block 104 because when delays (and especially long delays) are generated at step 104 we find it preferable that the first line of printing occur immediately in response to the decoding of the unique key sequence at step 100 rather than waiting for the calculator to first complete a long delay before performing the first printing operation. We chose to have the first line printed immediately, as opposed to waiting for the delay, so that an operator inserting the unique key sequence at block 100 knows immediately whether or not the sequence has been entered properly.

After block 104, printing at step 105 occurs using the calculator's normal printing routine for printing the contents of the printing register. By branching immediately to the normal printing routine at step 105 we avoid the addition of additional instruction words to the ROM for testing the status of the printing, decoding the contents of the printing register for printing and so forth. Upon completing the line of printing under control of the calculator's normal supervisory or operating system, it then reads out the key code at the "next location" in the key stack at step 106. Of course, at the "next location" is the code for the self-testing routine which was previously inserted in the "next location" at step 102 thus causing a branch back to the point in the program between blocks 100 and 101, the branch or loop being indicated by numeral 107.

It will be appreciated by those skilled in the art that the order of steps of 101-105 may be altered, if desired; however, certain alterations may not always make the best use of the calculators existing operating or supervisory system, should those practicing our invention decide to make use of such operating of supervisory systems. Thus, step 102 could be accomplished either before step 101 or as late as after step 105. Step 105 could be performed before step 104, and which would, in addition, eliminate any need for step 103 inasmuch as the first line would be printed before delay would be generated at step 104.

It should be appreciated that using the self-testing burn-in program described with reference to FIG. 3 results in a desensitization of the microprocessor chip to entries made at the calculator's keyboard inasmuch as the branch made at block 106 based on the contents of the next location in the first-in, first-out key stack because the key code at that location is controlled by block 102 rather than by entries made at keyboard 2. The calculator may be simply returned to its normal condition (i.e. not in the burn-in test mode) by de-energizing and then re-energizing the calculator.

Referring now to FIG. 4, there is shown another embodiment or invention. At step 110 the unique key sequence is decoded much in the same manner as was done at step 100 (FIG. 3). Upon decoding the unique key sequence, the printing register in the calculator is loaded with a desired alphanumeric code, such as a plurality of eights, much in the same manner as was done at step 101 (FIG. 3).

At step 112 the contents of the printing register is printed according to a series of instructions outputted from the ROM. These instructions cause the contents of the printing register to be decoded for energization of the linear array of thermal heaters. These instructions preferably include the instructions for stepping the platten 2.1 as the mesas are energized so that a line of characters is printed. For example, the array of mesas are selectively energized as the thermally sensitive paper is stepped passed the array; in one embodiment, the thermally sensitive paper may be stepped seven times for each line of characters to be printed and a width of five mesas may be used for printing a single character so that a set of alphanumeric characters may be printed within the bounds of a five by seven block of dot producted on the thermally sensitive paper by heating of the mesas.

After completing the printing operation at step 112, the operations at block 113 are accomplished for delaying the next operation for some selected or predetermined period of time. This may be done in much the same manner as the delay was generated at step 104 (FIG. 3). Upon completing the delay at block 113, a branch, indicated by line 114, occurs to block 111 where the instructions for loading the printing register are located. Of course, if during the printing operation at block 112 the contents of the printing register are not destroyed, then the branch after block 113, represented by line 114, may be made directly to the instructions for printing one line, at block 112, in lieu of reloading the data into the printing register at block 111.

In Table I (which comprises Tables I-0-0 through I-0-15 and Tables I-1-1 through I-1-15) is listed the set of instructions which may be stored in the read-only-memories 24A and 24B of the microprocessor described with reference to FIG. 2, which instruction set provides a printing calculator of the type shown in FIG. 1 with the burn-in test mode described with reference to FIG. 3. Referring now to Table I, there are several columns of data which are, reading from left to right: PC (Program Counter), INST (Instruction), BRLN (Branch Line), Line, and Source Statement (which includes name, title and comments). In the microprocessor of FIG. 2, the read-only-memories are addressed with a seven bit address in the program counter, a four bit address in ROM page address register 46 and according to the state of chapter latch 33a. The instructions listed on Table I-0-0 correspond to Chapter 0, in the microprocessor, while the instructions listed in Table I-0-1 are those of Chapter 0 and so forth through the instructions in Table I-0-15 which are stored of Chapter 0 in the microprocessor. Similarly, the instructions listed on Table I-1-0 correspond to Chapter 1, in the microprocessor while the instructions listed in Table I-1-1 are those of Chapter 1 and so forth through the instructions in Table I-1-15 which are stored in Chapter 1 of the read-only-memories in the microprocessor of FIG. 2.

The program counter of the microprocessor of FIG. 2 is preferably comprised of a feedback shift register and therefore counts in a pseudorandom fashion, thus the addresses in the left hand column of Table I, which are expressed as a hexadecimal number, exhibit such pseudorandomness. If the instructions starting at Chapter 0 were read out sequentially from the starting position in program counter (00) then the instruction would be read out in the order shown in Table I. In the "line" column is listed a sequentially increasing decimal number associated with each source statement and its instruction and program counter address. The line number starts at line 12 for reason of convenience not important here. When an instruction requiring either a branch or call is to be performed, the address to which the program counter will jump, the page number to which the page register will jump, if required, and the status of the chapter latch is reflected by the binary coded comprising the instruction or instructions performing the branch or call. For sake of convenience, however, the branch line column indicates the line number in Table I to which the branch or call will be made. The title in the source statement is a mneumonic for the instruction associated therewith. The comments column shows the names which have selected for branch routines, the values of various constant fields in the instruction and other comments made by the person who developed the set of instructions. The name column lists the names given to subroutines called by call or branch instructions.

In Table 2 there is a listing of the various instruction types, their mneumonic names and the functions performed in response to these instructions. The instructions generally correspond to the instruction set listed in U.S. Pat. No. 3,988,604 with modifications to permit three bits as opposed to two bits to be inserted into the RAM page address registers 73 and an instruction to permit the chapter latch 33a to be complimented. Since the instruction set listed in U.S. Pat. No. 3,988,604 is already fully populated, various instructions listed therein have been deleted to make room for the additional instructions required for the chapter latch and the extra bit in the RAM page address register. Of course, some of the decoders coupled to bus 33 in the microprocessor of FIG. 2 and U.S. Pat. No. 3,988,604 need to be modified to properly decode the instructions of Table II. Inasmuch as these decoders are preferably programmable, the decoder should be appropriately programmed at the same time the instruction set is loaded into ROMs 24a and 24b of the microprocessor of FIG. 2.

We have described our invention in connection with certain specific embodiments thereof. It is to be understood that modifications may now suggest itself to those skilled in the art and this is invention is not limited to the specific embodiments disclosed, except as set forth in the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6##