Transistor Bias Circuit

This invention relates to a bias circuit for a transistor, and more particularly to a bias circuit for a microwave field-effect transistor.

A field-effect transistor (FET) is more difficult to bias than bipolar transistors. This is particularly true of a gallium arsenide (GaAs) microwave FET because the gate-to-source voltage, V.sub.gs, is frequently comparable to and sometimes larger than the drain-to-source voltage, V.sub.ds, whereas most biasing schemes rely upon the latter being much greater than the former.

Biasing of a GaAs FET can be achieved in a conventional manner by selection of resistors, or by potentiometer adjustments, but such conventional biasing has the disadvantage of being temperature sensitive, and often expensive, unreliable, or time consuming to adjust. An object of this invention is to provide a biasing circuit for a FET.

In exemplary embodiments of the invention, a constant bias voltage and current is provided for a transistor by the combination of two resistors in series between common and output electrodes of the transistor, namely the source and drain electrodes of an FET, and the emitter and collector electrodes of a bipolar transistor, and means connected to a source of direct current voltage for maintaining a predetermined voltage across the one resistor connected to the output electrode, thereby to produce a constant current through that one resistor. The common electrode of the transistor is connected to the source of constant current by a means selected for maintaining the desired bias current through the transistor. A signal to be amplified is applied to a third (control) electrode of the transistor.

The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings.

FIG. 1 illustrates a conventional circuit utilizing a feedback voltage regulator to maintain a constant voltage across one resistor thereby to produce a constant current through a second series resistor, thereby to produce a regulated voltage across the two series resistors.

FIG. 2 illustrates the novel application of the circuit of FIG. 1 to bias an FET.

FIG. 3 illustrates a variation of the bias circuit of FIG. 2.

FIG. 4 illustrates the novel application of the circuit of FIG. 3 to bias a bipolar transistor.

FIG. 5 illustrates of two FETs in cascade with the bias circuits of FIGS. 1 and 2.

Referring now to FIG. 1, a 3-terminal feedback voltage regulator 10 is shown with an input terminal 1 adapted to be connected to a source of direct current voltage, and its control and output terminals, 2 and 3 respectively, connected to ends of a resistor 11. The regulator thus connected is floating in that it maintains a constant voltage, V.sub.REF, across the resistor 11. As a consequence, a constant current, I.sub.1, is maintained from the output terminal through a second resistor, or potentiometer, 12 to maintain a substantially constant output voltage, V.sub.OUT. The adjustment current I.sub.ADJ from terminal 2 is negligible so that it will not affect the output voltage V.sub.OUT or constant current I.sub.1. The output voltage is given by ##EQU1## National Semiconductor Corporation produces such a feedback voltage regulator (FVR) as a 3-terminal adjustable regulator LM117 capable of supplying in excess of 1.5 amperes over an output voltage range from 1.2 V to 37 V. However, any 3-terminal feedback regulator with negligible feedback control current I.sub.ADJ would be acceptable for the present invention.

The voltage regulation circuit of FIG. 1 is employed in a novel manner to provide bias (voltage and current) for a field-effect transistor Q.sub.1 in a circuit as shown in FIG. 2. For convenience in understanding this bias arrangement, the same reference numerals are employed for elements in this bias arrangement common to the circuit of FIG. 1. Additional elements are a small resistor, or potentiometer 13 and a capacitor 14. The resistor 13 is chosen, or set, for the desired bias current. The object of the bias arrangement is to provide a constant drain-to-source bias voltage, V.sub.ds, and current, I.sub.s. The drain-to-source bias voltage is thus given by the following equation (neglecting I.sub.ADJ):

The bias current I.sub.s, i.e., the current through the source electrode of the field-effect transistor, is given by the equation

where I.sub.c is the constant current of the resistor 13. The capacitor 14 is to provide an rf ground and frequency compensation of the FVR. The value of resistor 13 depends upon the characteristics of Q.sub.1 and upon the current through resistor 12. Accordingly, resistors 12 and 11 are made large compared to 13 so that 13 and Q.sub.1 more precisely fix the current through Q.sub.1. A transistor biased in this manner will amplify an input signal and provide an output signal which may be DC coupled to another amplifying stage, as described with reference to FIG. 5. The signal input terminal is preferably connected to ground through an RF choke, as represented in FIG. 2.

FIG. 3 illustrates a second embodiment, or variant, of a circuit for biasing a field-effect transistor Q.sub.2. Elements common to the embodiment of FIG. 2 are identified by the same reference numerals. The variation is the use of a feedback voltage regulator 15 with a feedback resistor 16 to provide a constant current.

FIG. 4 illustrates the application of this biasing circuit to a bipolar transistor Q.sub.3. For convenience, the same reference numerals are used as for the biasing circuit in FIG. 3 from which it can be seen that the same circuit can be applied to a bipolar transistor as well as to a FET. The same applies to the biasing circuit of FIG. 2 which differs only in the implementation of the constant current source.

Referring now to FIG. 5, transistors Q.sub.1 and Q.sub.2 of FIGS. 2 and 3 are shown, with their biasing circuits, connected in cascade. This illustrates one advantage of the present invention, which is that the two transistors may be directly coupled, i.e., connected with a DC coupling. Diodes CR.sub.1 and CR.sub.2 protect the gate electrode of the transistor Q.sub.2 against forward bias if accidental shorting to ground occurs. Such an accidental shorting may occur while tuning if these cascaded amplifiers are used in a microwave system with GaAs microwave FETS. An alternative might be the use of a Zener diode in place of the diode CR.sub.2, and another alternative might be the use of a Zener diode from the gate to the source of the transistor Q.sub.1 to protect against occurence of shorts and oscillations during tuning. Any of the resistors could be placed in series or parallel with a temperature sensitive element (or replaced by a temperature sensitive element) to achieve a specific type of temperature compensation. The amplifier circuit requires only a single unregulated supply. It is explicity designed for a direct coupled stage of amplification. Additional similar amplifier stages could easily be added by direct coupling. For some applications, the transistors could be bipolar transistors.

Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art. For example, the embodiments disclosed herein have assumed a common source electrode configuration. However, it should be readily understood that the invention is also applicable to common drain of common gate configurations and it is therefore intended that the claims be interpreted to cover such modifications and variations.