Demand Publishing Royalty Accounting System for an Electrostatic Copier

The widespread use of document reproduction facilities such as the ubiquitous photo copier and, to a lesser extent, the microfiche duplicators has created a significant problem to present royalty accounting systems. These copying facilities have found widespread use primarily because of their convenience for the "fair user" such as students and researchers who seek a single copy of a copyrighted document. Unfortunately, these copiers provide the same convenience for the mass copying of documents by copyright infringers and the present non-automated systems of royalty accounting are not capable of dealing with this problem.

Recent progress has been made in establishing universal numbering standards to permit a digital coding of documents; the standard book numbering system comprises a ten-digit number and the standard serial numbering system provides a seven-digit number that records group identification such as national, geographic, or language information, publisher identification and title of the copyrighted document. The raw copyright data is, therefore, already adapted to a numerical code intended for automated digital processing.

Rapid scanning of digital information has also been developed in the bar code and optical decoding devices such as an optical wand and the like for receiving and inputting numerical data to digital processors. It is, therefore, not surprising to find that others have suggested that the universal book and serial numbering systems be reduced to a bar code on the copyrighted document and that copying facilities at document storage locations such as libraries and the like be provided with an access control system requiring the input of the digital copyright information from a bar code to enable the copying machines for reproduction of the copyrighted document.

The access control systems which have been suggested by others, however, lack adequate input capability to permit a convenient and widespread usage. Ideally the access control should provide for receiving input user information data by a manual keyboard or by an optical bar code and the like. Additionally, the system should provide for the automated recording and storage of the transaction data as well as for the transmission of the data through a data terminal by use of an acoustical coupler and the like to permit use of telephone facilities to communicate to remotely located central accounting offices.

This invention comprises an automated transaction accounting system for copyrighted documents such as microfiches and the like. The system includes a microfiche copier such as a microfiche duplicator and/or a hard copy printer; a copier access control system for the input of transaction data through a transaction data terminal including an optical wand and the like for processing of bar coded document and/or user identification and a manual keyboard for input of information such as the date of the transaction, number of copies, user identification, etc. The system also includes enabling means to access the microfiche copier upon the successful completion of the data input with data recording means such as magnetic and/or paper tape recorders to record and store the transaction data. Preferably the system includes a data terminal and has a data transmission sequence mode to permit communicating of stored or simultaneously entered transaction data with a royalty accounting system. In the preferred embodiment, the data terminal includes an acoustical coupler to permit the direct use of telephone lines for communication to remote royalty accounting offices.

The invention will be described with reference to the figures of which:

FIG. 1 is a view of a typical installation of the invention;

FIG. 2 is a view along lines 2--2 of FIG. 1;

FIG. 3 is a simplified block diagram of the transaction accounting system;

FIG. 4 is a block diagram of the AC power distribution of the system;

FIG. 5 illustrates the low voltage power distribution used in the system of the invention;

FIG. 6 is a firm ware block diagram of the control electronics of the system;

FIGS. 7a, 7b, 8 and 9 illustrate the system control electronics;

FIG. 10 is a schematic diagram of the control box interface;

FIG. 11 is a schematic diagram of the front panel controls interface;

FIG. 12 is a circuit diagram of the keyboard interface;

FIGS. 13a, 13b and 13c are a circuit diagram of the display interface;

FIG. 14 is a circuit diagram of the printer interface;

FIG. 15 is a schematic diagram of the output interface;

FIG. 16 is a block diagram of the magnetic tape interface;

FIG. 17 is a block diagram of the control logic of the magnetic tape interface;

FIG. 18 is a block diagram of the encoder-decoder for the magnetic tape;

FIGS. 19, 20a and 20b are the circuit diagram of the cassette interface of the system;

FIG. 21 is a circuit diagram of the bar code reader interface; and

FIG. 22 is a circuit diagram of the EIA interface of the system.

Referring now to FIG. 1, the transaction accounting system of the invention is shown together with the microfiche copying facilities, access to which is controlled by the invention system. As there illustrated, the complete system includes a xerographic microfiche printer 10, a microfiche duplicator 20, an acoustic coupling data terminal 30; a bar code reader 40; a control panel 50, and system electronics housed within a console 70. The system is conveniently provided with a mating console 73 for storage and for support of the table 72.

The xerographic microfiche printing system is a conventional microfiche hard copy printer such as that marketed by Xerox Corporation, Model 970 MPS which includes a front control panel 12 for selection of the number of copies desired and a panel 13 for selection of the microfiche frame to be copied. The microfiche to be copied is loaded into a transport carriage 14 that correctly orients the selected microfiche frame to the optical input system that includes projection optics such as a projection lamp, projection lens and reflecting mirrors to image the selected microfiche plane to a location where it is scanned by the copier onto a photoconductive surface, all contained within the housing 15 of the hard copier 10. The blank paper storage for the copier is in bin 16 and the hard copies are delivered to a collection bin 17. Further descriptions of suitable copy systems can be found in U.S. Pat. No. 3,373,653 to R. R. Roberts et.al. and U.S. Pat. No. 3,400,631 to R. C. Rauscher.

The microfiche duplicator of the invention comprises a conventional duplicator such as that available as Bruning Model OP11 cut microfiche duplicator. This duplicator 20 has a hinged cover 21 on a base 22 to permit loading of the microfiche in cavity 23 and has a front panel control 24 for selection of the appropriate development intensity. The duplicate microfiche is processed through the right hand side 25 of the duplicator and is delivered through output slot 26 of the duplicator.

The data terminal is a commercial acoustic data coupling device available from Texas Instruments as model Silent 700 data terminal. It is intended for the acoustic coupling of transaction data through a conventional phone receiver hand set 31 and telephone transmission lines to a remote accounting system.

The optical bar code reader 40 includes a platform 42, preferably inclined to table 72, for support of a conventional microfiche document and an optical wand 43 used for reading conventional bar coded information. Control panel 50 includes a digital display panel 51, power indicator 52, a digital keyboard 53, and a sequence mode selector panel 60.

The consoles 70 and 73 which provide for storage of the electronic components of the system and/or accessory equipment include slide drawers 71 and hinged front doors 74.

Referring now to FIG. 2, the data input and selector control panel will be described in greater detail. As there illustrated, a standard 98-page, silver-gelatin microfiche 41 rests on support platform 42. The microfiche is provided, in its upper right hand corner, with a bar code 44 which comprises document information encoded in a standard, universal product code form. Information which is thus encoded can comprise the digital standard book numbering system a, ten-digit number providing group identification of the document such as its national or geographical origin and language; publisher identification and document title together with a standardized check digit. Similar information is provided for periodicals or journals using the standard serial numbering system which includes a seven-digit informational code and a check digit.

The bar code reading means can be a rapid scanning means or, more conveniently, an optical wand 43 which is a hand held tool adapted to be manually moved across the bar code 44 for sensing the coded information with an optical system that is electronically processed into digital information and passed through cord 45 to the system electronics.

Adjacent the bar code reader 40 is the control box 50 of the transaction accounting system. The upright front panel 54 of the control box includes a twelve digit LED display panel 51 and a power indicator 52. The forward deck 55 of the control box has a horizontally inclined cover in which are mounted a digital, calculator type keyboard 53 that includes a key 56 for correction of data input and a delete key 57 for recording negative transactions, in a manner hereinafter described, necessitated, e.g., when illegible copies are produced.

The remainder of the front deck 55 receives the sequence mode selector panel 60 which includes start button 61, a ready indicator 62, indicator 63 to warn the operator that insufficient recording tape is in storage, a stop button 64, a hard copy select button 65, a microfiche duplicator button 66, a transmit mode selector button 67 and an override button 68 permitting enabling of the copying machines 10 and 20 without input of the transaction data.

FIG. 3 is a simplified block diagram of the transaction accounting system showing the functional interconnections of the various parts of the system. The control electronics 80 is connected through interface 81 to control box 50, previously described. The transaction data are recorded on suitable means such as a paper tape printer 82 which is provided with a power supply 83 and connected to the control electronics through printer interface 84. Other recording means can be used instead of or besides the aforementioned paper tape printer, including a conventional magnetic tape recorder 85 such as a conventional cassette recorder that is connected to the control electronics through interface 86.

The microfiche copying means can include the aforementioned xerographic hard copy machine 10 and/or the aforementioned microfiche duplicator 20 that are connected to the control electronics 80 through output interface 87. The communicating device such as the data terminal 30 is connected to the control electronics through the EIA interface 88.

Referring now to FIG. 4, the AC power is supplied to console 70 through a receptacle on the back side of the console. The live power line 90 is provided with a circuit breaker on-off switch 91 locatd on the front of the console behind door 72 while the access door to the rear of the console 70 has an interlocking switch to disconnect the AC power when the access door is opened. Line 92 provides a chassis ground for the electronics and capacitor 93 and a line filter 94 are provided for EMI considerations. A low voltage power supply 95 of .+-.12 volts DC is provided by a conventional voltage regulator (AC/DC Electronics ET 401-11) and a similar voltage supply 96 is provided for a .+-.5 volt DC power supply. The latter unit is AC/DC Electronics EC 5 N31. The printer power supply 97 is provided at the line AC voltage.

Referring now to FIG. 5, the low voltage power distribution is shown with the low voltage power supply 95 connected to the indicated terminals 89 of the bar code reader printed circuit board and, with the 5 volt power supply 96 connected to the main electronics panel 99 at the identified terminals. The power supply 95 is also connected across terminals 1 and 2 of the control box 50.

Referring now to FIG. 6, the firm ware block diagram for the control electronics will be described. The control electronics employs the Motorola 6800 microcomputer family of devices and includes the microcomputer clock M6870 and buffer drivers. As shown in FIG. 6, the control electronics includes the microprocessor unit 100, a 256 byte ram 101, a 3K byte PROM 102 and interface adapters 103-107 which are interconnected by address bus 108, control bus 109 and data bus 110. Address bus 108 has 16 lines and is output only in terms of the microprocessor unit 100. The data bus is bidirectional and has eight lines to transfer data to and from the memory and peripheral adapters 103-107.

Referring now to FIGS. 7 and 8, the control electronics identified as block 80 in FIG. 3 will be described in greater detail. As shown on FIG. 7a, the microprocessing unit 100 receives two clock signals from system clock 112 which is a crystal controlled oscillator in a high-bred module requiring no adjustment. This clock operates at 1 MHZ. The system busses described with regard to FIG. 6 are shown in the illustration wherein the 16-line address bus 108 is connected to the output terminals of the microprocessor unit 100 through buffer registers 114-116 which extend the drive capability to the microprocessor unit address bus. The necessary address decoding to generate the proper chip select signals for the enabling devices requiring such signals is accomplished by the address decoding section which includes inverters 118-122 of FIG. 7b, inverter 128 of FIG. 7a and the NAND gates 124-129 of FIG. 7b. The system memory map set forth in the following table gives the various locations in memory of the devices in this section which is accessed by the proper address code on the address bus and by signals from the control bus that are used in the generation of the device enable signals hereafter mentioned.

The eight-line bidirectional data bus 110 of FIG. 7b transfers data to and from the memory and peripheral devices. The registers 130-132 of FIG. 7a are used as bidirectional bus extenders and the direction of data flow in data bus 110 of FIG. 7b is controlled by the Read/Write R/W signal from the microprocessor unit 100 of FIG. 7a. When this signal is high the microprocessor unit is in the read state to receive input data and when the signal is low the microprocessor unit is in the write state for data output.

The control bus 109 of FIG. 7b carries the remainder of the signals including the PROM 1, 2 and 3 enabling signals shown as P1E, P2E and P3E from the decoding section, the R/W signal, the valid memory address signal (CS1), the IRQ, interrupt request signal, enable, reset, etc.

Referring now to FIG. 8, the subsystems of the transaction accounting system are connected to the microprocessor section through the peripheral interface adapters 102-107. Each of these peripheral interface adapters consists of two bidirectional eight-bit peripheral busses and four control lines. These interface adapters appear as memory locations to the microprocessor unit 100 and are accessed by a combination of the proper address and necessary enable signals carried on the address bus 108 and control bus 109, respectively. The functional configurations of the peripheral interface adapters are programmed by the microprocessor unit 100 during the initialization of the transaction accounting system.

The schematic diagram of the microprocessor section, FIG. 7a, shows only the connections used by the microprocessor unit to interface with the peripheral interface adapters. The two eight-bit data busses and four control lines are shown on the schematic diagrams of each of the respective subsystem interfaces, FIGS. 10-14, and 19-22 described hereinafter.

The interface adapter 107 is an asynchronous communications interface adapter to provide data formatting and control to interface serial, asynchronous data communications information to the microprocessor unit 100; its functional configuration is also programmed by the microprocessor unit 100 during the system initialization. At that such time, variables such as word length, clock division ratios and transmit-receive controls are established. The interface adapter 107 appears as memory to the microprocesser unit 100 and is accessed accordingly.

Referring now to FIG. 9, there is shown a monostable multivibrator 133 which provides a master reset pulse (MR) when power is applied to the system. The rising power supply voltage is sensed and when it reaches the proper level a pulse of approximately 50 MS is generated and is used throughout the sytem to initialize the circuitry.

The application of power to the control circuitry generates the master reset pulse and, after a slight delay, the system clock 112 begins operation. The duration of the master reset pulse allows a minimum of eight complete clock cycles to occur before enabling the microprocessor unit 100 and the remaining system components. The trailing edge of the master reset pulse causes the microprocessor unit 100 to begin a reset sequence. At such time, the contents of the last two locations in memory are loaded into the microprocessor units; these are addresses FFFE and FFFF and are located at PROM unit 102b (refer to the system memory map, Table 1). The starting address of the operating software is stored in these locations and the microprocessor unit begins system initialization. During this phase of the operating system the various interface adapters are configured and the microprocessor unit prepares itself for normal system operation.

Upon completion of the system initialization, the microprocessor unit 100 goes into a standby mode of operation. Because of dynamic characteristics of the internal registers, the microprocessor unit activity never completely halts and this mode of operation is actually a "wait-for-interrupt" mode operation during which the microprocessor unit 100 is performing several software tests.

The microprocessor unit is interrupt driven out of the standby or wait mode of operation in response to an activity occurring in one or more of the subsystems such as an interrupt resulting by an operator pressing a control panel switch. When the microprocessor unit senses an interrupt it begins a polling sequence to determine the source of the interrupt by reading the interface adapters 102-107 in a predetermined sequence. Once the microprocessor unit 100 determines the source of the interrupt signal, the program control passes to the appropriate subroutine to complete the operation. Upon completion of the operation, the microprocessor unit 100 resumes its standby or wait mode of operation.

FIG. 10 is a block diagram of the control box interface. The interface consists of four parts which are the keyboard 53, the light pen 43, the display panel 51 and the front panel sequence mode selector controls and indicators which are grouped as elements 60 in FIG. 2 and which include controls 61, 64 and 65-68, indicators 62 and 63 and indicating lights associated with controls 65-68.

Peripheral interface adapter 105 interfaces this section with the microprocessor unit. The signal lines PA0-PA7 comprise the eight-bit input data bus while signal lines PB0-PB7 provide an eight-bit output data bus. Signal line CA2 receives the interrupt signal from NOR gate 134 which receives the interrupt command from keys 53, wand 43 or the control panel. Signal line CA2 carries the output signal to device 135 indicating the microprocessor unit response to the interrupt input signal. These two signals are active for the data input into the microprocessor unit section. Signal line CB2 is used to indicate data ready when the microprocessor unit section has output data to provide to the control box interface.

The data that is passed to and from the microprocessor unit section and the control box interface is all numerical in form. As a result, only the low order bits PA0-PA3 for the input case and PB0-PB3 for the output case are required to form a data word. The high order bits PA4-PA7 and PB4-PB7 are used as simple addresses or control functions.

The schematic diagrams of the sections which individually comprise the control box interface elements are described in greater detail hereinafter with reference to FIGS. 11-13 and 21 and include the following table showing the function of the low order bits and the appropriate address bit for that section. The bits used for the control functions are also shown in the table.

The following table summarizes the bit assignment:

The front panel control section will be described with reference to FIG. 11 which is the schematic diagram of this section. The section contains the necessary switches and indicators to permit control of the system operation and display of the status of the system.

The following tables set forth the bit pattern of the four bit data word associated with each switch or indicator. The switches are all momentary push-button types that use solid state circuitry to generate a TTL level to indicate a contact closure. The indicators are part of the switches except for indicators 62, 63 and 52 which are indicators alone.

Device 140 is a decoder that senses the switch outputs and generates the four-bit data word associated with each switch function. The data words generated are passed through inverters 141-144 to the quad latch 145. The positive OR gate 146 senses any change in the output of the decoder 140 and generates a clock signal to store the data word in the quad latch 145. A clock signal also causes flip flop 147 to set. The output of flip flop 147 sets the interrupt signal CA1, address bit A4 and enables the tri-state output of the quad latch 145. The microprocessor unit 100 reads the data word in response to the interrupt signal and clears the flip flop 147 which resets the output.

With the exception of the power on indicator 52, the microprocessor unit 100 has control of the status of each indicator. Quad latch 148 has double rail output and stores the four-bit data words sent from the microprocessor unit section. The Nand Gates 150-157 are used as decoder drivers to decode the data word and turn on the proper indicator through their respective transistors 158-165. The microprocessor unit 100 has control of the ready indicator 62 by use of the address bit B4 and flip flop 166. This is provided to permit the proper combinations of mode and status to be maintained while operations indicated by the ready indicator are occurring.

The schematic diagram of the keyboard section interface is FIG. 12. The keyboard section is used for data input only and the data board itself is a standard 12 position (4.times.3) type having a calculator format; see FIG. 2. The switches used in the keyboard or solid state devices which require no debouncing. A TTL-level signal is generated whenever a key has been depressed.

The keyboard interface circuit is provided with an RC oscillator 170 formed of discrete parts including Nand Gates 171-173 and an RC network of resistors 174, and 175 and capacitor 176. The output of the oscillator is connected through lead 177 to a binary counter 178. Counter 178 drives a 16-1 data selector 179 that sequentially looks at the 12 keyboard output lines. When a key is depressed, its corresponding output line goes high and the output of the 16-1 data selector 179 goes high when the selected keyboard output line is encountered by the scanning sequence. This action causes the scan oscillator 170 to stop which stops the binary counter 178. The four-bit data word present at the output of the binary counter now represents the value assigned to the key that has been depressed. The four-bit data word is also connected to a data register 180.

The output of the scan oscillator 170 is also connected to a retriggerable, one-shot device 181. As long as this scan oscillator 170 is running (no keys depressed) the one-shot is continually retriggered and its output remains low. When the scan oscillator stops the one-shot is allowed time out which results in its output going high. This signal going high causes the data register 180 to store the four-bit data word from the binary counter 178. The signal also sets flip flop 182. Flip flop 182 generates an interrupt signal to the microprocessor unit section, sets bit A7 high indicating the keyboard interface and enables the tristate output of the data register 180. The microprocessor unit 100 reads the control box signal P1A as a result of the interrupt and the eight-bit data word containing the key word information and address is passed to the microprocessor unit section for processing. The microprocessor unit action of reading the control box signal P1A may also cause signal CA2 to go low for approximately one machine cycle. This signal going low clears the flip flop 182 which turns out the output of the data register 180. This completes the operation of passing the information represented by depressing a key to the microprocessor unit section for processing.

FIGS. 13a, 13b and 13c are the schematic for the display section interface. The display section consists of a twelve digit gas discharge display panel 51 and associated circuitry. The display panel is designed for multiplex operation with all like cathode segments bussed internally. Each anode has its own external connection. The display panel 51 requires an ionization voltage of approximately 170 volts which is supplied by a DC to DC converter 190. The voltage divider 191 of FIG. 13b across the output of the converter provides bias voltages to insure the digits are below the ionized level when deselected. Characters are displayed by successively applying positive signals in sequence to the anodes corresponding to each of the digit positions. At the same time the appropriate cathode segment busses are switched to near ground.

The two stable multivibrators 192 and 193 of FIG. 13a generate approximately 7 KHz. scan frequency whose output clocks a binary counter 194. The counter outputs provide the inputs to a four to sixteen decoder 195. The thirteenth output pulse from decoder 195 is fed back to reset the counter 194. The resultant twelve sequential pulses are capacitively coupled to anode drivers 196 and 197 of FIG. 13b and the twelve digit position buffer drivers 212 and 213 of FIG. 13a, drivers 214-220 of FIG. 13b, and drivers 221-223 of FIG. 13c. Display cathode blanking is obtained by running the scan oscillator output through two cascaded monostable multivibrators 198 and 199 of FIG. 13a to provide a cathode drive signal that has an approximately 25 microsecond leading edge and 50 microsecond trailing edge blanking interval relative to the anode digit select pulse. The four bit data words sent to the display section are stored in the quad latches 200-211 of FIGS. 13a, 13b and 13c. There is one quad latch for each digit position and the output of each latch is fed to its corresponding driver 212-223. The anode digit select pulses are used to sequentially enable the appropriate buffer drivers. The like outputs of the twelve buffer drivers 212-223 are connected together and the resultant four lines 224-227 are the input to the BCD to seven segment cathode decoder driver 228.

Flip flop 229 and counter 230 of FIG. 13a are used to count the number of characters being displayed and to provide a leading zero supression feature. The number of characters being displayed is continually compared with the output of the anode digit position counter 194 by a four bit magnitude comparator 231. Anytime the anode digit position count exceeds the display character count the display is blanked. When the display has been cleared, a zero is displayed in the rightmost digit position (position 1). The flip flop 229 is used to prevent the first character sent to the display section from upsetting the displayed characters counter 230. The display is cleared by sensing a hexadecimal value of F at the input.

Referring now to FIG. 14, the printer interface circuit will be described. The printer interface contains the paper tape printer 82 (FIG. 3) and the necessary circuitry to connect the printer to the microprocessor unit section. The printer has a drive motor 240, a solenoid coil 242 to control the paper feed, solenoid coils 243-247 to control the printing hammers, and a solenoid coil 248 to change color of the printer.

The printer uses a rotating drum and on-the-fly impact printing techniques. Each print hammer spans three columns, each column having numerals 0 through 9 and two mathematical marks which are not used in the system of this invention. There are five print hammers for a total of fifteen columns. The system of this invention employs columns 1 through 12.

Associated with each row of characters on the drum is a character pulse signal. Once, during each drum revolution, a reset pulse is generated. These two signals (character and reset) are generated by light emitting diodes 249 and 250 and photo transistors 251 and 252, for the reset and character pulses, respectively.

The printer power supply provides an unregulated 30-volt DC to the print hammers and a 24 volt AC to the drum motor. A dropping resistor 239 off the 30 volt supply provides approximately 24 volts DC to the color change solenoid 248 and to the paper feed solenoid 242. The character pulse and reset pulse are each fed to a comparator stage, 253 and 254, respectively. Each is formed of a voltage divider circuit and operational amplifier to amplify and convert the signals into pulse signals which are fed to Schmidt trigger circuits 255 and 256, each circuit of which comprises a pair of serially connected NAND gates with joined input terminals to shape up the leading and trailing edges of the pulses. The reset pulse provides the CA1 interrupt signal while the character pulse provides the CB1 interrupt signal. The eight data lines PB0-PB7 are used for output only and each line controls one of the solenoid driver devices 257-264.

The entire operation of the printer interface circuit is under program control. The operating system stored in PROM 102 includes a printer routine that performs all the necessary logic operations. The two interrupt inputs CA1 and CB1 to the microprocessor unit contain the necessary information for the printer routine. The printer power supply is turned on by the microprocessor unit section when there is data to be printed. At this time 24 volts AC is applied to motor 240 and the solenoid driver voltage is applied. Drum rotation causes the generation of the two interrupt signals which give the relative drum position to the printer software routine. Printing of the data begins when the printer routine receives the second reset pulse signal and the printer begins outputting data on the eight program interface adapter 106 data lines which signal the various printer hammers to fire and also signal the paper advance and color change solenoid drivers to fire.

When all the data has been printed, the printer routine turns the power supply off. The printer power supply contains a circuit breaker on the 30 volt DC supply line to prevent damage to the printer solenoids in the event of a failure.

The output interface shown in FIG. 15 provides the necessary circuitry to connect the microprocessor unit to external devices such as the hard copy printer 10 and the microfiche duplicator 20. The external devices connected to this section are inhibited by the microprocessor unit section until certain conditions have been met. Assuming the hard copy printing mode has been selected and the proper conditions have been satisfied, the microprocessor unit section sends an enable signal to the output interface section. Data bit PB1 from peripheral interface adapter 103 goes to a logic 1 which, with the output signal CB2, causes flip flop 270 to set. The output of flip flop 270 is fed to a peripheral driver 280 which controls a solid state, optically coupled relay 281 in the hard copy printer 10. Closure of the relay 281 contacts connects the start print switch to the start print circuitry within the hard copy printer 10 to enable the machine for use.

The coil 283 of relay 284 is connected to the copy count meter so that every time the copy count meter is implemented the contacts of relay 284 are switched. The resulting signal is fed to a S-R latch 285 which debounces the contacts. The output of the S-R latch 285 is fed to the D input of flip flop 286 and also to a monostable multivibrator 287. The output of the multivibrator 287 is a pulse of approximately 10MS which is used to clock the flip flop 286. The multivibrator 287 is used to improve noise immunity in the circuit by rejecting spurious signals.

The output of flip flop 286 is fed to the PA1 input of the peripheral interface adapter 103 and also to a three input NOR gate 288. The output of NOR gate 288 is the CA1 interrupt signal used to indicate a data ready condition to the microprocessor unit section. The microprocessor unit 100 now reads the peripheral interface adapter 103 getting the copy count data resetting flip flop 289. This entire operation repeats itself each time a copy count meter is incremented. The total number of copies is determined by the operating system software.

When the hard copy duplicator 10 has finished making all the copies requested, it goes into a shut-down mode. This causes relay 290 to energize which sends a signal to section 2 of S-R latch 285. This signal is handled exactly the same way as the copy count signal was by flip flop 289 and a second monostable multivibrator 291. When the microprocessor unit 100 reads the shut down (cycle complete) signal from the peripheral interface adapter 103 it turns data bit PB1 off which inhibits the start switch in the hard copy copier 10.

The operation of the microfiche duplicator 20 is controlled by relay 291 which responds to solenoid coil 292 to supply the power to the microfiche duplicator. This responds to an enabling signal from PB2 which causes flip flop 293 to set. The output of flip flop 293 is fed to a peripheral diver 294 to supply the operative voltage for solenoid coil 292. The completion of the cycle is initiated by the shut down mode of the microfiche duplicator 20 which energizes relay 295 to send a signal to the S-R latch 285. When the microprocessor reads the shut-down signal from the peripheral interface adapter 103 it turns data bit PB2 off which inhibits the start switch in the microfiche duplicator 20.

Referring now to FIGS. 16 through 19, the structure and operation of the casette interface is depicted. In the block diagram of FIG. 16, there is shown a peripheral interface adaptor 104 which includes an input B side from the microprocessing unit and an output A side which is linked to the cassette recorder. Signal lines CA1 and CB1 are used for interrupt control of the peripheral interface adaptor and the driver 301 and the two to one multiplexer 302 are adapted to respond to a negative signal at CB1 and CA1 respectively. CA2 and CB2 are used as outputs by the controller 300 to read information from the peripheral interface adaptor 104 and to clear registers when information has been excepted by the mircoprocessing unit. These outputs are utilized in the write strobe with E restore mode. An encoder and decoder logic unit 303 effectuates parallel to serial and serial to parallel conversion for communication between the peripheral interface adaptor of FIG. 16 and the tape transport unit. The driver unit 301 connected to the B side of adaptor 104 is used to increase the drive capabilities of the peripheral interface adaptor signals.

The controller logic 300 is depicted in block form in FIG. 17 and in greater detail in FIGS. 20a and 20b and is the logic used to control the tape transport, the sequence of the states of operation and generation of the status condition of the system mode. The controller logic 300 of FIG. 16 includes a word decoder 304 of FIG. 17 which employs a pair of NOR gates 311 and 312 of FIG. 20a connected to the input lines CB2 and PB7 of the B side of the peripheral interface adaptor 104. An inverter 313 inverts the state of the input at PB7 to the NOR gate 312. The word decoder 304 generates a strobe pulse to the encoder and decoder logic of FIG. 18 or to the remaining circuitry of the control logic of FIG. 17 depending upon the state of PB7. When CB2 is low, the status of PB7 is sampled by the NOR gates 311 and 312. A data read signal 313a is sent to the encoder and decoder logic of FIG. 18 if the state of the input at PB7 is equal to zero. On the other hand, a command read signal 314 is generated by the word decoder 304 within the controller logic of FIGS. 17 and 20 when PB7 is equal to one. The command read signal 314 acting through an invertor 317 appears at the C inputs of a right/read C-D flip flop 315 and an erase C-D flip flop 316. The command read signal 314 thereby strobes in the control bits at PB6 and PB3 to the mode 319. This establishes whether a write or read function is to occur and whether or not the tape is to be erased. If a write function is signalled, the flip flop 315 strobes another flip flop 317 in the mode control 309 to provide one input to AND gate 308. If a read function is selected, the output is indicated as a NOT WRITE MODE signal on line 319. The output at 320 from the erase flip flop 317 acts through a pair of NOR gates 321 and 322 to clock a state changing flip flop 323 in the state sequence logic circuitry 305. The Q output of the flip flop 323 clocks a state one flip flop 324 to advance to act as an input a state 2 flip flop 325. This increments the condition of the state sequence logic 305 from its initial state 1 to the second state 2.

The state sequence logic 305 of FIG. 17 includes a four bit ring counter formed by the flip flops 324, 325, 326 and 327 of FIG. 20b. The ring counter is cycled from an intial state 1 in which the output of flip flop 324 is high, through subsequent states two through four in which the outputs of the flip flops 325, 326 and 327 are respectively high. At the termination of state four the recounter is reset to state 1. Two sequence control flip flops 323 and 328 of FIG. 20a are used to generate the clock pulse for the ring counter. The control flip flop 323 is set by a signal on the preset input at 329 or by the start/stop timer 330 timing out. The timer 333 is a monostable multivibrator with a Schmidt trigger input from NOR gate 331 and with a clearing input from NOR gate 332. The control flip flop 328 is used to reset the control flip flop 323 through a NOR gate 333. An additional flip flop 334 is used to generate a reset pulse to the timer 330 through the NOR gate 332 during the read mode only. By clearing the timer 330 during the read mode by virtue of the signal from flip flop 334, the duration of state 2 is shortened so that no data will be missed if it occurs within 50 milliseconds of start up. Otherwise, the timer 330 establishes a 60 millisecond duration for state 2 to allow the tape to reach speed.

The reset decoder 306 of FIG. 17 includes two NAND gates 337 and 338 of FIG. 20a which respectively respond to the inputs PB4 and PB5 from the B side of the peripheral interface adaptor 104. An invertor 339 inverts the output of NAND gate 338. The reset decoder 306 generates a reset pulse to either the tape transport on line 340 or to the status generator 308 on line 341, or both. This determination is made depending upon whether PB4 and PB5 are high at the time the NAND gates 337 and 338 receive the command read signal 314. Reset pulses to the tape transport on line 340 clear the shut down state of the transport. Pulses to the NOR gate 342 in the status generator 308 clear the EOT/BOT (end of tape/beginning of tape) flip flop 343, thus clearing the flag signal 344 therefrom. In the mode control 309, bits PB6 and PB3 are sampled by flip flops 315 and 316 respectively when a command read signal 314 is received. The state of these bits determines whether the read or write mode is selected. The default mode is the read mode so no change is made if PB6 is zero. The mode control 309 controls the write mode output 346 and the write data block 345 emanating from the NAND gate 318 to the tape transport. Also, the write mode signal 346 and the not write or read mode signal 319 are sent to other parts of the system.

In the write mode, the write/read flip flop 315 of FIG. 20a is set high which sets the write mode signal and write mode line 319 low. The write data block signal 345 is brought low at the end of state 2, than set high after state 3, as established by the state sequence logic 305. In the erase mode, the erase flip flop 316 is set when PB3 is high. This in turn presets the read/write flip flop 315 which sets the write mode line 346 low. The write data block signal 345 is then prevented from going low by inhibiting the pulse to the clock input to the flip flop 317 through the NOR gate 347. The motion control circuit 307 is built around a four bit priority latch register 348. This latch is cleared during state 1 and state 4 by applying the Q output signals from the flip flops 324 or 327 to the NOR gate 349, the output of which is inverted by an inverter 350 and applied as an input to the latch 348. Data is latched into the register 348 when the strobe input 351 is low, as developed by the NOR gates 322, 352 and 353. Initially the status of the register 348 is cleared during state 1 and state 4 by the signal from the invertor 350. Data is latched into the register 348 when the strobe input 351 is low. The strobe input is developed by the NOR gates 322, 352 and 353. Initially the status of the register 348 is cleared and unlatched. The leading edge of the command read pulse 314 acts through the NAND gate 355 and the NOR gates 356 and 357 to set the flip flop 323 to increment the controller into state 2. This releases the clear input from the inverter 350, leaving the register in the unlatched condition. The trailing edge of the command read signal sets the flip flop 356 which latches the motion bit appearing at PB0, PB1 or PB2 into the register 348. The register is unlatched if the controller of FIGS. 17, 20a and 20b is in state 3 and either the erase mode output 320 of erase flip flop 316 is set or the gap signal is set by the gap detector 357. Either of these conditions will act as an input to the NOR gate 321a which, through NOR gates 322, 352 and 353 provide a signal at strobe input 351. The unlatched condition is gated with the output at 359 from the register 348 of the motion control circuit 307 generating a high state to increment the state sequence logic 305. When all of the outputs of the register 348 are zero, the signal at 358 will equal zero. This will cause the output of the NOR gate 359a to go high, which initiates an increment pulse to the state sequence logic 305. This method is used to terminate the read and erase modes.

The speed control section 310 of FIG. 17 controls the direction and speed of the tape by controlling the appropriate signals to the tape transport. Forward go signal 360 and reverse go signal 361 serve as inputs to the tape transport to select the direction of tape movement. The speed is controlled by the width of the pulse on one of two speed input leads 362 and 365. One of these leads carries a speed control signal which is generated by either of two one shot multivibrators 363 or 364. The multivibrator 363 fires for thirty microseconds to provide a low speed signal of ten inches per second. The high speed multivibrator fires for thirty-seven microseconds to provide a signal to drive the tape at eighty inches per second. The forward command 368 acts through the NOR gate 369, the inverter 370 and the NOR gate 366 to drive the low speed one shot 363. The reverse command acts through the inverter 371 to enable the high speed one shot 364. Another one shot 373 is used during the write mode to delay the determination of tape motion by ten miloseconds to allow the last recorded bit to pass the read head.

The write clock generator 314 of FIG. 20a employs a counter chip 376 to generate a 16 KHz squarewave for the tape transport used for timing when recording data. The counting chip 376 is driven by a timer circuit 377 that also provides a reset signal to the flip flop 328 in the state sequence logic 305.

A gap detector 357 of FIG. 20a is provided in the form of a four bit counter which is enabled only during the read mode. Initially the gap detector output 378 is set high. The first read clock pulse acts through the NOR gate 380 and clears the counter 357 indicating no gap. Each time a read clock pulse 379 is received the counter 357 is reset. The prerecorded clock pulses at 381 are counted by the gap detector 357. The condition for gap is when eight prerecorded clock pulses occur without a read clock pulse occurring.

The status generator 308 of FIG. 17 generates the bits for the status word which is passed through a two to one multiplexer 382 of FIG. 20b to the A side of the peripheral interface adaptor 104. The status generator 308 includes a series of NAND gates, NOR gates and inverters coupled together to provide the appropriate inputs as indicated in FIGS. 20a and 20b. A unit ready bit is provided by the output of NOR gate 383 of FIG. 20b if, and only if, the cassette is loaded, write tab is in place and the controller is in state 1. If either the cassette is not loaded or the write tab is removed, the ring counter of the state sequence logic 305 will stay in state 1, thus maintaining an input to NOR 383 on lead 384. Status conditions from the encoder and decoder logic circuitry of FIGS. 18 and 19 are used to generate an error signal through NOR gate 385 and invertor 386 of FIG. 20b in the status generator 308. The error bit is set if there is an over flow or parity. Parity is checked only during the read mode. A buffer ready signal 387 transmitted to the two to one multiplexer 382 is used to indicate when the controller of FIG. 17 is ready to accept data during the write mode. The clear leader signal, indicated in the status generator 308 at the output of the invertor 388 indicates the status of the optical detector in the transport. The gap detector output 378 shows the state of the counter 358 while the bit at 389 to the two to one multiplexer 382 is held high to set the word identification bit. The EOT/BOT flag 344 is set when a hole is detected by the optical detector. The flag 344 remains set until it is reset by the microprocessor. A flip flop 390 is used to set IRQA1 when a gap BOT/EOT hole is detected during a read operation by means of signals transmitted through a NOR gate 391 and an inverter 393. The flip flop 390 is reset by the acknowledge pulse 392a acting through the inverter 393 and the NOR gate 394.

The encoder and decoder logic is depicted in FIGS. 18 and 19, but also communicates with the A side of the peripheral interface adapter 104 of FIG. 16 through the two to one multiplexer 382 in FIG. 20b. With reference to FIGS. 18 and 19, the word buffer 320 and shift register 321 are connected differently in the read and write mode. All timing and data signals to the buffer 320 and shift register 321 are changed by the two to one multiplexer 382 in FIG. 20b. The state of the multiplexer 382 is controlled by the read mode signal 319. The word buffer 320 consists of an eight bit register 395. Data is clocked into the register either from the A side of the peripheral adapter 104 or from the output of the shift register 321, which is an eight bit bi-directional shift register chip 396. The output 397 of the buffer 395 is used as a register full signal, and is used as a status bit by other sections. The register full signal 397 is gated with the read mode signal 319 from the mode control 309 of the control logic 300 at a NAND gate 398. The output of NAND gate 398 is a buffer ready signal 399 which is enabled only in the read mode and which controls the two to one multiplexer 382 that is connected to the A side of the peripheral interface adapter 104 in FIG. 17. The output of the NAND gate 398 operates through a flip flop 400 to produce a read overflow error. If the system is in the read mode and if the word buffer 395 is full a strobe pulse to load the buffer is generated.

The parity generator and detector 323 in FIG. 18 includes a nine bit odd/even parity generator chip 401 and a parity detector flip flop 402. In the write mode, the parity bit is generated at 403 by the parity generator chip 401 and strobed into the shift register 396 along with the data bits. During the read mode, all eight bits are monitored when the word buffer 395 is loaded from the shift register 396. A parity detector flip flop 402 is set if parity is wrong. The parity error flip flop 402 is only enabled during the read mode and cleared through an NOR gate 404 by the state 2 signal from the flip flop 325.

In write mode, data is loaded from the word buffer 395 and transferred to the tape transport serially at the output 405 of the shift register chip 396. Data is loaded by setting the input 406 to the shift register chip 396 low and clocking the shift register through the inverter 407. The load signal and load clock are generated by the write control logic 325 which includes four six bit registers 408. During the read mode only the shift mode of the shift register 396 is used. Data from the tape transport is enabled and shifted in on the line 409 from the tape transport through an inverter 410 and a NOR gate 411. Data is clocked into the shift register 396 from the tape transport by the read clock signal 412 acting through the read module 413 to provide a signal through the inverter 407 to the shift register chip 396. After every eighth bit, the data word is located into the word buffer 395.

The bit counter 324 includes a four bit counter chip 414. The output 415 of the counter 414 is connected to a flip flop 416. The flip flop 416 is used only when reading the first word of a data block. The first word of a block is formed by counting nine clock pulses at 417 to the counter 414 to ignore the leading zero bit of a block. Once the flip flop 416 is set, it remains in that state until state one or a gap is detected through the NOR gate 418.

Whenever a word has been assembled, a strobe pulse is generated by a flip flop 419 acting through a NOR gate 324a connected to the clocking input of the bit counter 414. The strobe pulse to the bit counter 414 is generated by presetting the flip flop 419 with a high output, and clocking it low by delaying the output of the flip flop 419 with a one shot multivibrator 421. In the read mode, the strobe pulse output from multivibrator 421 is used to load the word buffer 395. During the write mode, the strobe pulse is used by the write control logic 325 to generate the load signal and load clock 422 as an output of the six bit counter 408.

The write control logic 325 generates the required signal to load the registers 396 when a data read or strobe pulse is received as a clocking input to the flip flop 423. Initially, all of the flip flops 423, 424, 425, 426 and 427 are cleared. The data read pulse acting as a clocking input to the flip flop 423 sets the flip flop 423 using it to generate a clock pulse at 428 for the word buffer 305. The word buffer 395 is empty, the pulse is allowed to clock data into the word buffer 395 and reset the clock pulse flip flop 423. When the buffer 395 is full, the register full signal 397 appears and clocks the first load flip flop 425 and disables the clock NOR gate 429. The output of the first load flip flop 425 enables the one shot 430 and initiates a pulse therefrom 431. With the shift full flip flop 424 cleared so that the input to the shift register 396 from the inverter 407 is high, the pulse from the one shot 430 clocks the data from the word buffer 395 to the shift register 396. The clock 430 also sets the shift full flip flop 424 through the NOR gate 433. The shift full flip flop 424 goes low, setting the shift register chip 396 in the shift mode. With the shift full flip flop 424 high, the not Q output clears the word register 395. The register clear flip flop 426 is reset when the register full signal at 397 is reset.

The next read data pulse to the flip flop 423 sets the flip flop 423 which generates another word buffer clock pulse through the inverter 407 to transfer data from the peripheral interface adapter 104, side A, to the word buffer 395 and also clears the clock pulse flip flop 423. With the register full signal from the flip flop 426 set, the clock NOR gate 429 is disabled. The third read data pulse sets the clock pulse flip flop 423 which remains set and the clock NOR gate 429 is disabled. The clock pulse flip flop 423 also generates the buffer ready full signal at 435, which is transformed to the buffer ready signal through the inverter 436 in the control logic circuit of FIG. 20. With the clock flip flop 423 set, the signal 435 is high so that the buffer ready signal low indicating that the controller of FIGS. 17 and 20 is not ready to accept data. If another data read signal is received by the flip flop 427, the not Q output 437 therefrom will be set. This signal is the write overflow signal and indicates that the last word in the peripheral interface adapter 104 is lost.

When state three is entered, the controller will start receiving shift data in pulses at 438 from the tape transport. The shift data impulses act through the inverter 439 to the input of the NOR gate 432. The shift data impulses 438 clock data out of the shift register through the inverter 407 and increment the bit counter 414 by means of a clock input 417. The strobe output 415 is transmitted through a NOR gate 440 to set a flip flop 419. The output of the flip flop 419 acts through a NOR gate 441 as an input to another NOR gate 442 to the shift full flip flop 424. The output of NOR gate 442 resets the shift full flip flop 424. The shift full flip flop 424 being reset changes the status of the shift register 396 into the load condition and loads data from the word register 395 by the delayed strobed pulse from NOR gate 442. The shift full flip flop 424 initiates a clear signal to the word buffer 395 by setting the register clear flip flop 426, the not Q output of which at 444 is transmitted through the register 409a to the clear input 445 of the buffer 395. In addition, the Q output of the flip flop 427 enables the clock pulse NOR gate 429. With the NOR gate 429 enabled and the clock pulse flip flop 423 set clock pulses at not Q output 428 of the clock flip flop 423 are allowed to strobe data into the word buffer 395. The clock flip flop 423 is cleared by the output of NOR gate 429 acting through NOR gate 447. With the clock pulse flip flop 423 cleared, the buffer ready signal to the two to one multiplexer 382 is high, requesting data from the microprocessor.

FIG. 21 is the circuit diagram for the bar code reader interface. The bar code reader is a complete system that consists of a hand held light pen 43 (FIGS. 1 and 2) and a decoding logic printed circuit board with a printed circuit board connector 450. The light pen 43 contains a LED source and reflective sensor assembly in its associated signal conditioning circuitry. The signals generated by the light pen in response to reading bar coded indicia are fed to the decoding logic printed circuit board. The decoding logic uses its own microprocessor system to convert the signals from the light pen to a usable output. The Identicom Model 600 Pen Reading System is a commercially available reading system employed in the invention and is supplied with its own operational manual having a complete description on the operation and use of the bar code reader.

Two commands from the microprocessor unit section are used to control the operation of the bar code reader; the user ready signal (line 451) enables the bar code reader and is used to clock the data out after a read operation has been performed; and the reset signal (line 452) is used to clear the decoding logic after the data has been passed to the microprocessor unit section and during system initialization. The commands are scored in a quad latch 455. The action of the reset command is straight forward.

The user ready command causes the flip flop 454 to set which applies a logic one to the user ready input of the decoding logic. This signal remains high enabling the bar code reader until a read operation has been performed and the data is ready to be output. At this time the data strobe signal goes low and returns high, clocking the four bit data word output of the decoding logic into the quad latch device 455. The data strobe signal also causes flip flop 456 to set. The output of flip flop 456 clears the user ready signal, sets the interrupt signal CA1, sets the address bit PA6 and enables the tristate output of the quad latch 455. The microprocessor unit 100 responds to the interrupt signal and reads the data stored in the quad latch 455. As a result of the microprocessor unit read operation, signal CA2 goes low, momentarily, and then returns high. This clears flip flop 456 which turns off the output of the quad 455. The microprocessor unit 100 then sends the user ready command which causes the entire cycle to be repeated. This operation is repeated until the last data word has been passed from the decoding logic to the microprocessor unit section. The decoding logic signifies the end of coded information by sending the hexadecimal character D to the microprocessor unit section. The hexadecimal character D is the four low order bits of the ASCII character CR (Carriage Return). The data output of the bar code reader is actually an eight bit ASCI character.

The microprocessor unit section senses the end of coded information and begins processing that information. At the proper time the microprocessor unit section sends the user ready command to the bar code reader to enable it for the next read operation.

Referring now to FIG. 22, there is shown a schematic diagram of the Electronics Industry Association Interface Section. This Section allows an external telecommunications device to be connected to the transaction accounting system in accordance with the provisions of the EIARS-232C specification on interconnected telecommunications equipment. Devices 460 and 461 provide the necessary shifting to convert the telecommunications level signals to PTL level signals used by the ACIA, device 462. A voltage controlled oscillator 463 provides the data rate for the interface. The nominal frequency of oscillator 463 is adjusted to 4.8 KHC which is sixteen times the 300 baud data rate. The ACIA 462 uses a divide by sixteen clock ratio for improved noise immunity.

The preceding description and illustrations are intended solely to illustrate the presently preferred mode of practice. The system thus described employs the elements identified in the following table:

The invention has been described with reference to the presently preferred and illustrated embodiment. It is not intended that the invention be unduly limited by this disclosure. Instead, the invention is intended to be defined by the means and their obvious equivalents set forth in the following claims.