High Performance CMOS Sense Amplifier

1. Field of the Invention

This invention relates to a high performance sense amplifier that is fabricated from complementary metal oxide semiconductor (CMOS) devices and is suitable for sensing, reading, or writing amplifier applications with large scale integrated semiconductor memories, and the like.

2. Statement of the Prior Art

As is known to those skilled in the art, some of the primary performance characteristics that must be ideally optimized in a sense amplifier that is utilized in conjunction with a high capacity and medium or high performance memory include increased sensitivity, speed, and noise immunity and decreased space and power consumption. The conventional sense amplifier approach generally comprises a differential type amplifier with flip-flop type operation. Typically, the conventional sense amplifier is characterized by medium speed, sensitivity, and power dissipation.

While the prior art differential amplifier could be modified to improve the sensitivity, the gain and the speed of operation, the number and/or the size of the component devices thereof, and the corresponding power dissipation typically increases. In addition, the prior art differential amplifier is not adapted to tolerate non-symmetrical parameters or load on its two sides.

Some of the other problems inherent in the fabrication of the sense amplifiers of the prior art include the following. The desired precharge voltage does not match with the high gain area of the sense amplifier. That is, the precharge voltage is defined by the logical "0" and "1" signal levels occurring within a selected memory cell, by the threshold voltages of the transmission devices, by the different charge couplings and leakage currents, by capacitive and resistive load non-symmetricity, and by the offset voltage of the sense amplifier. However, the location of the high gain area of the sense amplifier is otherwise dependent upon the width-to-length ratio, the threshold voltage, the leakage current, the body effect factor, and the gain factor of the individual MOS devices which comprise the sense amplifier.

What is more, the differential type amplifiers of the prior art and the MOS devices associated therewith cannot tolerate any non-symmetrical changes in the structure of the component devices, the threshold voltages, and the parasitic capacitances, resistances and leakages, such as those caused by either device processing or by a nuclear radiation event. Any deviation from the ideal symmetrical case degrades performance rapidly and usually is accompanied by error or malfunction. More particularly, exposure of a conventional sense amplifier to a nuclear radiation event may result in both permanent degradation of MOS component parameters as well as a temporary upsetting of the sense amplifier operation. Permanent degradation in the characteristics of the semiconductor components which comprise the sense amplifier is typically caused by ionizing and neutron radiation effects. A permanent degradation in component characteristics may result in a shifting (i.e. an increase or decrease) in the threshold potentials of complementary semiconductor devices, an increase in leakage current, and a decrease in gain. The shifting of component characteristics (i.e. electrical parameters) varies with each individual component device and depends upon the voltage bias of the device electrodes that occurs during the time of radiation exposure. Additionally, temporary upsets induced by high energy, short term radiation exposure with rapid anneal effects from a nuclear event may result in momentary shifts in the parameters of the MOS components, which parameters return approximately to original parameter levels. Such rapid anneal effects are common when the sense amplifier is exposed to a large dose from x-rays, or gamma rays. The transient radiation temporarily causes extremely high leakage, transient shifts in the threshold voltages, as well as degradation in gain factor and in other parameters of the components which comprise the sense amplifier. As the rapid anneal effects dissipate with time, the parameters of the components subsequently and approximately recover to the level of permanent degradation.

The following patents show examples of prior art sensing arrangements:

U.S. Pat. No. 4,003,035 Jan. 11, 1977;

U.S. Pat. No. 4,003,034 Jan. 11, 1977;

U.S. Pat. No. 3,959,781 May 25, 1976,

U.S. Pat. No. 3,909,739 Sept. 30, 1975.

However, none of the aforementioned patents discloses a CMOS sense amplifier comprising first and second cross-coupled inverter-amplifier stages having series or parallel connected compensating components which automatically compensate for the effects of electrical parameter non-uniformities that may occur as a result of MOS device processing or exposure to a radiation event. Moreover, none of the aforementioned patents shows a sense amplifier which utilizes the body effect (such as that available in a MOS transistor device fabricated by silicon on sapphire techniques) to achieve self-compensation, as provided by some of the embodiments of the present invention.

Briefly, and in general terms, a high performance sense amplifier is disclosed that, in a preferred embodiment, is fabricated from complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) with silicon on sapphire (SOS) technology. In one embodiment of the present invention, the sense amplifier is comprised of first and second complementary pairs of series connected p and n-channel FETs forming cross-connected inverter-amplifier stages with or without feedback. The source electrodes of the p-channel FETs that comprise the inverter-amplifiers are connected together at an electrical junction. Another p-channel FET is connected between this electrical junction and a source of relatively positive source voltage. The gate electrode of the additional p-channel FET is supplied with a clock control signal. The source electrodes of the n-channel FETs that comprise the inverter-amplifiers are also connected together at an electrical junction. Another n-channel FET is connected between this last mentioned electrical junction and a source of relatively negative source voltage. The gate electrode of the additional n-channel FET is also supplied with a clock control signal. By virtue of the present invention, the sense amplifier achieves high sensitivity, high gain, optimum noise immunity, and low power dissipation, inasmuch as the complementary field effect transistor pairs operate with the sum of their respective drain-source voltages equal to the sum of the threshold voltages of a pair of complementary field effect transistors.

In another embodiment of the present invention, a self-compensating sense amplifier is provided which automatically compensates for geometrical non-uniformities that may occur as a result of MOS device processing or from exposure to a nuclear radiation event. Self-compensation is achieved by arranging either series or parallel connected compensating elements (resistors, FETs, and the like) with the first and second pairs of complementary series connected field effect transistors so as to automatically control the respective drain currents in each of the first and second transistor pairs. Moreover, self-compensation may also be achieved by utilizing the body effect on MOS device threshold voltages by fabricating both the complementary transistor pairs and the compensating elements with silicon on sapphire techniques, or the like.

FIG. 1 shows a high performance CMOS sense amplifier formed in accordance with the present invention.

FIGS. 2-8 each show a high performance, self-compensating CMOS sense amplifier formed in accordance with another embodiment of the present invention.

FIGS. 9-11 each show a CMOS sense amplifier that utilizes the body effect on field effect transistor device threshold voltage to automatically compensate for non-uniformities occurring as a result of device processing or exposure to a nuclear radiation event.

FIG. 1 of the drawings shows a preferred embodiment of a complementary metal oxide semiconductor (CMOS) sense amplifier 2 with maximized signal sensitivity, speed, noise immunity, and gain and minimized size and power dissipation. In accordance with the present invention, the sense amplifier 1 is formed by first and second cross-coupled inverting amplifier stages 2 and 4. Inverter-amplifier stage 2 is comprised of a pair of series connected field effect transistors (FETs) Q.sub.2 and Q.sub.3. Inverter-amplifier stage 4 is comprised of a pair of series connected field effect transistors (FETs) Q.sub.4 and Q.sub.5. Each of the gate electrodes of FETs Q.sub.2 and Q.sub.3 are connected together at a first electrical junction and input terminal 6 formed between the series connected conduction paths of FETs Q.sub.4 and Q.sub.5. Each of the gate electrodes of FETs Q.sub.4 and Q.sub.5 are connected together at a second electrical junction and input terminal 8 formed between the series connected conduction paths of FETs Q.sub.2 and Q.sub.3 so that the cross-coupled inverter stages 2 and 4 provide feedback signals to one another. The series connected conduction paths of FETs Q.sub.2 and Q.sub.3 are connected in electrical parallel with the series connected conduction paths of FETs Q.sub.4 and Q.sub.5 between a pair of electrical junctions 10 and 12.

A first FET Q.sub.1 is connected between a source of relatively positive supply voltage V.sub.DD and the electrical junction 10. The gate electrode of FET Q.sub.1 is connected to a clock terminal means 14 to receive a first clock signal .phi.. A second FET Q.sub.6 is connected between electrical junction 12 and a source of relatively negative supply voltage V.sub.SS, such as, for example, ground. The gate electrode of FET Q.sub.6 is connected to a clock terminal means 16 to receive a second clock signal .phi.. The first and second clock signals may be complements of one another. FETs Q.sub.1 and Q.sub.6 are rendered conducting by the respective clock signals .phi. and .phi. so as to clamp electrical junctions 10 and 12, with suitable varying resistance, to one of the supply voltages V.sub.DD or V.sub.SS. In a preferred embodiment, FETs Q.sub.1, Q.sub.2, and Q.sub.4 are p-channel transistor devices, while FETs Q.sub.3, Q.sub.5, and Q.sub.6 are n-channel transistor devices. Moreover, for minimizing voltage and current offset, FETs Q.sub.2 and Q.sub.4 as well as Q.sub.3 and Q.sub.5 are identically sized devices.

To separate the presently disclosed sense amplifier 1 from any one of a plurality of memory cells 20 comprising a suitable array thereof or to precharge input terminals 6 and 8 independently from the data bus lines, well known coupling means are connected between the sense amplifier 1 and a pair of the data bus lines. More particularly, a first coupling transistor means 17 is connected between the input electrical junction 8 and a BIT data bus line. A second coupling means 18 is connected between the input electrical junction 6 and an opposite state BIT data bus line. By way of example, coupling transistor means 17 and 18 may each comprise a pair of complementary field effect transistors having their respective conduction paths connected in electrical parallel with one another between a sense amplifier input terminal 6 or 8 and a corresponding data bus line. However, the coupling transistor means 17 and 18 may also be fabricated from single devices or, depending on the memory organization, they may be eliminated entirely. The conductivity of each of the pair of coupling transistors is controlled by the clock signals .phi. and .phi. applied to the respective gate electrodes thereof. The presently disclosed sense amplifier 1 may be interfaced with an array of memory cells 20 via the BIT and BIT data bus lines in any well known configurations, such as a row amplifier arrangement, a pipe lined amplifier arrangement, or the like.

The operation of the presently disclosed CMOS sense amplifier 1 having optimized performance is described as follows. During the start of operation, disabling clock control signals .phi. and .phi. are supplied from clock terminal means 14 and 16 to the respective gate electrodes of FETs Q.sub.1 and Q.sub.6, and FETs Q.sub.1 and Q.sub.6 are rendered non-conducting. Although the electrical potentials applied to electrical junctions 10 and 12 are floating, the voltage of electrical junction 10 is nearly that of the V.sub.DD supply voltage, and the voltage of electrical junction 12 is nearly that of the V.sub.SS supply voltage. Precharge voltages more positive than the sum of the V.sub.SS supply voltage and the threshold voltage drop of an n-channel FET and more negative than the difference between V.sub.DD supply voltage and the threshold voltage drop of a p-channel FET are respectively applied to each of the electrical junctions 6 and 8 and to the gate electrodes of FETs Q.sub.2, Q.sub.3, Q.sub.4 and Q.sub.5 so as to render conducting each of FETs Q.sub.2 -Q.sub.5. After developing the proper precharge voltages, the voltage at electrical junction 10 is equivalent to the sum of the precharge voltage plus the threshold voltage drop V.sub.tp of the p-channel FET Q.sub.2. The voltage at electrical junction 12 is equivalent to the difference between the precharge voltage and the threshold voltage drop V.sub.tn of the n-channel FET Q.sub.5. Therefore, the voltage difference between electrical junctions 10 and 12 is equivalent to the sum of the threshold voltage drops of the p-channel FET Q.sub.2 (or Q.sub.4) and the n-channel FET Q.sub.5 (or Q.sub.3), i.e.: .vertline.V.sub.tp .vertline.+V.sub.tn, which, thereby, automatically results in a nearly rectangular function of input-output transfer characteristics regardless of the size of the amplifier component devices and automatically places the initial operating point into the center of this rectangular function regardless of varying device parameters, temperature, supply voltage, or radiation effects. Thus, the sense amplifier 1 begins to work automatically at the optimum operating point where the highest sensitivity, highest gain, best noise immunity, and lowest power dissipation of any amplifier can be achieved whenever FETs Q.sub.1 and Q.sub.6 are rendered conducting by the .phi. and .phi. clock signals.

When a particular memory cell 20 from the array thereof is selectively accessed, the potentials at electrical junctions 6 and 8 are respectively increased and decreased, or vice versa, in accordance with the information stored in the selected memory cell. After the selected memory cell 20 is accessed, FETs Q.sub.1 and Q.sub.6 are relatively slowly rendered conducting. During this slow conduction of FETs Q.sub.1 and Q.sub.6, the sense amplifier works close to the initial ideal operating point. However, after the proper potential difference has been achieved between electrical junctions 6 and 8, high sense amplifier sensitivity is no longer critical, and the clock signals .phi. and .phi. that are supplied to the gate electrodes of FETs Q.sub.1 and Q.sub.6 cause FETs Q.sub.1 and Q.sub.6 to be rendered fully conducting to thereby provide to the electrical junctions 6 and 8, in a relatively short time, a maximum logic "1" signal level (that is equivalent to the V.sub.DD supply voltage) and a minimum logic "0" signal level (that is equivalent to the V.sub.SS supply voltage). Unlike those sense amplifiers of the prior art, because of the nearly ideal transfer characteristics and the automatic ideal operating point adjustment, the present sense amplifier 1 is characterized by small integrable size, while achieving optimum performance for sensitivity, gain, noise immunity, and power dissipation. However, the sense amplifier 1 remains responsive to the non-symmetricity of devices, load, or parasitic effects on either of the two cross-coupled inverter-amplifier stages 2 and 4.

Immunity from non-uniformities as a result of device processing or from imbalances caused by exposure to a nuclear radiation event is provided by arranging MOS devices, according to the following embodiments of the present invention, so as to form sense amplifier configurations which automatically compensate for the undesirable effects of non-symmetry and for degradation in the characteristics of the semiconductor components caused by ionizing radiation, neutron and transient annealing effects.

FIG. 2 shows a self-compensating CMOS sense circuit 21 that operates in the linear MOS region and has both read and write capabilities. The sense circuit 21 is identical to the sense circuit 1 of FIG. 1, except for the addition of compensating resistors R.sub.1 -R.sub.4. Referring to FIG. 2, resistor R.sub.1 is connected in electrical series with FET Q.sub.2 between electrical junctions 10 and 8. Resistor R.sub.2 is connected in electrical series with FET Q.sub.3 between electrical junctions 8 and 12. Resistor R.sub.3 is connected in electrical series with FET Q.sub.4 between electrical junctions 10 and 6. Resistor R.sub.4 is connected in electrical series with FET Q.sub.5 between electrical junctions 6 and 12.

In operation, resistors R.sub.1 -R.sub.4 enable the presently disclosed sense amplifier 21 to achieve high sensitivity relative to the level of the information signals on the BIT and BIT data bus lines by supplying individual compensation to the critical MOS devices (e.g. FETs Q.sub.3 and Q.sub.5) to prevent sense amplifier failure as an undesirable result of either temperature or radiation induced threshold voltage changes. The effective transconductance g.sub.m ' of the sense amplifier 21 is represented by:

where g.sub.m depends upon transistor device parameters such as threshold voltages, mobility, geometry, etc. However, if R.sub.s (e.g. R.sub.1 -R.sub.4)>>1, then g.sub.m ' is approximately equal to 1/R.sub.s, so that, by virtue of the present sense amplifier 21, g.sub.m becomes virtually independent of the transistor device parameter changes.

In two similar self-compensating CMOS sense amplifiers 31 and 41, the compensating resistors R.sub.1 -R.sub.4 of FIG. 2 are replaced by compensating FET devices Q.sub.11 -Q.sub.14 that operate in the triode region, as illustrated in FIGS. 3 and 4. FETs Q.sub.11 -Q.sub.14 decrease the required silicon area while facilitating the utilization of a simplified process technique and decreasing the processing and masking strips. However, the radiation hardness of the sense amplifiers 31 and 41 is usually weaker, inasmuch as FET devices are more sensitive to radiation than are hardened resistors.

Each of the sense amplifiers 31 and 41 is identically comprised of the aforementioned four compensating FETs Q.sub.11 -Q.sub.14. Sense amplifier 31 also includes first and second cross-coupled inverter-amplifier stages 2 and 4, having cross-connected FETs Q.sub.2 -Q.sub.5, identical to that illustrated in FIG. 1. The sense amplifier 41 includes first and second inverter-amplifier stages 42 and 44, comprising respective pairs of series connected FETs Q.sub.15, Q.sub.16 and Q.sub.17, Q.sub.18, which FETs are not cross-connected so that no feedback signals are supplied to one another. Therefore, the sense amplifier 41 of FIG. 4 can be characterized as having a high input impedance, while providing inverted output signals at electrical junctions 46 and 48. Each of the gate electrodes of the compensating FETs Q.sub.11 and Q.sub.13 of both of the sense amplifiers 31 and 41 are connected together and to the clock terminal means to receive the .phi. clock signal. Moreover, each of the gate electrodes of the compensating FETs Q.sub.12 and Q.sub.14 of both of the sense amplifiers 31 and 41 are connected together and to the clock terminal means to receive the .phi. clock signal. An electrical junction between the series connected conduction paths of inverter-amplifier FETs Q.sub.15 and Q.sub.16 of sense amplifier 41 is connected together to form a first output. An electrical junction between the series connected conduction paths of inverter-amplifier FETs Q.sub.17 and Q.sub.18 of sense amplifier 41 is connected together to form a second output. The conduction path of a first additional FET Q.sub.1 is connected between the relatively positive source of supply voltage V.sub.DD and one conduction path electrode of each of the compensating FETs Q.sub.11 and Q.sub.13 of sense amplifiers 31 and 41. The gate electrode of FET Q.sub.1 is connected to clock terminal means to receive the .phi. clock signal. The conduction path of a second additional FET Q.sub.6 is connected between one conduction path electrode of each of the compensating FETs Q.sub.12 and Q.sub.14 of sense amplifiers 31 and 41 and the relatively negative source of supply voltage V.sub.SS. The gate electrode of FET Q.sub.6 is connected to clock terminal means to receive the .phi. clock signal. In a preferred embodiment, compensating FETs Q.sub.11 and Q.sub.13 are p-channel transistor devices, while compensating FETs Q.sub.12 and Q.sub.14 are n-channel transistor devices.

Another self-compensating CMOS sense amplifier 51 is illustrated in FIG. 5. The presently disclosed sense amplifier 51 includes a pair of cross-coupled inverter-amplifier stages 2 and 4, comprising FETs Q.sub.2 -Q.sub.5, as previously illustrated in FIG. 1, and four cross-connected compensating FETs Q.sub.19 -Q.sub.22. The conduction path of a first compensating FET Q.sub.19 is connected between electrical junctions 52 and 56 and in electrical series with FET Q.sub.2. The conduction path of a second compensating FET Q.sub.21 is connected between electrical junctions 54 and 56 and in electrical series with FET Q.sub.4. The gate electrodes of FETs Q.sub.19 and Q.sub.21 are cross-connected to electrical junctions 54 and 52, respectively. The conduction path of a third compensating FET Q.sub.20 is connected between electrical junctions 53 and 58 and in electrical series with FET Q.sub.3. The conduction path of a fourth compensating FET Q.sub.22 is connected between electrical junctions 55 and 58 and in electrical series with FET Q.sub.5. The gate electrodes of FETs Q.sub.20 and Q.sub.22 are cross-connected to electrical junctions 55 and 53, respectively. The conduction path of a first additional FET Q.sub.1 is connected between the relatively positive source of supply voltage V.sub.DD and the electrical junction 56. The gate electrode of the FET Q.sub.1 is connected to clock terminal means to receive the .phi. clock signal. The conduction path of a second additional FET Q.sub.6 is connected between the electrical junction 58 and the source of relatively negative supply voltage V.sub.SS. The gate electrode of the FET Q.sub.6 is connected to clock terminal means to receive the .phi. clock signal. In a preferred embodiment, FETs Q.sub.1, Q.sub.2, Q.sub.4, Q.sub.19, and Q.sub.21 are p-channel transistor devices, and FETs Q.sub.3, Q.sub.5, Q.sub.6, Q.sub.20, and Q.sub.22 are n-channel transistor devices.

The operation of the self-compensating sense amplifier 51 of FIG. 5 is briefly described as follows. Under ideal operating conditions, the respective drain currents in each of the cross-coupled inverter FETs Q.sub.3 and Q.sub.5 are identical. However, should an undesirable geometrical non-uniformity or an exposure to a radiation event cause an amplifier variation such as, for example, in the threshold potential, leakage current, or gain factor in one of the cross-coupled inverter-amplifier stages 2 or 4, the drain current of one of the first inverter FETs Q.sub.3 exceeds the corresponding drain current of one of the second inverter FETs Q.sub.5, inasmuch as the source-drain resistance of FET Q.sub.3 becomes less than that of FET Q.sub.5. Hence, the voltage at electrical junction 53 exceeds the corresponding voltage at electrical junction 55, and, as a result, FET Q.sub.22 turns on harder than FET Q.sub.20. Therefore, the source-drain resistance of FET Q.sub.22 is effectively reduced relative to the source-drain resistance of FET Q.sub.20, so that the voltage at electrical junction 55 is decreased and the voltage at electrical junction 53 is correspondingly increased. By virtue of the self-compensating sense amplifier 51, the sum of the source-drain resistances of the series connected FETs Q.sub.3 and Q.sub.20 approximates that of FETs Q.sub.5 and Q.sub.22, whereby the drain currents of FETs Q.sub.3 and Q.sub.5 are approximately equalized.

Another self-compensating CMOS sense amplifier 61 is illustrated in FIG. 6. Sense amplifier 61 is comprised of an arrangement of four compensating FETs Q.sub.23, Q.sub.24, Q.sub.25 and Q.sub.26. In addition to the compensating FETs Q.sub.23 -Q.sub.26, the conduction paths of a pair of FETs Q.sub.27 and Q.sub.28 are connected in electrical series with one another between electrical junctions 62 and 63. The conduction paths of another pair of FETs Q.sub.29 and Q.sub.30 are connected in electrical series with one another between electrical junctions 64 and 65. The respective gate electrodes of FETs Q.sub.27 and Q.sub.29 are connected together at the source of relatively negative supply voltage V.sub.SS. The respective gate electrodes of FETs Q.sub.28 and Q.sub.30 are also connected together at the source of relatively negative supply voltage V.sub.SS. Unlike the sense amplifier of FIG. 1, the gate electrodes of FETs Q.sub.27 -Q.sub.30 are not cross-connected relative to one another, so that the presently disclosed sense amplifier 61 operates without inverter feedback, with a high sense input impedance at input electrical junctions 6' and 8', and with a minimum number of transfer devices.

One conduction path electrode of a first compensating FET Q.sub.23 is connected at the electrical junction 66. The second conduction path electrode of FET Q.sub.23 and the gate electrode of a second compensating FET Q.sub.25 are connected together at the electrical junction 62. One conduction path electrode of the compensating FET Q.sub.25 is connected at the electrical junction 66. The second conduction path electrode of FET Q.sub.25 and the gate electrode of compensating FET Q.sub.23 are connected together at the electrical junction 64. A first additional FET Q.sub.1 is connected between the electrical junction 66 and the source of relatively positive supply voltage V.sub.DD. The gate electrode of FET Q.sub.1 is connected to clock terminal means to receive the .phi. clock signal. In a preferred embodiment, FETs Q.sub.1, Q.sub.23, Q.sub.25, Q.sub.27, and Q.sub.29 are p-channel transistor devices.

One conduction path electrode of a third compensating FET Q.sub.24 is connected to the electrical junction 68. The second conduction path electrode of compensating FET Q.sub.24 and the gate electrode of a fourth compensating FET Q.sub.26 are connected together at the electrical junction 63. One conduction path electrode of compensating FET Q.sub.26 is connected to the electrical junction 68. The second conduction path electrode of FET Q.sub.26 and the gate electrode of FET Q.sub.24 are connected together at the electrical junction 65. The conduction path of a second additional FET Q.sub.6 is connected between electrical junction 68 and the source of relatively negative supply voltage V.sub.SS. The gate electrode of FET Q.sub.6 is connected to clock terminal means to receive the .phi. clock signal. In a preferred embodiment, FETs Q.sub.6, Q.sub.24, Q.sub.26, Q.sub.28, and Q.sub.30 are n-channel transistor devices.

The operation of the self-compensating sense amplifier 61 of FIG. 6 is briefly described as follows. Under ideal operating conditions, the drain currents of each of FETs Q.sub.28 and Q.sub.30 are identical. However, should the drain current of FET Q.sub.28 exceed that of FET Q.sub.30 due to an unbalance, such as that caused by a device parameter nonuniformity or by a nuclear radiation event, the corresponding voltage at electrical junction 63 exceeds that at electrical junction 65. Hence, FET Q.sub.26 turns on harder than FET Q.sub.24, and, as a result, the sum of the source-drain resistances of the series connected FETs Q.sub.30 and Q.sub.26 approximates that of the series connected FETs Q.sub.28 and Q.sub.24. Therefore, by virtue of the disclosed self-compensating sense amplifier 61, the drain currents of each of FETs Q.sub.28 and Q.sub.30 are approximately equalized. What is more, maximized logic level "0" and "1" signals (i.e. V.sub.DD and V.sub.SS) can be generated by the sense amplifier 61 at electrical junctions 6' and 8', which signals are clearly distinguishable from one another.

Another form of the self-compensating CMOS sense amplifier configuration illustrated in FIG. 6 is that shown in FIG. 7. The sense amplifier 71 of FIG. 7 includes a pair of cross-coupled inverter-amplifier stages 2 and 4, comprising FETs Q.sub.2 -Q.sub.5 and an arrangement of four compensating FETs Q.sub.31, Q.sub.32, and Q.sub.34 (identical to those illustrated in FIG. 5). One conduction path electrode of each of the compensating FETs Q.sub.31 and Q.sub.33 are connected together at an electrical junction 76. The gate electrode of compensating FET Q.sub.31 is connected at an electrical junction 72 with the second conduction path electrode of compensating FET Q.sub.33 and one conduction path electrode of FET Q.sub.2. The second conduction path electrode of FET Q.sub.31 is connected at an electrical junction 74 with the gate electrode of FET Q.sub.33 and one conduction path electrode of FET Q.sub.4. Thus, the conduction paths of FETs Q.sub.31 and Q.sub.4 and FETs Q.sub.33 and Q.sub.2 are connected in electrical series. One conduction path electrode of each of the compensating FETs Q.sub.32 and Q.sub.34 are connected together at an electrical junction 78. The second conduction path electrode of compensating FET Q.sub.32 and the gate electrode of compensating FET Q.sub.34 are connected together at an electrical junction 75 with one conduction path electrode of FET Q.sub.5. The second conduction path electrode of FET Q.sub.34 and the gate electrode of FET Q.sub.32 are connected together at an electrical junction 73 with one conduction path electrode of FET Q.sub.3. Thus, the conduction paths of FETs Q.sub.3 and Q.sub.34 and FETs Q.sub.5 and Q.sub.32 are connected in electrical series. The conduction path of the first additional FET Q.sub.1 is connected between the source of relatively positive supply voltage V.sub.DD and the electrical junction 76. The gate electrode of FET Q.sub.1 is connected to clock terminal means to receive the .phi. clock signal. The conduction path of a second additional FET Q.sub.6 is connected between the electrical junction 78 and the relatively negative source of supply voltage V.sub.SS. The gate electrode of FET Q.sub.6 is connected to clock terminal means to receive the .phi. clock signal. In a preferred embodiment, FETs Q.sub.1, Q.sub.2, Q.sub.4, Q.sub.31, and Q.sub.33 are p-channel transistor devices, while FETs Q.sub.3, Q.sub.5, Q.sub.6, Q.sub.32, and Q.sub.34 are n-channel transistor devices.

It is pointed out that while the mechanization and operation of the sense amplifier 71 of FIG. 7 are electrically identical to that of the sense amplifier 51 of FIG. 5, the sense amplifier 71 may have certain geometrical advantages. More particularly, on the silicon surface, each of FETs Q.sub.2, Q.sub.3, Q.sub.31, and Q.sub.32 is geometrically arranged on one side of symmetrical axis 79, and each of the FETs Q.sub.4, Q.sub.5, Q.sub.33, and Q.sub.34 is arranged on the other side of axis 79. This symmetrical arrangement of FET devices achieves a compensating effect during processing to account for misalignments from fabrication. For example, if the gain of a FET Q.sub.5 is higher than that of Q.sub.3 as a result of different channel widths, the gain of FET Q.sub.34 is usually also higher than that of FET Q.sub.32. Since FET Q.sub.3 is connected in electrical series with FET Q.sub.34 and FET Q.sub.5 is connected in electrical series with FET Q.sub.32, any resulting gain difference is minimized.

Another self-compensating CMOS sense amplifier 81 which compensates for the effects of processing, temperature and radiation induced parameter changes in MOS devices is illustrated in FIG. 8. Unlike those sense amplifiers illustrated in FIGS. 2-7 that include an arrangement of series connected compensating devices, FIG. 8 shows a sense amplifier 81 having parallel connected MOS compensating devices. More particularly, the disclosed self-compensating sense amplifier 81 includes first and second cross-coupled inverter-amplifier stages 2 and 4 comprising respective pairs of series connected FETs Q.sub.2, Q.sub.3 and Q.sub.4, Q.sub.5 identical to that illustrated in FIG. 1. The conduction path of a first compensating FET Q.sub.35 is connected in electrical parallel with inverter FET Q.sub.2 between electrical junctions 82 and 8. The conduction path of a second compensating FET Q.sub.36 is connected in electrical parallel with inverter FET Q.sub.3 between electrical junctions 8 and 84, whereby the conduction paths of compensating FETs Q.sub.35 and Q.sub.36 are connected in electrical series relative to one another. The gate electrodes of FETs Q.sub.35 and Q.sub.36 are connected together at electrical junction 8. The conduction path of a third compensating FET Q.sub.37 is connected in electrical parallel with inverter FET Q.sub.4 between electrical junctions 82 and 6. The conduction path of a fourth compensating FET Q.sub.38 is connected in electrical parallel with inverter FET Q.sub.5 between electrical junctions 6 and 84, whereby the conduction paths of compensating FETs Q.sub.37 and Q.sub.38 are connected in electrical series relative to one another. The gate electrodes of FETs Q.sub.37 and Q.sub.38 are connected together at electrical junction 6. In a preferred embodiment, FETs Q.sub.35 and Q.sub.37 are p-channel transistor devices, while FETs Q.sub.36 and Q.sub.38 are n-channel transistor devices. The conduction path of a first additional FET Q.sub.1 is connected between the relatively positive source of supply voltage V.sub.DD and the electrical junction 82. The gate electrode FET Q.sub.1 is connected to clock terminal means to receive the .phi. clock signal. The conduction path of a second additional FET Q.sub.6 is connected between the electrical junction 84 and the source of relatively negative supply voltage V.sub.SS. The gate electrode of FET Q.sub.6 is connected to clock terminal means to receive the .phi. clock signal. In operation, each cross-coupled inverter-amplifier stage 2 and 4 functions as a well known source follower to provide compensation for the logic level signals applied to the electrical junctions 6 and 8.

In another embodiment of the present invention, the body or back gate bias effect on MOS device threshold voltage is employed for self-compensation, as illustrated by the sense amplifier 91 in FIG. 9. The sense amplifier 91 is identical to that illustrated and previously disclosed when referring to FIG. 2, except that the respective floating body nodes (inherently formed between the conduction path electrodes and under the channel region of a MOSFET) of each of the p-channel FETs Q.sub.1 ', Q.sub.2 ', and Q.sub.4 ' are connected to the relatively positive source of supply voltage V.sub.DD. The respective body nodes of each of the n-channel FETs Q.sub.3 ', Q.sub.5 ', and Q.sub.6 ' are connected to the relatively negative source of supply voltage V.sub.SS. In a preferred embodiment, FETs Q.sub.1 ', Q.sub.2 ', Q.sub.3 ', Q.sub.4 ', Q.sub.5 ', and Q.sub.6 ' are each fabricated by conventional silicon on sapphire (SOS) techniques.

The operation of the self-compensating sense amplifier 91 of FIG. 9 is briefly described as follows. Under ideal operating conditions, the drain currents in each of FETs Q.sub.3 ' and Q.sub.5 ' are identical. However, should the drain current of FET Q.sub.3 ' exceed that of FET Q.sub.5 ' due to an unbalance, such as that caused by a parameter non-uniformity or by a nuclear radiation event, the corresponding source voltage of FET Q.sub.3 ', is increased relative to that of FET Q.sub.5 '. As a result, the difference between the source voltage of FET Q.sub.3 ' and the source of negative supply voltage V.sub.SS (which is connected to the body node of FET Q.sub.3 ') is, accordingly, increased. Because of the well known body effect or back gate bias effect, the threshold voltage of FET Q.sub.3 ' is also increased, thereby causing a decrease in the difference between the gate voltage and threshold voltage of FET Q.sub.3 '. Hence, the drain current of FET Q.sub.3 ' is diminished. What is more, due to similar, but opposing effects, the drain current of FET Q.sub.5 ' is increased. Therefore, by virtue of the self-compensating sense amplifier 91, the drain currents of each of FETs Q.sub.3 ' and Q.sub.5 ' are approximately equalized. Moreover, the value of the resistors R.sub.1 -R.sub.4 is virtually independent of the radiation level that results from a nuclear event.

Another self-compensating sense amplifier configuration 101 that utilizes the body effect on MOS transistor device threshold voltages is shown in FIG. 10. The self-compensating sense amplifier 101 is identical to that illustrated and previously disclosed while referring to FIG. 6, except for the connections of the inherently formed body nodes of each of the MOSFETs. More particularly, the respective body nodes of p-channel FETs Q.sub.1 ', Q.sub.27 ', and Q.sub.29 ' are each connected to the relatively positive source of supply voltage V.sub.DD. The respective body nodes of each of the p-channel compensating FETs Q.sub.23 ' and Q.sub.25 ' could be connected together at electrical junction 66, as shown, or connected to the source of positive supply voltage V.sub.DD when bulk CMOS fabrication techniques are employed. The respective body nodes of the n-channel FETs Q.sub.6 ', Q.sub.28 ', and Q.sub.30 ' are connected to the relatively negative source of supply voltage V.sub.SS. The respective body nodes of each of the n-channel compensating FETs Q.sub.24 ' and Q.sub.26 ' could be connected together at the electrical junction 68, as shown, or connected to the source of negative supply voltage V.sub.SS when bulk CMOS fabrication techniques are employed. In a preferred embodiment, FETs Q.sub.1 ', Q.sub.6 ', Q.sub.23 ', Q.sub.24 ', Q.sub.25 ', Q.sub.26 ', Q.sub.27 ', Q.sub.28 ', Q.sub.29 ', and Q.sub.30 ' are each fabricated by conventional silicon on sapphire techniques.

The operation of the self-compensating sense amplifier 101 of FIG. 10 is briefly described as follows. The threshold voltages of MOSFET devices (e.g. FETs Q.sub.28 ' and Q.sub.30 ') depend upon the substrate (body) bias thereof, and, by changing the sourcebody voltage of these MOS devices, any current difference therethrough can be compensated by the respective body-source voltages. Under ideal operating conditions, the drain currents in each of FETs Q.sub.28 ' and Q.sub.30 ' are identical. However, should the drain current of FET Q.sub.28 ' exceed that of Q.sub.30 ' due to an unbalance, such as that caused by a nuclear radiation event, the corresponding voltage at electrical junction 63 exceeds that at electrical junction 65. As a result, the body-source voltage of FET Q.sub.28 ' exceeds that of FET Q.sub.30 ', and, accordingly, the source-drain resistance of FET Q.sub.28 ' is increased, while the source-drain resistance of FET Q.sub.30 ' is decreased. Hence, the sum of the resistance of the series connected FETs Q.sub.28 ' and Q.sub.24 ' approximates that of the series connected FETs Q.sub.30 ' and Q.sub.26 '. Therefore, by virtue of the self-compensating sense amplifier 101, the drain currents of each of FETs Q.sub.28 ' and Q.sub.30 ' are approximately equalized.

Another self-compensating sense amplifier configuration 111 that utilizes the body effect on MOS transistor device threshold voltages is shown in FIG. 11. The sense amplifier 111 is identical to that illustrated and disclosed when referring to FIG. 7, except for the connections of the inherently formed body nodes of each of the MOSFETs. More particularly, the respective body nodes of each of the p-channel FETs Q.sub.1 ', Q.sub.2 ', Q.sub.4 ', Q.sub.31 ', and Q.sub.33 ' are connected to the relatively positive source of supply voltage V.sub.DD. Moreover, the respective body nodes of each of the n-channel FETs Q.sub.3 ', Q.sub.5 ', Q.sub.6 ', Q.sub.32 ', and Q.sub.34 ' are connected to the relatively negative source of supply voltage V.sub.SS. In a preferred embodiment, each of FETs Q.sub.1 ', Q.sub.2 ', Q.sub.3 ', Q.sub.4 ', Q.sub.5 ', Q.sub.6 ', Q.sub.31 ', Q.sub.32 ', Q.sub.33 ', and Q.sub.34 ' is fabricated by conventional silicon on sapphire techniques. Inasmuch as the principle of operation of the sense amplifier 111 of FIG. 11 to compensate for undesirable unbalances is similar to that of the sense amplifier 101 illustrated in FIG. 10, a description of the operation of the self-compensating sense amplifier 111 is omitted.

It will be apparent that while a preferred embodiment of the invention has been shown and described, various changes and modifications may be made without departing from the true spirit and scope of the invention. For example, although the presently disclosed sense amplifiers are preferably fabricated from MOSFET devices, it is to be understood that either metal insulated semiconductor (MIS), junction field effect transistor (JFET), or bipolar devices may also be suitably employed to mechanize the instant sense amplifiers.