Pulse Width Modulated Signal Amplifier With Protective Means

1. Field of the Invention

This invention relates generally to a pulse width modulated signal amplifier, and more particularly is directed to a protecting circuit of a pulse width modulated signal amplifier having a rectifying circuit for rectifying an AC voltage to obtain a DC operating voltage for the amplifier.

Description of the Prior Art

In a prior art pulse width modulated signal amplifier, there is provided at its output side, a low pass filter including an inductance for demodulating an amplified pulse width modulated signal to an audio signal or the like. Normally, forward and backward (positive and negative) currents alternately flow through this low pass filter. However, when the frequency of the output signal is very low, for example, on the order of 20Hz, or when a load impedance is lowered due to short-circuiting of the load, a large current will flow, particularly in one direction, in the low pass filter. This current causes overcharging of a smoothing condenser of a rectifying circuit forming a DC power supply for the amplifier, and hence the level of the DC output voltage of the rectifying circuit rises unacceptably to destroy the smoothing condenser or to damage an amplifying switching element of the amplifier.

An object of this invention is to provide a pulse width modulated signal amplifier which is free of the above described defect.

Another object is to provide a pulse width modulated signal amplifier which can effectively prevent a smoothing condenser of the DC power supply from being destroyed in a no-load condition.

A further object of this invention is to provide a pulse width modulated signal amplifier, as aforesaid, which can effectively prevent damage to an amplifying switching element in the no-load condition.

Still another object is to provide a pulse width modulated signal amplifier, as aforesaid, in which a detecting signal is obtained when a DC power supply voltage exceeds a predetermined value.

An additional object of this invention is to provide a pulse width modulated signal amplifier, as aforesaid, in which when a DC power supply voltage exceeds a predetermined value, an output signal is not supplied to a signal output terminal of the amplifier.

A still further object of this invention is to provide a pulse width modulated signal amplifier in which the protecting circuit functioning at a time when a DC power supply voltage exceeds a predetermined value to prevent damage to a smoothing condenser or to an amplifying switching element, also serves as a muting circuit upon turning-on of the power supply.

According to an aspect of this invention, a pulse width modulated signal amplifier comprises a DC power supply, a pulse width modulated signal amplifying circuit having amplifying switching means operated by DC voltages from the DC power supply and driven in response to a pulse width modulated signal for normally providing a demodulated signal through a low pass filter to a signal output terminal, and a detecting circuit for detecting the level of the DC voltages from the power supply so as to provide a detecting signal when either of the DC voltages exceeds a predetermined value. The occurrence of such detecting signal is desirably employed to cause a protective circuit to prevent the application of the demodulated output to the signal output terminal, whereby to avoid damage to smoothing condensers associated with the DC power supply or to the amplifying switching means, for example, as when a DC voltage from the DC power supply is excessively increased due to a very low frequency of the demodulated output signal or due to a lowered load impedance, as by short-circuiting of the load connected to the signal output terminal.

The above, and other objects, features and advantages of the present invention, will be apparent from the following description which is to be read in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulse width modulated signal amplifier according to this invention; and

FIGS. 2A to 2D and FIGS. 3A to 3D are respective waveforms to which reference will be made in explaining operation of the pulse width modulated signal amplifier according to this invention illustrated on FIG. 1.

Referring to the drawings in detail and initially to FIG. 1 thereof, it will be seen that a pulse width modulated signal amplifier according to this invention is there illustrated to generally comprise a DC power supply 1 including a power transformer 2, rectifing means 3 and a constant voltage circuit 4, an amplifying circuit 5, and a detecting circuit 6.

More particularly, in the DC power supply 1 of the illustrated embodiment, power transformer 2 is shown to have a primary winding 2a and a secondary winding 2b. A commercial AC voltage of 100 volts is applied to primary winding 2a between its input terminals T.sub.01 and T.sub.02. The secondary winding 2b is grounded at its mid-point and connected at its opposite ends to rectifying means 3 consisting of a pair of rectifying circuits 3A and 3B from which are respectively derived positive and negative DC voltages. The rectifying circuit 3A is formed of rectifying diodes D.sub.1 and D.sub.2 and a smoothing condenser C.sub.1a so that a positive DC voltage can be obtained at an output terminal T.sub.11. Similarly, rectifying circuit 3B is formed of rectifying diodes D.sub.3 and D.sub.4 and a smoothing condenser C.sub.1b so that a negative DC voltage can be obtained at an output terminal T.sub.12. The junction between smoothing condensers C.sub.1a and C.sub.1b is grounded.

The rectifying means 3 is connected at its output side with constant voltage circuit 4 which is shown to consist of a pair of voltage regulating circuits 4A and 4B. The voltage regulating circuit 4A is formed of a pair of voltage regulating NPN-type transistors Q.sub.1a and Q.sub.2a having a Darlington configuration, an NPN-type transistor Q.sub.3a for comparison, a Zener diode D.sub.z serving as a reference voltage element, and a series circuit of resistors R.sub.1 and R.sub.2 serving as a load voltage detecting circuit.

The collector of transistor Q.sub.1a is connected to the terminal T.sub.11 and the emitter thereof is connected to a DC output terminal T.sub.21. The base of transistor Q.sub.2a is connected to the collector of transistor Q.sub.3a and the emitter of transistor Q.sub.3a is connected to the cathode of Zener diode D.sub.z which has its anode grounded. The series circuit of resistors R.sub.1 and R.sub.2 is connected between DC output terminal T.sub.21 and the ground and the junction between resistors R.sub.1 and R.sub.2 is connected to the base of transistor Q.sub.3a. Between the terminal T.sub.21 and the ground is further connected a smoothing condenser C.sub.2a so that a constant positive DC voltage can be obtained at terminal T.sub.21.

The voltage regulating circuit 4B is formed of a pair of voltage regulating PNP-type transistors Q.sub.1b and Q.sub.2b having a Darlington configuration, a PNP-type transistor Q.sub.3b for comparison, and a series circuit of load voltage detecting resistors R.sub.3 and R.sub.4. The collector of transistor Q.sub.1b is connected to terminal T.sub.12 and the emitter thereof is connected to a DC output terminal T.sub.22. The base of transistor Q.sub.2b is connected to the collector of transistor Q.sub.3b and the emitter of transistor Q.sub.3b is grounded. The series circuit of resistor R.sub.3 and R.sub.4 is connected between terminals T.sub.21 and T.sub.22, and the junction between resistors R.sub.3 and R.sub.4 is connected to the base of transistor Q.sub.3b. Between the terminal T.sub.22 and the ground is connected a smoothing condenser C.sub.2b so that a constant negative DC voltages can be obtained at terminal T.sub.22.

In the amplifying circuit 5, an input terminal 7 is provided to receive a pulse width modulated signal (a rectangular wave signal) such as is shown on FIGS. 2A and 3A. Such incoming pulse width modulated signal is applied through input terminal 7 to a driving circuit 8 to derive therefrom positive and negative half-cycle signals which are supplied to the gates of P- and N-channel amplifying field effect transistors or FETs Q.sub.9a and Q.sub.9b to turn these FETs ON and OFF alternatively. The sources of FETs Q.sub.9a and Q.sub.9b are respectively connected to DC output terminals T.sub.21 and T.sub.22 for obtaining therefrom the positive and negative DC voltages of DC power supply 1, and the drains of FETs Q.sub.9a and Q.sub.9b are connected together to a low pass filter 9 consisting of a coil 10 and a condenser 11. The demodulated output of low pass filter 9, which may be an audio signal, is intended to be supplied to a load L, for example, in the form of a loudspeaker, by way of a signal output terminal 12.

The detecting circuit 6 provided according to this invention for detecting the level of a DC voltage derived from rectifying means 3 of DC power supply 1 is shown to include a series circuit of resistors R.sub.5 and R.sub.6 connected between terminals T.sub.21 and T.sub.22. The junction between resistors R.sub.5 and R.sub.6 is connected to the base of an NPN-type transistor Q.sub.4 and to the emitter of an NPN-type transistor Q.sub.5. A resistor R.sub.7 is connected between the ground and the base of transistor Q.sub.4 to determine detection sensitivity by its resistance value. The emitter of transistor Q.sub.4 and the base of transistor Q.sub.5 are connected together to ground. The collectors of transistors Q.sub.4 and Q.sub.5 are connected together to the base of a PNP-type transistor Q.sub.8. Between terminal T.sub.21 and the ground is connected a series circuit of resistors R.sub.9 and R.sub.10 for forming a bias voltage and the junction therebetween is connected through a resistor R.sub.8 to the collector of transistor Q.sub.8 and to the base of a PNP-type transistor Q.sub.6. The emitters of transistors Ql.sub.6 and Q.sub.8 are connected together to terminal T.sub.21. A condenser C.sub.3 is connected between the emitter and base of transistor Q.sub.6. The collector of transistor Q.sub.6 is connected to the base of an NPN-type transistor Q.sub.7 and the base of transistor Q.sub.6 is connected to the collector of transistor Q.sub.7 to form a thryistor configuration.

Further, in accordance with this invention, in the pulse width modulated signal amplifying circuit 5, between low pass filter 9 and signal output terminal 12 is provided a contact 14 of a relay 13 and the emitter of transistor Q.sub.7 is connected to ground through a coil 15 of relay 13.

Operation of the pulse width modulated signal amplifier shown on FIG. 1 will now be described with reference to FIGS. 2A to 2D and FIGS. 3A to 3D:

If it is assumed that an unmodulated pulse signal having a duty cycle of 50%, as shown on FIG. 2A, is supplied to input terminal 7 of pulse width modulated signal amplifying circuit 5, a current I.sub.1 flows through the source-drain of FET Q.sub.9a and has a triangular wave signal with symmetrically positive and negative portions, as shown in FIG. 2B, only during each interval where the pulse signal of FIG. 2A is positive. Similarly, a current I.sub.2 flows through the source-drain of FET Q.sub.9b and has a triangular wave signal with symmetrically positive and negative portions, as shown on FIG. 2C, only during each interval where the pulse of FIG. 2A is negative. As a result, a triangular wave signal current I.sub.3 having symmetrically positive and negative portions, as shown on FIG. 2D, flows through coil 10 of low pass filter 9. Such signal current I.sub.3, when integrated by the low pass filter 9, results in zero, so that no signal current flows through load L.

If l is an inductance of coil 10, i is a current flowing through coil 10 and E.sub.l is a voltage across coil 10, the following equation is obtained:

Accordingly, the current increasing factor is expressed as follows:

When there is no modulation, E.sub.l becomes equal to the DC power supply voltage E.sub.1.

When the input terminal 7 receives a signal which is modulated in pulse width by a positive audio signal, its waveform has a duty cycle other than 50%, as shown on FIG. 3A. Accordingly, the currents I.sub.1 and I.sub.2 flowing through the source-drains of FETs Q.sub.9a and Q.sub.9b, respectively, are symmetric relative to their positive and negative portions, as shown on FIGS. 3B and 3C, that is each of currents I.sub.1 and I.sub.2 has a relatively larger positive portion in this example. The current I.sub.3 flowing through the coil 10 of low pass filter 9 is also asymmetric, in respect to its positive and negative portions, as shown on FIG. 3D, that is, current I.sub.3 becomes a triangular wave current having larger positive portions than negative portions in the case where the signal applied to input terminal 7 is modulated in pulse width by a positive audio signal. As a result, when the triangular wave signal I.sub.3 of FIG. 3D is integrated by the low pass filter 9, a DC positive current is supplied to the load L. If E.sub.o is the DC positive voltage across the load L, the following relation is obtained during a positive interval of the pulse signal of FIG. 3A,

and, during a negative interval of the pulse signal of FIG. 3A,

When the frequency of the pulse width modulated signal supplied to input terminal 7 is very low, for example, on the order of about 20 Hz, and/or when the load impedance is lowered, a large current, in this case a DC positive current, flows through load L. When the pulse signal is modulated by a positive audio signal, the current flowing through the FET Q.sub.9a connected to the positive DC output terminal T.sub.21 is increased in the forward direction, while the current flowing through the FET Q.sub.9b connected to the negative DC output terminal T.sub.22 is increased in the backward direction, as is apparent from FIGS. 3B and 3C, respectively. Consequently, the smoothing condenser C.sub.2b associated with the rectifying circuit 3B for producing the negative DC voltage is charged to increase the voltage between terminals T.sub.21 and T.sub.22. A similar situation occurs when a negative DC current flows through the load L. In either case, as the absolute value of the positive DC voltage at terminal T.sub.21 rises or the absolute value of the negative DC voltage at terminal T.sub.22 rises, such fact is detected by circuit 6, that is, transistor Q.sub.4 or Q.sub.5 is turned ON to make transistor Q.sub.8 conductive. Normally, the electric charge on condenser C.sub.3 applies a predetermined voltage between the emitter and base of transistor Q.sub.6 to keep it conductive. However, the condenser C.sub.3 is short-circuited by the emitter-collector of transistor Q.sub.8 when the latter is turned ON so that condenser C.sub.3 is discharged and hence transistor Q.sub.6 is turned OFF. As a result of the foregoing, transistor Q.sub.7, which was in a conductive state, is also turned OFF and hence the coil 15 of relay 13 is de-energized with the result that its contact 14 is opened. The opening of contact 14 prevents the appearance at signal output terminal 12 of the demodulated output signal from low pass filter 9.

Of course, in the normal operating condition of the amplifier, that is, when the DC voltages at terminals T.sub.21 and T.sub.22 do not exceed the predetermined value, transistors Q.sub.4, Q.sub.5 and Q.sub.8 are OFF and transistors Q.sub.6 and Q.sub.7 are ON so that coil 15 of relay 13 is energized to close contact 14 and thereby transmit the demodulated output signal to signal output terminal 12.

It will be noted that, upon turning-on of the power supply 1, condenser C.sub.3 and resistor R.sub.8 of detecting circuit 6 function as a muting circuit. More particularly, condenser C.sub.3 and resistor R.sub.8 constitute a time constant circuit to delay the turning ON of transistor Q.sub.6, and hence of transistor Q.sub.7, until condenser C.sub.3 has been charged. Therefore, until such time as condenser C.sub.3 is charged following the turning-ON of power supply 1, relay coil 15 remains de-energized to open contact 14 and thereby prevent the transmission of the output signal to terminal 12.

In the above-described embodiment of the invention, when the DC voltage of rectifying circuit 3 applied through constant voltage circuit 4 to terminals T.sub.21 and T.sub.22 exceeds a predetermined value and is detected by detecting circuit 6, damage to the smooth condensers C.sub.2a, C.sub.2b or to the amplifying switching devices Q.sub.9a, Q.sub.9b is avoided by opening of contact 14 in response to the detecting circuit 6 to prevent the application of the output signal from amplifying circuit 5 to the load L. However, condensers C.sub.2a, C.sub.2b and amplifying switching devices or FETs Q.sub.9a and Q.sub.9b may be similarly protected from damage by causing detecting circuit 6, when it detects an excessive DC voltage at terminal T.sub.21 or T.sub.22, to suitably lower the DC voltage from rectifying circuit 3, or to disconnect the source of the pulse width modulated signal from input terminal 8 of amplifying circuit 5, or to halt the operation of driving circuit 8.

Although an illustrative embodiment of the invention has been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.