Digital Recognition Circuits

The present invention relates to digital communications and more particularly, but not exclusively, to apparatus for detecting a particular sequence of digits and for detecting errors in the digits.

In digital communications which is meant to include digital recording and/or reproduction as well as digital transmission, information is transmitted in the form or words which consist of a number, often 4 or 8 of bits. The words are transmitted in series, and it is possible that due to errors in transmission or reception the whole of each word may not be received. Unless the reception or reproduction equipment can recognize errors and is given a reference from which to start, the information can become completely garbled.

The present invention provides apparatus for monitoring digital words made up from a plurality of digits comprising storage means for storing the digits of digital words, recognition means connected to said storage means for producing an output signal indicative of the number of correct digits stored, and comparison means for comparing said output signal with a reference signal and producing and indication of the result of the comparison.

An embodiment has been designed for use in the recording and reproduction of video signals and is arranged to identify a digital word representing the start of a block of data e. g. of a line of a video scan in order to synchronize subsequent equipment.

In order that the present invention be more readily understood, an embodiment thereof will now be described with reference to the accompanying drawing, the single FIGURE of which shows:

A BLOCK DIAGRAM OF APPARATUS FOR DETECTING A PARTICULAR SEQUENCE OF DIGITS.

Referring to the drawing, serial digital information is fed to a clock generator circuit 10 which recovers clock pulse information from the digital information and produces clock pulses for clocking the information into a shift register 11 of sufficient capacity to store the word identifying the start of a line of a video scan. The serial digital information is also fed directly to the shift register 11 where it is stored and shifted in response to the clock pulses from the clock generator 10. In the present instance, the shift register has 16 locations each of which has two outputs, one being a true output and the other being an inverted output. The outputs from the shift register 11 are arranged to produce a pre-determined pattern of digits when the correct word is assembled and to produce from two programmable read only memories 12 and 13 a predetermined number when all the 16 locations are correctly filled.

This is achieved in the particular embodiment by feeding the outputs from the 16 locations of the shift register 11 through sixteen switches 14. The two outputs of one location are fed to two poles of one switch 14 in such a way that only one output can be transmitted through the switch to an input of the memories 12,13. The switches 14 are preferably digital switches in the form of logic gates to produce a succession of logic ones to the 8 bit addres of each of the memories 12 and 13 when the correct 16 bit word is inserted into the shift register 11. For the switch arrangement shown, the start word is:

The memories each produce a 4 bit output indicative of the number of correct signals fed through the switches 14 to their addresses. The corrected signals are selected to be ones but could equally be zeros. More Specifically, each of the memories will produce a binary output indicative of a number from 0 to 8.

The outputs from the memories 12 and 13 are added together by an adding circuit 15 and fed to inputs 6A of a comparator 16 where they are compared with a reference value fed to the comparator via inputs B. The reference value is indicative of an acceptable limit to the number of correct bits in the shift register 11. The reference may be the lower acceptable limit for the number of correct bits, as shown in the diagram. In this case if, for example, the limit is 14, an output is produced from the comparator 16 if the sum is greater than or equal to the reference. Thus a maximum of two incorrect bits in the shift register 11 will produce an output. Alternatively, the reference may be the upper limit for the number of errors e.g., 2 in which case an output is produced if the sum produces a number of errors less than or equal to the reference.

The output from the comparator is held by an output latch 17 for the duration of the clock pulse from the clock generator 10 and in this way latch 17 produces at its output a recognition pulse.

In the above description, it has been assumed that the memories produce which is linear with respect to their input, i.e., six correct inputs will produce the binary representation of six. This need not be the case, however, and in some cases a non linear relationship may be preferred. For example, it may be determined that if two adjacent locations in the shift register produce incorrect outputs then this is more detrimental than two spaced incorrect outputs in which case the memories can be programmed to produce an output which is representative of, say, 4 rather than 6 as would otherwise be the case.

It is preferred to inhibit the apparatus described above until just before a start word should appear. This is best achieved by feeding an inhibiting signal to the latch 17. For regularly spaced start words, the inhibiting signal may be produced by a timer which thus switches the apparatus off for a predetermined period of time after a start word has been recognized. It is sometimes advantageous to precede the start word by a preamble of say, alternate ones and zeros to ensure a good clock recovery component and to be unlike a start word.

The apparatus has been described above as recognizing a single start word per line but it can also be used to identify a further reference word or words which can be inserted in between words representing locations along a line of a video scan or during the field blanking. Thus, the mid-line can also be recognised. This can be achieved by altering the switches to represent another pattern producing a succession of ones when the correct 16 bits are in the shift register 11. Alternatively, there need not be a start word every line, all that is required is that blocks of data are broken up occasionally by a start word. However, it is preferred to use at least one start word for every line of video.

The embodiment is of general application in digital recording or transmission and can be used for audio as well as video signals. It is however of particular application for colour T.V. video signals.