Method and System for Squelching Decaying Current in Motor Phases

This invention relates generally to the control of an inductively controlled multi-phase motor. More specifically, it relates to the control of a stepper motor whose rotational motion is translated into linear motion.

While the invention is useful in the control of stepper motors for a wide variety of applications, in the preferred embodiment it is used to control a stepper motor for positioning the printhead of a thermal printing mechanism. A typical prior art system is that disclosed and claimed in U.S. patent application Ser. No. 456,496, filed Apr. 1, 1974, now U.S. Pat. No. 3,953,778, and entitled "Motion Control System for an Inductively Controlled Multi-Phase Motor," and in U.S. patent application Ser. No. 452,320, filed Mar. 18, 1974, now abandoned, and entitled "Switching Regulator Control for Inductively Controlled Electro-Mechanical Device." Briefly, the prior art system included means for selectively enabling the individual phases of the stepper motor. A switching regulator circuit controls the average value of the current flowing in an enabled phase. The regulator includes a small resistance coupled to the phase windings of the motor such that the current flowing in an enabled winding flows through the resistor. The voltage developed across the resistor, which is proportional to the current flowing in the enabled winding, provides an input to one side of a voltage comparator. The other voltage to the comparator is a controllable voltage reference. When a phase is enabled, and when the voltage representing the current flowing in the winding is less than the reference voltage, a transistor switch couples the phase winding to a supply voltage. When the current flowing in the phase winding is large enough to cause the resistor voltage to exceed that of the reference voltage, the power transistor is turned off, thereby decoupling the phase winding from the supply voltage. At this time the decaying current in the phase winding causes the voltage across the winding to change polarity, and the decaying current is caused to flow through a recovery circuit comprising the series combination of a resistor and a diode. This recovery circuit also provides the path for a decaying phase winding current when the enabling means for that particular phase is disabled.

There are several disadvantages associated with the use of the prior art type of recovery circuit. First, since it is desired to minimize the current ripple in an enabled phase as the switching regulator switches on and off, the resistor in the recovery path must have a relatively low value of resistance. When, however, a phase is disabled and the next phase enabled so as to cause the stepper motor to rotate, it is desired that the current in the disabled phase rapidly decay to zero. The low resistance of the resistor in the recovery path, however, is not suitable to provide this desired rapid current decay. It will be appreciated, therefore, that the resistance value of the resistor in the recovery circuit represents a compromise between two conflicting requirements.

A further disadvantage of the prior art recovery circuit stems from the fact that energy is wasted in the recovery resistor during those portions of the switching regulator cycle when the regulator is turned off.

It is an object, therefore, of the present invention to provide a control system for a stepper motor wherein the switching regulator action causes relatively small ripple on the current flowing in a motor winding, while the decaying current in a disabled motor winding may be rapidly brought to zero.

It is another object of the invention to provide a controller for a stepper motor having reduced losses.

Briefly, in the controller of the present invention, the resistor of the prior art recovery circuit is replaced by a network for controlling the decaying current in a phase of the stepper motor. When an input logic signal to the network occupies a first state, the network functions so as to provide almost no impedance to the flow of current therethrough. The series combination of the network and a flyback diode comprise the return path for the decaying current flowing in a motor phase winding. This low impedance state is employed when the motor phase is de-energized by the action of the switching regulator, and also at those times when the motor phase is disabled by its enabling circuit if there is no need to rapidly quench the inductively maintained current flow.

When, however, one phase of the stepper motor is disabled and an adjacent phase enabled so as to cause rotation of the stepper motor, rapid acceleration of the motor may be desired. In this case, the input logic signal to the network is changed to a second state. This has the affect of changing the operation of the network so that it provides a finite time varying impedance to the flow of current therethrough. In the preferred embodiment of the invention the nature of the impedance variation is such as to maintain the voltage across the disabled motor phase winding substantially constant. This in turn has the affect of causing the inductive current in the winding to decay rapidly and linearly to zero. When the stepper motor is used to control the position of a thermal printhead, the switchable nature of the network may be used to advantage in both the print/step and carriage return modes of operation so as to provide smooth, efficient, and noise free operation of the printhead.

Other objects and features of the invention will become clear through a consideration of the following detailed description taken in connection with the accompanying drawings wherein:

FIG. 1 is a block diagram of a portion of the controller.

FIG. 2 is a detailed block diagram of the logic section.

FIG. 3 is a schematic diagram of the address decode circuit.

FIG. 4 is a schematic diagram of the motor driver circuit.

FIG. 5a shows the position sensor.

FIG. 5b shows the output signal of the position sensor.

FIG. 6 is a timing diagram for the print/step sequence.

FIG. 7 is a flow diagram for the carriage return sequence.

There is shown in FIG. 1 a block diagram of a portable thermal printing computer terminal in which the present invention may be used. There is shown at 10, a logic section which in the preferred embodiment comprises first a central processing unit (CPU). The CPU may be a model TMS8080 microprocessor functioning under the control of ROM storage which comprises two Model TMS4700 ROMS, each of which has 1,000 words of eight bit storage. A Model TMS4036 RAM provides 64 words of eight bit storage. Both parallel and serial data input and output services, as well as masked prioritized interrupts and interval timers, are provided by a Model TMS5501 I/O chip. Each of the above referenced TMS devices is available from Texas Instruments Incorporated of Dallas, Texas. Address decode circuits of the type well known in the art respond to the digital addresses provided by the microprocessor to properly address other system elements.

A thermal printhead 12 may be of the type disclosed and claimed in co-pending U.S. Pat. application Ser. No. 533,427, filed Dec. 16, 1974, and entitled "Thermal Printhead with Memory." This thermal printhead, in the preferred embodiment, comprises a 5.times.7 element array of electrically and thermally isolated semiconductor mesas. The mesas, when selectively heated, serve to print alpha-numeric or other characters on thermally sensitive paper. For any given character, the 5.times.7 matrix of mesas is addressed using an x-y coincidence addressing technique. During a relatively brief address period, the columns of mesas are strobed "ON" sequentially by signals appearing on the five column (X) input lines. As each column is strobed, those mesas in the column which are to be heated are turned on by signals appearing on the seven row (Y) input lines. After all five columns have been strobed, the mesas which have been addressed remain on for a print period which is long in comparison with the address period. After the print period, the supply voltage is removed from all mesas, thereby turning them off in preparation for printing of the next character.

The lowest order 12 bits of the 16 bit address bus of the microprocessor are connected by lines 14 to the X and Y printhead drivers 16 and 18. The lowest order 7 bits are coupled to the Y printhead drivers 18 while bits 7 through 11 are coupled to the X printhead drivers 16. During a printing operation, one of bits 7 through 11 will be high to indicate which of the columns of the printhead is to be strobed. At the same time, the bits 0 through 6 will be selectively high to indicate which of the mesas of that column are to be heated. At the same time, a high level bit 13 on the address bus is utilized by the address decode circuit to apply a printhead strobe pulse to printhead drivers 16 and 18, thereby causing the drivers to couple the information on the address bus to the printhead terminals. This procedure is repeated five times so as to sequentially strobe the five columns of the printhead.

Printhead 12 is mounted on a carriage which operates in response to logic signals from the controller to move from one to another of the print positions and to slew to the left in a carriage return mode. The carriage is positioned by a cable which is in turn driven by a three phase stepper motor. The arrangement of the stepper motor, cable, and carriage are of the type well known in the art and need not be further discussed here.

Eight bit data words from the microprocessor are coupled by the I/O chip to parallel output bus 20. The data words are coupled through driver buffer 22, which in the preferred embodiment, simply comprises a Model SN7406 inverter in each of the eight lines of bus 20. The inverters serve to match the signal levels of the I/O chip to the signal levels required by the TTL control registers 24 and 26 and by the keyboard 28. Control registers 24 and 26 may comprise an SN 74174 and SN 74175 integrated circuit, respectively. Selected bits appearing at the output of driver buffer 22 are coupled to the inputs of control registers 24 and 26. During printhead operations, signals from the address decode circuit of logic network 10 strobe these bits onto the output terminals of the control registers 24 and 26 to control printing and motion of the printhead.

Selected output bits from driver buffer 22 are also connected to the row scan lines of keyboard 28. Periodically, keyboard 28 is scanned using these row inputs and detected key depressions are coupled to 8 bit input bus 30. Data appearing on 8 bit input bus 30 in turn is coupled by the I/O to the microprocessor. The interface between keyboard 28 and the control logic is of a type known in the art and need not be further discussed here.

Logic network 10 communicates with external systems such as a remote terminal through the I/O chip on a serial transmit channel 32 and a serial receive channel 34. Serial transmit and receive channels 32 and 34 may be coupled to a telephone line by means of a modem assembly as is well known in the art.

The signal from a position sensor is coupled by line 36 to logic network 10 wherein the I/O chip couples this signal to the CPU.

Logic network 10 is shown in greater detail in FIGS. 2 and 3, the latter figure disclosing the details of the address decode circuits. With reference to FIG. 2, CPU 40 comprises a microprocessor, which as previously noted in the preferred embodiment is a Model TMS8080 device. CPU 40 operates under control of ROMs 42 and 44. In addition to the instruction sequence for the CPU, ROMs 42 and 44 contain tables such as a table of delay times for switching phases on the stepper motor as the printhead carriage travels from column 12 to column 1 in the carriage return mode. Temporary storage for CPU 40 is provided by RAM 46. Finally, input/output services for the CPU are provided by I/O chip 48.

CPU 40 has an 8 bit data word which is coupled to each of ROMs 42 and 44, RAM 46, and I/O chip 48 by 8 bit data bus 50. CPU 40 has a 16 bit address word which is coupled by address bus 52 to the various elements of logic network 10. Bits A0 through A9 of the address word are coupled to the 10 address inputs of each of ROMs 42 and 44. Bits A0 through A5 of the address word are coupled to the six address inputs of RAM 46. Bits A0 through A3 of the address word are coupled to the four address inputs of I/O chip 48. Finally, bit A15 of the address word is coupled to the chip enable input of I/O chip 48.

The clock inputs of CPU 40 and I/O chip 48 are provided on lines 54 and 56 from a two phase clock. The clock has period of 500 nanoseconds. The sync output of CPU 40 is coupled by line 58 to the sync input of I/O chip 48. Interrupt signals from I/O chip 48 are coupled by line 60 to the interrupt input of CPU 40. THe CPU DBIN signal is coupled by line 62 to the CS2 inputs of ROMs 42 and 44 and to the DBFL input of RAM 46. Line 64 couples the WR output of CPU 40 to the R/W input of RAM 46. Various signals appearing in FIG. 2 are coupled to the address decode circuit of FIG. 3, these including the SYNC, WR, and WAIT outputs of CPU 40, as well as bits A10, A12, A13 and A14 of the address bus. Signals from the address decode circuit are coupled to the CS1 terminals of ROMs 42 and 44 and to the CS terminal of RAM 46.

The position sensor signal is coupled by line 36 to the SEN terminal of I/O chip 48. The serial output and input channels 32 and 34 connect to the XMT and RCV terminals, respectively, of the I/O chip. The 8 bit parallel output word X0 is connected by output bus 20 to the driver buffer 22. Data from the keyboard is coupled by 8 bit input bus 30 to the 8 XI terminals of I/O chip 48.

The address decode circuits as illustrated in FIG. 3 respond to bits A10, A12, A13 and A14 of the address bus to selectively energize various elements of the control system. Decoder 70 in the preferred embodiment is a Model 74LS138 TTL integrated circuit. Address bits A12, A13, and A14 are coupled respectively to the A, B and C inputs of decoder 70 by lines 72, 74 and 76. When the G1 and G2A inputs of decoder 70 are connected as shown and when the G2B input is in the low logic state, all but one of the Y output terminals will have a high logic level, the single Y output terminal in the low state being determined by the state of the A, B and C inputs as shown in Table I.

The A10 bit of the address bus is coupled by line 78 to one input of NAND gate 80 and through inverter 82 to one input of NAND gate 84. The Y0 output of decoder 70 is coupled through inverter 86 to the other input of each of NAND gates 80 and 84. If the A, B, and C inputs of decoder 70 are 000, the resulting low level of the Y0 output will cause one of NAND gates 80 and 84 to have a low level output. If, for example, the A10 bit of the address bus is low, the output of NAND gate 84 will be low thereby enabling ROM 42. Alternatively, if the A10 bit is high ROM 44 will be enabled by NAND gate 80. When the A, B, and C inputs of decoder are 001, the resulting low level Y1 output signal enables RAM 46 through line 90. Lines 92 and 94 couple the the Y4 and Y5 outputs to one input of each of OR gates 96 and 98. When the decoder 70 input is 100, the resulting Y4 output low logic level causes a low logic level at the output of OR gate 96. This is coupled to the clock input of control register 24 which simply comprises a plurality of D flip flops, one in each line of the control register. The low level clock input to the control register transfers the information from the D inputs of the flip flops to their outputs so as to provide appropriate PRINT, FAST, STEP, and phase control signals to the carriage drive electronics. Similarly, a 101 input to decoder 70 results in a low level Y5 output and ultimately in a low level at the output of OR gate 98. This low level signal clocks the D flip flops of control register 26 so as to provide appropriate bell, linefeed, and headlift signals. Clocking of control registers 24 and 26 is inhibited, however, when the CPU write signal WR appearing on line 100 is in the high logic level.

The SYNC output of CPU 40 is coupled by inverters 102 and 104 to one input of AND gate 106. The high level SYNC signal which occurs at the beginning of each machine cycle of the CPU, gates one pulse from clock phase one through AND gate 106 to the clock input of JK flip flop 108. Each of JK flip flops 108 and 110 may be a Model 74109 integrated circuit. While the SYNC signal is high at the beginning of each machine cycle, the 8 bit data output bus of CPU 40 contains status bits from the CPU. The D0 status bit, which is coupled through inverter 112 to the J and K inputs of flip flop 108, is high if the machine cycle is an interrupt acknowledge and is low for all other types of machine cycles. Flip flop 108, when connected as shown in FIG. 3, operates as a D flip flop. Accordingly, if the machine cycle is not an interrupt acknowledge, the Q output of flip flop 108 is clocked to a high level, this signal being coupled by line 120 to one input of AND gate 116. During this portion of the machine cycle, the WAIT output of CPU 40 appearing on line 118 is low. This low level is inverted by inverter 114 to present a high level to a second input of AND gate 116. If the machine cycle is not one in which the CPU communicates with I/O chip 48, the Y7 output of encoder 70 which is coupled by line 122 to a third input of AND gate 116 will also be high.

The resultant high level at the output of AND gate 116 is inverted by inverter 124 to a low level READY signal appearing on line 126. This low level READY signal is tested by CPU 40 during the second state of the machine cycle, and the low level READY signal causes the WAIT output of CPU 40 to go high at the end of the second state. This high level WAIT signal, after inversion by inverter 114, causes the output of AND gate 116 to go low, thereby resulting in a high level READY signal. The high level READY signal permits the CPU to read from or write on the data bus during the third state of the machine cycle.

If, in contrast with the foregoing, the machine cycle is an interrupt acknowledge, the D0 line of the data bus will be high during the SYNC pulse that initiates the machine cycle. This high level D0 is inverted by inverter 112 and clocked to the Q output of flip flop 108 by a clock pulse. The low level Q output causes the output of AND gate 116 to be low so that the READY signal is high when tested during the second state of the machine cycle. As a result, CPU 40 can pass directly to the third state of the machine cycle without encountering a WAIT state. It should also be noted that under these conditions, the high level Q output of flip flop 108, coupled by line 109 to the G2B input of decoder 70, inhibits the decoder from "reading" the address bits during an interrupt acknowledge.

The WAIT state is also skipped when the Y7 output of decoder 70 is low during the second state of a machine cycle.

The Q output of flip flop 110 appears on line 128 and is used to strobe printhead drivers 16 and 18. The Y2 output of decoder 70 (normally at a high logic level) is inverted by inverter 130 and the resultant low level logic signal presets the Q output of flip flop 110 to a low logic level. This preset is released only when the Y2 output of decoder 70 goes low, that is when the decoder input is 010. With the Y2 output low, the Q output of flip flop 110 is controlled by its J and K inputs. The high level SYNC pulse which initiates a machine cycle to strobe the printhead, is inverted by inverter 102 to provide a low level K input to flip flop 110. At the same time, the WAIT signal appearing on line 118 is low during this portion of the machine cycle so that the flip flop also has a low level J input. Under these conditions, the clock pulse from clock phase 1 switches the Q output of flip flop 110 to a high state. When the next clock pulse occurs, the WAIT signal appearing on line 118 will still be low but the inverted SYNC signal appearing at the K input of flip flop 110 will be high. Under these conditions, the clock signal will cause the Q output to remain in the state that it occupied just prior to the clock pulse, that is, the high state. At the time of the next succeeding clock pulse, the WAIT signal will have gone high so that both inputs to flip flop 110 are high with the result that the clock pulse switches the Q output back to the low state. It will be seen, therefore, that a print strobe machine cycle will cause the Q output appearing on line 128 to go high for a time period equal to the duration of two clock cycles. In the preferred embodiment where the clock pulses have a period of 500 nanoseconds, the printhead driver signals on line 128 remain high for one microsecond. The printhead drivers comprise a set of 12 AND gates, one in each of the 5 X and 7 Y printhead drive lines. The printhead drive signal appearing on line 128 is coupled to one input of each of these AND gates. Accordingly, a high level printhead drive signal gates the corresponding X and Y signals through the printhead drivers to the printhead itself.

In FIG. 4 is shown a schematic diagram of the stepper motor drive circuit which, subject to certain important exceptions, is similar to that disclosed in the aforementioned U.S. patent application Ser. No. 452,320. With reference to FIG. 4, the PHASE A signal from control register 24 is coupled to the base of transistor 140 and through resistor 142 to a +5 volt supply. Transistor 140 has its collector referenced through resistor 144 to a +30 volt supply and its emitter through resistor 146 to the output of comparator amplifier 148. The collector of transistor 140 is connected to the base of transistor 150, whose emitter is connected to the +30 volt supply. The collector of transistor 150 is connected to the base of transistor 152 and through resistor 154 to the emitter of transistor 152. The collector of transistor 152 is coupled to the +30 volt supply while its emitter is further coupled to the PHASE A winding 156 of the stepper motor. The opposite end of the PHASE A winding is coupled through current sensing resistor 158 to ground. The ungrounded side of current sensing 158 is connected through resistor 159 to capacitor 160 and to the noninverting input of comparator amplifier 148. The junction between the emitter of transistor 152 and stepper motor coil 156 is also connected to the cathode of "catch" diode 162. The anode of catch diode 162 is connected to a network indicated generally by reference designator 164. Network 164 replaces the recovery resistor normally found at this point in similar circuits.

As seen in FIG. 4, the current drive circuits for the PHASE B and C coils of the stepper motor are identical to that just described for PHASE A and no further discussion of these circuits is required here.

The step signal from control register 24 is connected to resistors 166 and 168, the former being coupled at its other end to the +5 volt supply voltage and the latter being coupled at its other end to the base of transitor 170. The base of transitor 170 is also connected through resistor 172 to ground and the emitter of transistor 170 is grounded. The collector of transitor 170 is connected through resistor 174 to the +5 volt supply and also to the base of transistor 176. Transistor 176 has its emitter grounded while its collector is referenced through variable resistor 178 to a +12 volt supply. The collector of transistor 176 is is also connected through resistor 180 to one end of resistor 182, the other end of this resistor being grounded. The junction between resistors 180 and 182 is also connected through resistor 184 to the inverting input of comparator amplifier 148 and to one end of capacitor 160. Finally, the junction between resistors 180, 182 and 184 is also coupled through resistor 186 to the cathode of zener diode 188, the anode of this diode being grounded. The cathode of diode 188 is also connected through resistor 190 to the +12 volt supply.

A clock input is coupled through capacitor 161, resistor 163, and resistor 165 to the junction between resistors 158 and 159. The junction between resistors 163 and 165 is also coupled through capacitor 167 to ground. The clock input which has a frequency of 20.8 KHZ synchronizes the switching action of the regulator and is chosen to be outside the audible frequency range of human beings.

The circuit of FIG. 4, in response to phase control signals at the PHASE A, B and C input terminals, serves to selectively energize one of the windings of the stepper motor. Further, in response to the CLOCK, STEP and FAST inputs, the circuit functions in a switching regulator mode to control the average current flowing in the selected motor winding. The current in the selected winding flows through current sensing resistor 158 to ground and generates a voltage across that resistor proportional to the current flowing in the selected winding. This voltage is mixed with the clock input signal and the combined signal is coupled to the noninverting terminal of comparator 148. A voltage reference controlled by the "STEP" signal is coupled to the inverting terminal of comparator 148. Subject to the replacement of the recovery resistor by the network 164, the circuit functions substantially in the manner disclosed in the aforementioned U.S. patent application Ser. No. 452,320, to provide closed loop control of the current flowing in the selected motor winding. In the preferred embodiment, variable resistor 178 is adjusted so that the average current flowing in the selected winding when the STEP signal is in the high state is approximately 1.4 amps, while the average current when the STEP signal is in the low state is approximately 0.6 amps.

Turning next to network 164, the FAST input signal from control register 24 is connected to the base of transistor 192 and through resistor 194 to the +5 volt supply. The emitter of transistor 192 is referenced through resistor 196 to ground while its collector is connected to the base of transistor 198 and through resistor 200 to the +5 volt supply. The emitter of transistor 198 is also connected to the +5 volt supply while the collector of that transistor is connected through resistor 202 to a -12 volt supply. Diode 204 couples the collector of transistor 198 to the base of transistor 206. The anode of diode 204 is also connected through zener diode 208 and diode 210 to the anode of the catch diode (i.e., diode 162). The anode of diode 204 is also coupled through resistor 212 to ground. The emitter of transistor 206 is coupled to the base of transistor 214 and through resistor 216 to ground. Transistor 214 has its emitter connected to ground, while its collector, in common with the collector of transistor 206, is connected to the anodes of the catch diodes.

Considering now the operation of the network, when the FAST input signal is in the low logic state, transistors 192 and 198 are turned off. This permits the -12 volt supply operating through resistor 202 and diode 204 to turn on transistors 206 and 214 hard. When a stepper motor winding such as winding 156 is conducting current and the current drive is suddenly interrupted as by turning off transistor 152, the inductance of winding 156 tends to maintain the flow of current. The path for this current flow from winding 156 is through resistor 158 to ground and back through transistor 214 and catch diode 162 to the winding. With the FAST input signal in the low logic state, transitor 214 which is turned on hard places very little load across the winding and the inductively maintained current decays at a relatively slow rate as desired during normal switching regulator action.

When the FAST input signal is in a high logic state, transistors 192 and 198 are turned on so as to prevent the -12 volt supply from turning on transitors 206 and 214. When the current drive to a winding such as winding 156 is interrupted, however, the rapidly decaying current causes a large reverse voltage to appear across the winding. Since very little of this voltage is dropped across resistor 158 which in the preferred embodiment has a resistance of one/half ohm, almost this total inductive voltage appears across the series combination of the emitter-to-base junctions of transistors 214 and 206, and diodes 208, 210 and 162. This inductive voltage rapidly reaches a level greater than the 20 volt breakdown voltage of zener diode 208. At this point, transistors 206 and 214 turn on and the voltage appearing across winding 156 (neglecting the very small voltage drop across resistor 158) is maintained at a level equal to the sum of the emitter-to-base voltage drops of transistors 206 and 214, the breakdown voltage of zener diode 208, and the forward diode drop of diodes 210 and 162. This voltage drop which will be labeled V.sub.r has a value of approximately 23 volts. Thus, with the FAST input signal in a high logic state, the path for the decaying inductive current may be thought of simply as a resistive load appearing across the motor winding. The effective value of this resistive load at the beginning of the decay period is simply V.sub.r divided by the initial current flowing in the motor winding. In the preferred embodiment where V.sub.r has a value of 23 volts, and the initial current flowing in the motor winding is 1.4 amperes (assuming a high level STEP signal) this effective resistance initially has a value of approximately 16 ohms. As the current decay proceeds, however, the voltage across winding 156 is maintained constant at V.sub.r volts while the current decays. It will be seen, therefore, that the effective value of the resistive load appearing across the motor winding increases as the current decays so as to maintain the current decay at a constant rate.

This may be seen more readily by considering that the voltage appearing across the motor winding is L di/dt. Since the inductance remains relatively constant, and since network 164 maintains a constant voltage across the winding, it follows that di/dt is a constant. In prior art systems which use a recovery resistor in series with the catch diodes, the current decay was exponential with an L/R time constant. In the present system, the current decays linearly and rapidly to 0. This has several important advantages.

First, as the stepper motor is stepped from one phase to the next phase, the FAST signal is simultaneously switched to a high logic state. This has the result of rapidly killing the current in the lagging motor phase so as to facilitate acceleration of the motor toward the next detent position. Another advantage of network 164 may be appreciated by considering that in prior art systems the recovery resistor is in the decaying current path at all times. This resistor must have a relatively high value so as to result in a rapid L/R current decay when the motor current is switched from a lagging to a leading phase. This large resistance, however, is also in the decay path when the motor is in a detent position and the switching regulator action of the controller causes the current drive to be alternately connected to and disconnected from the detent motor winding. During each disconnect portion of the cycle the motor current flows through the large value of resistance resulting in substantial power loss. With the network 164, however, during detent modes, the FAST input signal can be switched low with the result that the effective resistance appearing in the decaying current path is very low. Accordingly, there is almost no power lost in the decaying current path when the motor is in detent.

The determination of the position of the printhead at all times is accomplished with the aid of an optical sensing system associated with the stepper motor. A slotted disc 220 as illustrated in FIG. 5a is rigidly affixed to the shaft of the stepper motor so as to rotate with the stepper motor. A light source and sensor are located on opposite sides of slotted disc 220. The light source and sensor are oriented relative to slotted disc 220 such that the disc blocks the light path at all times except when one of the slots is in registry with the light path. The stepper motor used in the preferred embodiment of the invention has adjacent detent positions separated by 15.degree. of arc. Slotted disc 220 has a slot corresponding to each detent position. The disc is mounted on the shaft of the stepper motor such that, when the motor is in a detent position, the light path will strike the disc at a point midway between two adjacent slots. As the stepper motor is stepped from one detent position to the next, the electrical output of the light sensor changes states during that portion of the step when one of the slots traverses the light path. The angular position of the stepper motor as it steps from one detent position to the next and the corresponding electrical output signal from the light sensor are illustrated in FIG. 5b. Each of the slots in slotted disc 220 is 5.degree. wide and as pointed out above is located midway between two adjacent detent positions of the stepper motor. Accordingly, when the stepper motor has moved 1/3 of the way from one detent position to the next, the light beam enters the slotted area of the wheel and a quantum increase in the sensor output signal is noted. This continues until the stepper motor has reached two thirds of the travel to the next detent position, at which time slotted wheel 220 again blocks the light beam and the sensor output signal returns to its low logic level. This sensor output signal is coupled to line 36 of FIGS. 1 and 2. While the preferred embodiment employs 5.degree. slots located midway between adjacent detent positions, variations in the slot width and location may be made without departing from the spirit and scope of the invention.

As previously noted, microprocessor 40 operates under the control of ROMs 42 and 44. Table II gives the contents of ROM 42, while Table III gives the contents of ROM 44. The left hand column of each table gives the address of the first of 16 bytes in each row. These addresses, as well as the data at each byte location, are given in hexadecimal format. Each byte represents 8 bits of binary information.

The operation of the printhead control may be divided into a print/step sequence and a carriage return sequence. Considering the print/step operation, the controller first acquires the dot pattern for the particular character to be printed from ROM storage. This dot pattern is then strobed into the printhead and the print operation performed. At the completion of the print operation, the controller steps the printhead carriage to the next printer position in preparation for printing the next character.

At each print/step operation, however, prior to loading the dot pattern into the printhead, the controller enters a wait state for a period of 11.3 milliseconds. This is to insure that, at the end of a carriage return, all carriage motion has ceased prior to the printing of the first character in a line. At the end of the 11.3 millisecond wait state, the controller couples the power supply voltage to the printhead, accesses the dot pattern for the character and loads the first column of the dot pattern into the printhead. This loading is accomplished by generating an address such as that illustrated in Table IV. One bit of bits 7-11 will be high indicating which of the five columns of the printhead is being strobed. In the case illustrated, the first column is strobed. One bits in positions 0-6 indicate which of the mesas in the first column are to be strobed. Bit positions 0-11 are coupled to the X and Y printhead drivers 16 and 18 of FIG. 1. Bits 12, 13, and 14 are monitored by the address decode circuit and as previously indicated in the discussion of FIG. 3, the particular bit pattern shown results in a one microsecond high level signal appearing on line 128. This high level signal gates the printhead driver input signal to the appropriate X and Y inputs of the printhead itself. As a result, in the example of Table IV, dot positions 1, 4 and 7 of Column 1 of the printhead are turned on. As long as the power supply voltage remains applied to the printhead, these dot positions are latched on even though the X and Y input signals are subsequently removed. A new address is then loaded onto the address bus with the same bit patten in columns 12-15. In this case, however, only bit position 10 of positions 7-11 will be high and the pattern in positions 0-6 indicates which dots of column 2 of the printhead are to be turned on.

this procedure continues until all five columns of the printhead have been loaded, this procedure taking approximately 200 microseconds for its completion. The strobed printhead requires only 12 address lines to the printhead in contrast with 35 lines required when a 5.times.7 matrix is directly addressed. This is highly advantageous since the 12 line cable to the printhead is more reliable than a 35 line cable.

The print operation then continues for a total period of 10 milliseconds at the end of which the power supply voltage is removed from the printhead. At this point, the printhead carriage is stepped to the next printing location. The logic signal diagram of FIG. 6 may be useful in understanding the print/step cycle. The logic signals shown are those appearing at the output of control register 24. For the first 11.3 milliseconds of the cycle, that is form t.sub.1 to t.sub.2, the controller is in a wait state. For the next 10 milliseconds, that is from t.sub.2 to t.sub.3, the controller is in the PRINT state as described above. At t.sub.3, the PRINT signal is turned off, the enable signal to PHASE A is turned off, the enable signal to PHASE B is turned on, and both the FAST and the STEP logic signals are switched high. The high level FAST signal, which lasts for a one millisecond duration, has the effect of rapidly squelching the decaying current in the PHASE a motor winding so as to permit the stepper motor to move away from the PHASE A detent position. The high level STEP signal results in a rapid current buildup in the PHASE B motor winding to cause acceleration of the stepper motor toward the PHASE A detent position. This continues until time t.sub.4, at which time the change of the SENSOR signal indicates that the stepper motor has traversed one third of the distance between the detent positions for PHASE A and PHASE B. After a 200 microsecond delay, the enable signal to PHASE B is switched OFF and the enable signal to PHASE A is switched on so as to cause a decelerating current to flow in lagging PHASE A of the motor. At the same time the STEP signal goes low to cause a gradual build up of the braking current in PHASE A and the FAST signal goes high to rapidly squelch the decaying current in PHASE B. After one additional millisecond, the FAST signal is switched low and the STEP signal is switched high to permit the braking current in PHASE A to build up to a high level. One millisecond later, that is, at t.sub.6, PHASE A is switch off and the enable signal to PHASE B is switched on to generate a current in PHASE B for pulling the motor into the detent position. The STEP signal remains high for four additional milliseconds, that is, until t.sub.7, to insure that the stepper motor pulls into the detent position for PHASE B. At time t.sub.7, the STEP signal goes low to reduce the current flowing in the PHASE B motor coil to a holding value.

Each print/step operation is deemed to occupy a period of 28.5 milliseconds. In FIG. 6, this cycle begins at time t.sub.1 and concludes at time t.sub.8, at which time the 11.3 millisecond waiting period for the next print/step cycle begins. In a sense there is overlapped operation since the motor may still be pulling into the new detent position for the step cycle illustrated, even though the wait period for the next print/step cycle has already begun. This overlapped operation is made possible by the plurality of interval timers available in I/O chip 48. One of these interval timers is used to time the ten millisecond print period and the various periods associated with the turning on and off of the FAST, STEP, PHASE A, and PHASE B waveforms. A second of these interval timers is used to time the 11.3 millisecond wait period between t.sub.1 and t.sub.2, and to time the 7.2 millisecond period between time t.sub.3 and time t.sub.8. If, during this last mentioned 7.2 millisecond time period the SENSOR signal has gone high as illustrated in FIG. 6, then at the end of the 7.2 millisecond period, that is at time t.sub.8, the print/step cycle is declared to be over and the next cycle can begin. If, however, during the 7.2 millisecond time period no SENSOR signal has occurred, the controller declares a paper out condition. In this case rather than a normal termination of the print/step cycle as illustrated in FIG. 6, the controller goes into a fail-safe return mode which will be described below.

Under normal conditions, the stepper motor will rotate sufficiently far to cause a SENSOR signal well before the expiration of the 7.2 millisecond time period. If the printer has run out of paper, however, the abnormally high friction between the printhead and the paper roller prevents the stepper motor from traversing 1/3 of the distance between adjacent detent positions within 7.2 milliseconds. Accordingly, the expiration of the 7.2 millisecond period prior to the occurrence of a SENSOR signal is a valid indication of a paper out condition. It will be seen, therefore, that the single optical sensor, in addition to providing closed loop control of the stepping action from one detent position to the next, is also used as a paper out detector.

The backspace operation is identical to the forward space sequence described above with the exception of the fact that the 10 millisecond print period is eliminated. Thus, the total period for each backspace step is 18.5 milliseconds.

In describing the carriage return operation, it will first be assumed that the printhead carriage is located outside column 20 at the onset of the carriage return. Undersanding of the carriage return operation may be facilitated by a consideration of the flow diagram of FIG. 7. At the beginning of the carriage return, the flow is at state 300. At all times during the carriage return operation the STEP signal is high so as to induce rapid build up of current in each new leading phase as the stepper motor slews in the carriage return direction. In the preferred embodiment, it is desired that the motor slew at constant velocity with the travel time between adjacent detent positions having an average value of 1.5 milliseconds. Accordingly, at the beginning of the carriage return in state 300, one of the interval timers of I/O chip 48 is set to 1.5 milliseconds. At this same time, current is disabled in the detent motor phase occupied by the stepper motor at the time carriage return begins and the next motor phase in the carriage return direction is enabled. During the first several phase changes, the stepper motor is accelerating and the 1.5 millisecond timer expires before a SENSOR signal occurs, indicating that the motor has traversed 1/3 of the angular distance to the next detent position. Expiration of the timer causes the flow to follow path 301 to a wait state 302. The controller remains in wait state 302 until the SENSOR signal does occur at which time flow follows path 303 back to state 300. At this point in time, the timer is reset to a new 1.5 millisecond period, and the motor phases are again switched to enable the next new motor phase in the carriage return direction. Flow continues in this fashion around the loop 300, 301, 302 and 303 until the motor reaches or slightly exceeds the desired constant velocity. If the motor velocity should go slightly high, while the flow is in state 300, then a SENSOR signal will occur prior to the expiration of the 1.5 millisecond timer. Under these circumstances, flow will pass from stage 300 along path 304 to wait 305. Here the flow awaits the expiration of the 1.5 millisecond timer, at which point flow returns along path 306 to state 300. Thus, when the motor is slewing at a velocity lower than that corresponding to a travel time of 1.5 milliseconds between detent position, the change of motor phases awaits the occurrence of the SENSOR so as to prevent the electronics from getting ahead of the actual motor position. When the motor velocity, however, is higher than that corresponding to the 1.5 millisecond travel time, the motor phase changes await the occurrence of the timer so as to prevent the motor position from getting ahead of the electronics. In this way the stepper motor is controlled to slew at the desired constant velocity. At the beginning of each of the first five cycles of the above described sequence, the FAST pulse is switched high for a 1 millisecond period so as to rapidly squelch the decaying current in the lagging motor phase and assist in accelerating the stepper motor to the desired slew velocity.

If at any time during the above described sequence a total period of 8.0 milliseconds expires after the timer is set at stage 300, and before a SENSOR signal is received, then flow travels along path 301 to state 302 and along path 307 to a fail-safe return state 308. As before, this is deemed to be indicative of a paper out condition.

In the normal course of events, however, flow continues centered around state 300 until the printhead carriage reaches column 12. At this point, a controlled deceleration is initiated to bring the printhead to a stop as it reaches column 1. At the beginning of the move to column 10, instead of setting the timer to 1.5 milliseconds, a longer time is used. For each column throughout the deceleration period, a successfully longer time is used when setting the timer. This causes the motor phases to change on the timer, causing deceleration. The specific times used in the preferred embodiment of the invention are given in Table V. The values in the deceleration table are selected to decelerate the motor along the profile that resembles the natural deceleration of the system.

During the deceleration phase, particularly in low friction systems, it may sometimes happen that the printhead carriage does not decelerate as rapidly as desired and, as a result, two consecutive SENSOR signals may be received before the timer expires. By way of example, assume that the motor is passing through the phase C detent position and that at step 300 the timer is set and PHASE B is enabled. The first SENSOR signal indicating that the motor has rotated a portion of the way between PHASE C and PHASE B causes flow to move along path 304 to wait state 305. Before expiration of the timer, another SENSOR signal is received indicating that the motor has rotated to a point midway between PHASE B and PHASE A. This SENSOR signal causes flow to move along path 309 to wait state 310. Now, when the timer expires the flow moves along path 311 to state 312. At this point, the timer is reset and the motor phases are changed so as to energize PHASE A and de-energize PHASE B. It will be recalled, however, that the motor is already midway between PHASE B and PHASE A. The next SENSOR signal causing flow along path 313 indicates that the motor has progressed to a point part way between PHASE A and PHASE C. At this point, the motor current flowing in phase A causes a braking torque.

Thus, as long as the flow stays in the loop 310, 311, 312, and 313, thre will be a braking torque generated during a portion of each step. Ultimately, this braking torque will slow the motor down sufficiently so that two timer expirations will occur without the intervention of a SENSOR signal. When this occurs, flow will move from state 310 through path 311 to state 312 and through path 313 back to state 300. When this occurs, the motor phase excitation will be back in synchronization with the actual location of the stepper motor and normal deceleration continues.

In the above mentioned mode of operation, the timer was set to a 1.5 millisecond period for each step during the acceleration phase of the carriage return. When, however, the printhead carriage is inside column 21 when the carriage return begins, a different rate of acceleration is used. A slower acceleration allows the processor to intercept the deceleration profile and bring the head to a smooth stop at column 1. The times used in the preferred embodiment are shown in Table VI. The time is read from the acceleration table once at the beginning of the carriage return and that time is used for each step until a column is reached inside column 12 whose deceleration time is longer. This represents the point where the deceleration profile is intercepted and deceleration begins.

When power is first applied to the system, it is necessary for the controller to determine the precise location of the carriage. When the carriage is in column 1, the stepper motor is detented at the PHASE A detent position. It is possible for the carriage to move one more position to the left, in which case the stepper motor will be in the PHASE C detent position. This location will be referred to as column 0.

Further movement to the left from column 0 is inhibited by a mechanical limit. When power is first applied to the system, the carriage may be anywhere within its permissible range of travel. Initially, the phases are energized in the sequence C, B, A, C, with this sequence of four phase energizations occurring independent of whether or not any SENSOR pulses are received. If the carriage is initially at a point remote from the left hand mechanical limit, this results in the stepper motor moving first to the PHASE C detent position, then to PHASE B, then PHASE A, and finally PHASE C. If, on the other hand, the carriage was initially located in column 0, then the first phase change from PHASE C to to PHASE B will result in no movement since the attempted movement is inhibited by the left hand mechanical limit. When PHASE A is energized, however, the carriage will move to column 1 with the motor occupying the PHASE A detent position. When PHASE C is energized, the motor moves to the left to column 0. Similarly, if the carriage is in any of columns 1, 2 or 3 when power is applied, the initial sequence will conclude with the carriage being in column 0 position.

After the initial forced energization of four phases, the controller is repeatedly operated in the back space mode as described above. This continues until a back space is attempted and no SENSOR signal is received. Such lack of SENSOR signal will occur when the carriage has reached column 0 and the attempt to move the stepper motor to PHASE B is inhibited by the left hand limit. The controller recognizes this left hand limit by the absence of the SENSOR signal. At this point, the controller moves the carriage one space to the right to column 1.

After reaching column 1, a brief sequence is performed for the purpose of recognizing a paper out condition. Two more steps to the right are performed, that is to PHASE B and PHASE C. This is followed by two steps to the left, that is to PHASE B and to PHASE A so as to return the carriage to column 1. If, during any of the last mentioned four steps, a period of greater than 7.2 milliseconds expires before a sensor signal is detected, the controller interprets this as a paper out condition. If the paper out condition does not occur, the carriage is in column 1 and ready to begin print operations.

During step operations after power-up, a sensor failure will activate the paper out condition. The friction between the printhead and the roller is too great without paper to perform a normal step. When paper out is activated, the controller will only process carriage return, line feed, and bell characters. The keyboard scanner checks for a paper out condition when the paper advance key is detected. Instead of generating a series of carriage return characters, the keyboard scanner will generate a series of linefeed characters during a paper out condition when the paper advance key is depressed. This will cause the carriage return at the beginning to be bypassed. Entering a carriage return during a paper out condition will force a fail safe return to the left.

When the terminal runs out of paper, the printhead will stop wherever it first encounters the roller. The operator will then load paper using the line feed and paper advance keys. Entering a carriage return after paper is loaded will cause the printhead to seek the left-hand margin.

Whereas there has been disclosed the preferred embodiment of the invention, there may be suggested to those skilled in the art certain minor modifications which do not depart from the spirit and scope of the invention as set forth in the appended claims.