Semiconductor Device

(a) Field of the Invention

This invention relates to a semiconductor device, and more particularly to a semiconductor device having variable feed-back effect.

(B) Description of the Prior Art

In conventional semiconductor circuits, when the degree of feed-back is desired to be varied for performing mixing, modulation or logic operation, the negative feed-back voltage itself is varied to alter the characteristic of the circuit. Namely, the signal voltages are superposed outside the semiconductor device. According to such a method, however, the power required for the control becomes large and the effect of the characteristic change upon operation is transmitted reversely to the output circuit through the circuit for applying the negative feed-back voltage, to give undesired reaction to the circuit.

Therefore, this invention is intended to solve the conventional drawbacks as described above and an object of this invention is to provide a semiconductor device capable of effectively varying the characteristic with small power consumption.

Another object of this invention is to provide a semiconductor device having a pair of current electrodes and at least two control electrodes, one being utilized as the conventional control electrode and the other being utilized for varying the negative feed-back resistance of the device.

A further object of this invention is to provide a semiconductor device having a variable G.sub.m .multidot.r.sub.s product.

Other objects, features and advantages of this invention will become apparent from the following description of the preferred embodiments when taken in conjunction with the accompanying drawings.

FIGS. 1A and 1B are a schematic cross-section and a schematic top plan view of a semiconductor device according to an embodiment of this invention.

FIGS. 2A and 2B are a schematic cross-section and a schematic top plan view of a semiconductor device according to another embodiment of this invention.

FIGS. 3A to 3C are characteristic curves showing an example of the variable characteristic curves of a semi-conductor device according to this invention.

FIG. 4 is a top plan view of a semiconductor device having a modified structure on the basis of the structure of FIGS. 1A and 1B, in which the fourth electrode in FIGS. 1A and 1B is divided into a plurality of electrodes.

FIG. 5 is a cross-section of a vertical type semi-conductor device according to another embodiment of this invention.

FIG. 6 is a cross-section of a semiconductor device according to another embodiment of this invention.

FIGS. 7A to 7J are cross-sections showing various steps of manufacture of the semiconductor device of FIGS. 1A and 1B.

FIGS. 8A and 8B are cross-sections showing examples of the electrode structure to be used in the semiconductor device according to this invention.

FIGS. 9A to 9I are cross-sections showing various steps of the manufacture of the device of FIG. 5, and FIG. 9J to FIG. 9L are cross-sections showing modifications of the structure of FIG. 9I.

FIGS. 10A to 10C are cross-sections showing the MOS-type structure embodiments.

FIGS. 11A and 11B are characteristic curves showing an example of the performance of a semiconductor device according to this invention.

FIGS. 12A and 12B are characteristic curves showing another example of the performance of a semiconductor device according to this invention.

FIGS. 13A and 13B are characteristic curves showing another example of the performance of a semiconductor device according to this invention.

FIGS. 14A and 14B are characteristic curves showing another example of the performance of a semiconductor device according to this invention.

FIG. 15 is a cross-section showing another embodiment of the semiconductor device according to this invention.

FIGS. 1A and 1B show a semiconductor device according to an embodiment of this invention. In FIG. 1A, a simplified external circuit is also shown.

Two main electrodes 1 and 2 are formed on one principal surface of a semiconductor wafer 11. Between these two electrodes a third (control) electrode 3 is formed to change the characteristic of the voltage V.sub.D vs. the current I.sub.D flowing between the main electrodes 1 and 2. These electrodes 1, 2 and 3 constitute a similar structure to that of the conventional field effect transistor, but the impurity concentration in the semiconductor bulk 11 is selected to be low enough to enable the semiconductor device to have triode-like characteristics, i.e. operable as a static induction transistor proposed by the present inventor (J. Nishizawa, IEEE Trans. Electron Devices ED-22, No. 4, pp. 185-197, April 1975). In addition to the above structure, at least one electrode (two are shown in the figure) 4 (5, . . .) is formed between one main electrode 1 and the third electrode 3 so as to change the resistance r.sub.s of the semiconductor region through which the current flows. Namely, the negative feed-back resistance r.sub.s can be changed by the voltage V.sub.Gl applied to the electrode 4. When a plurality of such auxiliary control electrodes 4, 5, . . . are provided, an appropriate set of control voltages may be applied thereto. The control electrodes 3, 4, 5 . . . are formed of any of junction, MOS or Schottky structures.

In other words, the static induction transistor has similar operational principle to that of triode vacuum tube. The negative voltages applied to the auxiliary control electrodes serve to vary the cross-section of the current path and thereby the value of the negative feed-back resistance r.sub.s.

According to a simplified analysis, when a current I.sub.D flows between the two electrodes 1 and 2 through the semiconductor region 11 and a voltage V.sub.G is applied to the control electrode 3, the resistance r.sub.s between the electrodes 1 and 3 generates a voltage drop r.sub.s .multidot.I.sub.D therebetween and raises the potential at the electrode 3 and hence the control voltage V.sub.G applied to the electrode 3 has a similar effect to a control voltage of V.sub.G - r.sub.s .multidot.I.sub.D. Since the control voltage V.sub.G is usually of negative polarity, the effective control voltage is -(.vertline.V.sub.G .vertline. + r.sub.s .multidot.I.sub.D). According to this embodiment, another electrode 4 is additionally provided for changing the resistance r.sub.s and hence the magnitude of the negative feed-back can be very easily changed. The transconductance G.sub.m ' when the current I.sub.D is directly varied by the third electrode 3 can be represented by

where G.sub.m is the true transconductance when there is no negative feed-back resistance r.sub.s. Since .DELTA.V.sub.G .multidot.G.sub.m ' = .DELTA.I.sub.D, the ratio of change in the current I.sub.D with respect to the change in the voltage V.sub.Gl applied to the fourth electrode 4 is represented by ##EQU1## Thus, the ratio .gamma. of the control effect on the current I.sub.D by the voltage on the fourth electrode 4 to that by the voltage on the third electrode 3 becomes ##EQU2## When this ratio .gamma. is greater than unity, the control effect by the fourth electrode 4 is greater than that by the third electrode 3. Even if the negative feed-back resistance r.sub.s is extremely large and hence the transconductance G.sub.m ' is very small, it is easy to arrange this value greater than 1. For example, this can be achieved by keeping the impurity concentration of the semiconductor region 11 uniform and narrowing the width of the conductive region in the semiconductor region at which the negative feed-back resistance becomes r.sub.s, e.g. by providing a recessed portion in the region on the opposite side to that provided with the electrodes as shown by the dotted line in the figure, to increase the value of (.differential.r.sub.s /.differential.V.sub.Gl).

It will be apparent that the shape of the recessed portion is not limited to that shown in the figure. Evidently, it is possible to give similar or greater effect by providing the electrodes 3, 4, 5, . . . on the both surfaces of the semi-conductor wafer 11.

Once negative feed-back is effected, the value of r.sub.s increases. When the product of the transconductance G.sub.m and the negative feed-back resistance r.sub.s approaches unity, i.e. G.sub.m .multidot.r.sub.s .perspectiveto. 1, the value of r.sub.s increases further. This is because the voltage drop due to the current I.sub.D, i.e. r.sub.s .multidot.I.sub.D, serves additively to the control voltage V.sub.Gl applied to the fourth electrode 4 (when there are more than one electrodes 4, 5, . . . between the first and the third electrodes 1 and 3, the voltage drop serves additively to the respective control voltages V.sub.G1, V.sub.G2, . . . applied to the electrodes 4, 5, . . .). Thus, the control voltages have greater effects than that of their value. Therefore, the most effective use is to change the negative feed-back resistance r.sub.s from the region 1 > G.sub.m .multidot.r.sub.s to the region 1 < G.sub.m .multidot.r.sub.s by the application of the control voltage V.sub.G1. Namely, the value of the negative feedback resistance r.sub.s can be varied widely by the additional control voltages V.sub.G1, V.sub.G2, . . . applied to the additional control electrodes 4, 5, . . . and when the product of the transconductance G.sub.m and the negative feed-back resistance r.sub.s becomes greater than unity, G.sub.m .multidot.r.sub.s > 1, the negative feed-back resistance r.sub.s increases further more by the negative feed-back as described above.

FIGS. 2A and 2B show another embodiment of a semiconductor device, in which the first main electrode and the third electrode are short-circuited and the width of the conductive region in the semiconductor bulk 11 is made narrow in the region located below the control electrodes. In this embodiment, the third control electrode near the drain electrode 2 is connected to the source electrode 1. The connection of the third electrode 3 and the first electrode 1 is achieved with metal or low resistivity material. In this structure, control voltages are applied to the electrodes 4 and 5 and the negative feed-back resistance r.sub.s and hence the current I.sub.D can be effectively varied thereby.

The change in the characteristic curves by the change in the negative feed-back resistance r.sub.s will be described below. From the relation G.sub.m ' = G.sub.m /(1 + G.sub.m .multidot.r.sub.s), it can be seen that when G.sub.m .multidot.r.sub.s < 1, the relation becomes G.sub.m ' .perspectiveto. G.sub.m and when G.sub.m .multidot.r.sub.s > 1, the relation becomes G.sub.m ' .perspectiveto. 1/r.sub.s. The characteristic curves corresponding to these changes are shown in FIGS. 3A and 3B (G.sub.m .multidot.r.sub.s < 1) and in FIG. 3C (G.sub.m .multidot.r.sub.s > 1). Generally, when the voltage V.sub.G on the third electrode increases (considering the polarity), the main current I.sub.D increases. FIG. 3A shows the case when G.sub.m .multidot.r.sub.s < 1 and the current path (channel) below the third electrode 3 is not occupied by the depletion layer. This can be called the variable resistance characteristic. FIG. 3B shows the characteristic when G.sub.m .multidot.r.sub.s < 1 and the current channel is pinched off by the depletion layer. In this case, the I.sub.D vs. V.sub.D characteristic becomes triode-like characteristic where the current I.sub.D does not saturate with respect to the voltage V.sub.D. FIG. 3C shows the case when G.sub.m .multidot.r.sub.s > 1 and the I.sub.D vs. V.sub.D characteristic becomes pentode-like characteristic where the current I.sub.D becomes saturated with respect to the voltage V.sub.D since the negative feed-back due to the negative feed-back resistance r.sub.s is large.

The variation in the negative feed-back resistance r.sub.s constitutes a resistance-capacitance distribution coefficient circuit with the distributed capacitance of the third electrode 3. High frequency components applied to the third electrode 3, however, becomes used up in the negative feed-back resistance r.sub.s and not effectively applied to the depletion layer under the third electrode. Thus, the high frequency response becomes worse. This phenomenon can be utilized as a voltage-controlled notch filter. In this way, the frequency dependence of the characteristic of a semiconductor device can be varied by the negative feed-back resistance r.sub.s.

FIG. 4 shows an embodiment in which the fourth and the fifth electrodes 4 and 5 in the structure of FIGS. 1A and 1B are divided into a plurality of segments for decreasing the distributed capacitance. Further, the regions 9 between adjacent electrode segments are recessed or bored as shown by the solid line to restrict the current path only under the electrode segments, thereby enhancing the control effect on the negative feed-back resistance r.sub.s. The non-conductive region 9 may be provided by other means such as selective oxidation. The electrode segments are connected by metal lead deposited on the surface, etc. It will be apparent that such division of electrode may be arbitrarily modified in accordance with the purpose. For example, either one or all of the electrodes 3, 4, and 5 may be divided.

FIG. 5 shows an embodiment of the vertical structure. Namely, FIG. 5 is a cross-section. The main electrodes 1 and 2 are formed on the opposite principal surfaces of a semiconductor chip 11, and the control electrodes 3, 4 and 5 are formed on the side surface. The operation of this structure will be apparent from the foregoing description.

FIG. 6 shows another embodiment in which the fourth and fifth electrodes 4 and 5 are disposed between the second main electrode 2 and the third electrode 3 in place of between the first main electrode 1 and the third electrode 3. In this embodiment, when a voltage V.sub.G1 is applied to the fourth electrode 4 to decrease the main current I.sub.D, a voltage drop I.sub.D .multidot.r' occurs in the channel and hence the main current I.sub.D decreases. Thus, the effect of the voltage V.sub.G applied to the third electrode 3 decreases. When a positive voltage is applied to the third electrode, carriers injected from the third electrode decreases and the carrier density in the region between the first and the third electrodes decreases, thereby increasing the resistance in this region. As the result, the current between the first and the second main electrodes also decreases.

It will be apparent that such modifications as the division of the electrodes and the vertical structure as shown in FIGS. 4 and 5 on the basis of the embodiment of FIGS. 1A and 1B are also applicable to this embodiment.

Next, the manufacture of the semiconductor device according to this invention will be described, first taking the junction type as an example.

FIGS. 7A to 7J show how the semiconductor device of FIGS. 1A and 1B is manufactured. First, a p-type silicon substrate 10 of high resistivity is prepared (FIG. 7A). An n-type epitaxial layer 11 is grown on the substrate 10 (FIG. 7B). The epitaxial growth is achieved by flowing a mixed gas of H.sub.2, SiCl.sub.4 and AsCl.sub.3 on the silicon substrate 10 heated to 1000.degree. C. Next, the substrate 10 is subjected to oxidation in a mixed gas of oxygen and steam to grow a silicon oxide film 12 of about 500 nm on the surface of the epitaxial layer 11 (FIG. 7C). Then, windows are bored through the oxide film 12 by the photoetching technique using photoresist KPR, etc., and boron is diffused selectively into the epitaxial layer 11 through these windows 12 in a mixed gas of N.sub.2, O.sub.2 and BBr.sub.3 at 1000.degree. C. to form p-type regions 23, 24 and 25 (FIG. 7D). Here, a new oxide film is grown on the exposed silicon surface. Again, windows are bored in the oxide film 12 in the positions of the main electrodes 1 and 2 by the photoetching technique and arsenic is selectively diffused into the epitaxial layer 11 through these windows at 1100.degree. C. in a mixed gas of N.sub.2, O.sub.2 and AsCl.sub.3 to form heavily doped n-type regions 21 and 22 for forming ohmic contacts (FIG. 7E). Then, the oxide film formed in the diffusion process on the regions 21, 22, 23, 24 and 25 are selectively etched by the photoetching technique to expose the silicon surface. On the oxide and the exposed silicon surface, an aluminium film is vapor-deposited and selectively etched away to leave respective electrodes 1, 2, 3, 4, and 5 by the photoetching technique (FIG. 7F). In the case when a recessed portion corresponding to the portion indicated by the dotted line A in FIG. 1A is to be provided for narrowing the width of the current path of the main current I.sub.D and for raising the control efficiency, selective jet etch using a mixed solution of HF, HNO.sub.3 and CH.sub.3 COOH may be subjected to the rear surface of the crystal (FIG. 7G). Alternatively, boron may be selectively diffused into the substrate 10 before the growth of the n-type epitaxial layer to form a p-type embedded region 13 of low resistivity (FIG. 7H). Then, the n-type epitaxial layer 11 is grown (FIG. 7I). After the epitaxial growth, the substrate is subjected to a heat treatment at 1200.degree. C. in oxygen to form a p-type region 14 by the out-diffusion to substantially decreasing the width of the current path of the n-type region 11 (FIG. 7J). Similar steps to those of FIGS. 7C to 7G follow thereafter.

In manufacturing the semiconductor device as shown in FIGS. 2A and 2B, the first and the third electrodes may be bonded with gold wire, etc. Alternatively, an aluminium film may be selectively deposited (deposited and selectively etched) to leave an aluminium electrode short-circuiting the first and the third electrodes on the oxide film 12. For forming divided electrodes as shown in FIG. 4, boron may be selectively diffused to form divided p-type regions 24 and electrically connected with an aluminium film deposited on the silicon chip and the oxide film as shown in FIG. 8A. Alternatively, the current path may be defined by mesa-etching the silicon chip, the cut-away portions extending to the substrate 10 leaving the boron-diffused regions 24 and the underlying epitaxial layer 11 divided as shown in FIG. 8B. The oxide film 12 and the aluminium electrode 4 may be formed after the mesa-etching.

Next, the manufacture of a vertical type structure as shown in FIG. 5 will be described. FIGS. 9A to 9I show an example of the manufacturing steps. First, an n-type silicon chip 11 is prepared (FIG. 9A) and boron is selectively diffused after oxidation and photoetching process (or selective boron diffusion as the case may require) to form a p.sup.+ type layer 23 (FIG. 9B). Then, an n-type epitaxial layer 11' is grown thereon (FIG. 9C). Another p.sup.+ type layer 24 is formed by the photoetching process (or by the selective boron diffusion as the case may require) (FIG. 9D). Another n-type epitaxial layer 11" is grown thereon (FIG. 9E). Then, arsenic is diffused to the both principal surfaces to form n.sup.+ type layers 21 and 22 (FIG. 9F). The p.sup.+ type layer 24 is exposed by the first selective mesa-etching (FIG. 9G) and the p.sup.+ type layer 23 is exposed by the second mesa-etching (FIG. 9H). Then, aluminium is vapor-deposited and selectively etched to form the first and second main electrodes 1 and 2, the third and the fourth electrodes 3 and 4 (FIG. 9I).

Instead of forming an n.sup.+ type diffused layer 22 in the chip 11, an n.sup.+ type silicon chip may be used and an n-type layer 11 may be epitaxially grown thereon.

FIG. 9J shows an example of another structure in which p.sup.+ type layers or grids 23 and 24 are embedded or buried in an n-type semiconductor region and have at least one end of each connected to electrodes 3 and 4. The manufacturing steps are similar to those of FIGS. 9A to 9I. This structure enhances the control efficiency or allows a layer current flow in total.

FIG. 9K shows an example of another structure in which the p.sup.+ type diffused region 24 and the n.sup.+ type diffused region 21 are formed alternatively in the surface portion by oxidation, photoetching and selective diffusion. The p.sup.+ type diffused region 24 is formed deeper in the epitaxial layer 11' than the n.sup.+ type diffused region 21. Numeral 12 denotes an oxide film.

FIG. 9L shows a case when the first main electrode 1 and the fourth electrode 4 are off-set in the vertical position by mesa-etching. The structures of FIGS. 9K and 9L can reduce the distributed capacitance and hence are advantageous for high frequency use.

FIGS. 10A to 10C show MOS type structures. In FIG. 10A, n.sup.+ type diffused regions 21 and 22 are formed in a p-type high resistivity silicon chip 11. An oxide film 12 and aluminium electrodes 1, 2, 3 and 4 are formed on the silicon chip 11 to form a four-electrode MOS transistor structure. In FIG. 10B, the fourth electrode 4 is formed of a junction-type structure. The n-type epitaxial or diffused layer 11' is formed in the surface portion of the p-type high resistivity layer 11 and an p.sup.+ type heavily diffused region 24 is formed therein. The structures of the third and the fourth electrodes may be exchanged. FIG. 10C shows such an example in which the third electrode is formed of a junction type structure and a numeral 23 denotes a p.sup.+ type diffused layer. The fourth electrode 4 is of MOS type. The semiconductor region 11 is of n-type.

In the foregoing embodiments, n-channel field effect transistors of junction type and MOS type are described. It is apparent that p-channel devices can be similarly formed and Schottky junction may be used for at least one of the third and the fourth (the fifth, . . .) electrodes.

Next, examples of the characteristics of the semiconductor device according to this invention will be described.

In the vertical structure of FIG. 9J, the n-type region 11 had a thickness of 50 .mu.m and an impurity (donor) concentration of N.sub.D = 5 .times. 10.sup.14 cm.sup.-3, the first epitaxial layer 11' had a thickness of 20 .mu.m an impurity (donor) concentration of N.sub.D = 5 .times. 10.sup.14 cm.sup.-3, the second epitaxial layer 11" had a thickness of 20 .mu.m and an impurity (donor) concentration of N.sub.D = 1 .times. 10.sup.16 cm.sup.-3, the buried grid regions 23 and 24 had a cylinder form of a diameter of 15 .mu.m and a mutual distance of 30 .mu.m and an impurity (acceptor) concentration of 10.sup.19 cm.sup.-3. Characteristics as shown in FIG. 11A corresponding to the condition G.sub.m .multidot.r.sub.s < 1 were obtained. It can be seen that the resistance is almost constant for a fixed controlling voltage V.sub.G and varies with the change in the controlling voltage V.sub.G. Namely, the device works as a variable resistance element when no voltage is applied to the fourth electrode. When a negative bias voltage V.sub.G1 = -2 V is applied to the fourth electrode 4, the product is still less than unity G.sub.m .multidot.r.sub.s < 1 and the characteristics change into those shown in FIG. 11B, where the absolute resistance of the variable resistance has increased much. More precisely, the application of -2 V to the fourth electrode 4 increased the resistance to about ten times as large.

In the similar structure and dimensions with the example 1 but with the impurity concentration in the region 11 reduced to N.sub.D = 1 .times. 10.sup.13 cm.sup.-3, and the impurity concentration of the first epitaxial layer 11' raised to N.sub.D = 1 .times. 10.sup.16 cm.sup.-3, the characteristics shown in FIG. 12A were obtained. When a negative bias voltage V.sub.G1 = -1 V was applied to the fourth electrode, the characteristics change into those shown in FIG. 12B. These states also correspond to G.sub.m .multidot.r.sub.s < 1.

In the similar structure and dimensions as examples 1 and 2, the impurity concentration of the region 11 was selected at N.sub.D = 1 .times. 10.sup.13 cm.sup.-3, the impurity concentration of the first epitaxial layer 11' at N.sub.D = 1 .times. 10.sup.14 cm.sup.-3, the p.sup.+ type buried region 23 for the fourth electrode 4 was arranged to have a diameter of 30 .mu.m and a mutual distance of 50 .mu.m. When the fourth electrode 4 is short-circuited to the first electrode 1, i.e. V.sub.G1 = 0 V, triode-like characteristics as shown in FIG. 13A were obtained. When a negative bias voltage V.sub.G1 = -2 V was applied to the fourth electrode 4, the characteristics change into pentode-like ones as shown in FIG. 13B. The characteristics of FIG. 13A correspond to G.sub.m .multidot.r.sub.s < 1 and those of FIG. 13B correspond to G.sub.m .multidot.r.sub.s > 1. Namely, when a negative bias voltage V.sub.G1 is applied to the fourth electrode 4, the negative feed-back resistance r.sub.s increases to increase the negative feed-back effect. Then the value of r.sub.s increases further. Thus, the transition between the states of G.sub.m .multidot.r.sub.s < 1 and G.sub.m .multidot.r.sub.s > 1 can be easily obtained.

In the lateral structure as shown in FIG. 7 but without the fifth electrode 5, the n-type epitaxial layer 11 was arranged to have a thickness of 30 .mu.m and an impurity concentration of N.sub.D = 1 .times. 10.sup.13 cm.sup.-3, the third and the fourth electrodes had respective longitudinal lengths of 10 .mu.m and 3 .mu.m along the current flow, the p.sup.+ type diffused regions 23 and 24 had respective diffusion depths of 10 .mu.m and 3 .mu.m, the distance from the right edge of the n.sup.+ type diffused region 21 under the first main electrode 1 to the left edge of the p.sup.+ type diffused region 24 under the fourth electrode 4 was 5 .mu.m, the distance from the p.sup.+ type diffused region 24 to the left edge of the p+ type region 23 was 30 .mu.m and the distance from the right edge of the p.sup.+ type diffused region 23 to the left edge of the n.sup.+ type diffused region 22 was 50 .mu.m. When the fourth electrode 4 is connected to the first electrode 1, V.sub.G1 = 0 V, the condition G.sub.m .multidot.r.sub.s < 1 was satisfied and the triode-like characteristics as shown in FIG. 13A were obtained. When a negative voltage V.sub.G1 = -1 V was applied to the fourth electrode 4, the condition G.sub.m .multidot.r.sub.s > 1 was satisfied and pentode-like characteristics as shown in FIG. 13B were obtained. Namely, the main current I.sub.D decreased considerably by the application of the negative bias voltage for the same second electrode voltage V.sub.D.

In the MOS structure shown in FIG. 10A, the impurity concentration of the p-type silicon chip 11 was selected at N.sub.D = 1 .times. 10.sup.14 cm.sup.-3, the so-called channel length between the first and the second main electrodes 1 and 2 was set at 7 .mu.m, the thickness of the oxide layer 12 was 100 nm, and the distance between the third and the fourth electrodes 3 and 4 was 2 .mu.m. When a positive voltage V.sub.G1 = +2 V was applied, the current vs. voltage characteristics were as shown in FIG. 14A. When the positive bias voltage was changed to V.sub.G1 = +1 V, the current vs. voltage characteristics changed as shown in FIG. 14B. Both the characteristics of FIGS. 14A and 14B were pendode-like saturated characteristics satisfying the condition G.sub.m .multidot.r.sub.s > 1, but the current in FIG. 14B was much reduced. Namely, in the latter case, the negative feed-back resistance r.sub.s was increased by decreasing the fourth electrode voltage V.sub.G1 to increase the negative feed-back effect and hence to decrease the current I.sub.D.

As has been described above, various combinations and modifications are possible, but the gist lies in controlling the voltage V.sub.G1, V.sub.G2, . . . applied to the fourth, the fifth, . . . electrodes 4, 5, . . . to vary the magnitude of the negative feed-back and hence to effectively vary the effective voltage applied to the third electrode. Since the effective transconductance G.sub.m ' can be represented by G.sub.m ' = G.sub.m /(1 + G.sub.m .multidot.r.sub.s), the characteristics can be changed widely through variations in G.sub.m and r.sub.s. These values depend strongly on the structure, dimensions, impurity concentrations, etc. of the device and also on the controlling voltages V.sub.G1, V.sub.G2, . . .. Therefore, the number of combinations is almost innumerable.

In the foregoing embodiments, the negative feed-back resistance r.sub.s was mainly varied by the electric field, but any method can be adopted to vary the negative feed-back resistance r.sub.s externally.

For example, light may be irradiated on the surface between the first and the third electrodes as shown in FIG. 15 to utilize the photoconductivity. Namely, when light is irradiated, charge carriers are excited to reduce the negative feed-back resistance r.sub.s. Various changes in the characteristic can be provided similarly by this method. For example, when a deep-level impurity such as Fe, Cu or Au is doped in the semiconductor portion to be irradiated by light, the resistance is large and G.sub.m .multidot.r.sub.s > 1 when no light is irradiated while the resistance decreases and G.sub.m .multidot.r.sub.s < 1 when light is irradiated.

In another example, carriers may be injected from at least one of the additional fourth, fifth, . . . electrodes 4, 5, . . . to change the negative feed-back resistance r.sub.s. For example, in the structure of FIG. 7F, a forward bias may be applied to the diffused region 24 through the fourth electrode 4 to inject carriers or the conductivity type of the region 24 may be changed to n.sup.+ type to inject majority carriers into the channel portion. When carriers are injected in this manner, the resistance decreased. Hence, the condition G.sub.m .multidot.r.sub.s > 1 can be satisfied when no carriers are injected from the fourth electrode while the condition G.sub.m .multidot.r.sub.s < 1 be satisfied when carriers are injected.

As has been described above, the negative feed-back resistance can be changed effectively in various ways to change the current vs. voltage characteristics. Such a variable characteristic device can be used as a logic element, and an amplifying oscillation element, and further as a filter, etc. since the frequency dependence can be varied by the control of the negative feed-back resistance r.sub.s.