Variable Speed Facsimile Transmitter Using Storage Mode Photodetection Array

The present invention relates to facsimile communication and more specifically to a variable speed facsimile transmitter which employs a storage mode photodetection array as a means of deriving a video line signal and method of operating the facsimile transmitter employing such photodetection arrays.

The present invention incorporates self-scanning photodetection arrays as a means of sensing visual information recorded on a printed document to be transmitted over long distances. The photodetection arrays utilize solid state photosensitive devices which operate in a storage mode. These devices, when operated in the storage mode with a junction reverse biased, have the characteristics of a capacitor. When the junction is open circuited the junction slowly discharges as electrons and holes are generated thermally and neutralize the stored charge on each side of the junction. With the application of light to the junction the discharge of the junction occurs much more rapidly and hence the junction may be used to sense light. Typically, the junction is recharged periodically and the recharging current is sensed; this current is a function of the total incident light on the junction, i.e. the time integral of the incident light. In many pattern recognition applications which utilize an array of photodiodes in a storage mode of operation, an elongated row of the photosensitive device is scanned electrically. Typically, the electrical circuit utilized to scan the photosensitive devices is incorporated on the same semiconductor substrate or chip as the photosensitive devices. The photodetection array incorporated in the present invention is commercially available from Reticon Corporation, U.S.A.

Because of the storage mode of operation with the magnitude of the available output varying as a function of the time integral of the quantity of incident light, and because of the possible difference between the scanning speed of the photosensitive device and the speed at which an electronic circuit processes the video signal into a format suitable for transmission, it is necessary to drive the photosensitive device such that a same line path of a printed document is scanned repeatedly until the processor is ready to process the output of the photosensitive device. Otherwise, the photosensitive device would reach the saturation level upon prolonged exposure to the sensed line. This requires that the photosensitive device be repeatedly discharged at intervals.

In practice, facsimile communication sytems are designed to operate on a number of transmission speeds to meet the user's requirements. Where the aforesaid photodetection array is employed as a means of scanning documents, the amplitude of the scanner output will vary depending on the transmission speed.

To keep the video output constant over the differing transmission speeds, the prior art system, disclosed in Japanese Patent Application No. 51-105221, laid open to public inspection on Sept. 17, 1976, discharges the photodetection array at a constant frequency which is a common multiple of the different scanning frequencies of the system. For example, assume the system have 3 Hz and 5 Hz scanning frequencies, the photodetector is discharged always at 15 Hz, regardless of the selected scanning frequency.

However, since the amplitude of the photodetector output decreases inversely with the discharge frequency, the video output of the prior art system is of small amplitude, which would require amplification of the signal or high performance optical system to reduce the loss of incident light.

In a facsimile transmitter which employs a storage mode photodetection array and drives it at one of a plurality of manually selectable clock rates, the present invention contemplates to discharge the photodetection array at an instant of time which is delayed from the time of occurrence of the clock pulse by an interval responsive to the difference between the selected clock rate and the highest clock rate of the system so that the video signal available at that instant is discarded. Upon the discharge of the photodetection array, the array is allowed to develop charges for a constant time interval until the occurrence of a subsequent clock pulse, whereupon the array is energized to generate a video line signal having a constant amplitude regardless of the selected clock rate. Specifically, the interval is determined by counting a unit time period which is equal to the reciprocal of a common multiple of the selectable clock rates, and the discharge is effected when the count reaches a number determined by the difference between the selected clock rate and the highest clock rate.

It is an object of the invention to generate a video line signal of constant signal level from a storage mode photodetection array driven at variable clock rates regardless of the selected clock rate.

The invention will be further described with reference to the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of an embodiment of the invention; and

FIG. 2 is a timing diagram useful for describing the operation of FIG. 1.

The facsimile transmitter of the present invention represented in FIG. 1 of the drawings includes a 2,048-bit storage mode photodiode array or detector 10 which is shown connected to a starting circuit 12 which energizes the detector to receive drive pulses from a source (not shown) of drive clock (FIG. 2A) through a gate 14. The rate of this clock is so selected that the photodetector 10 completes its delivery of a line video output within the period of a synchronization pulse (FIG. 2C) which appears at the start of each line scan. The sync pulse is applied to an AND gate 16 to enable it to pass a discharge clock pulse (FIG. 2D) used to discharge the photodiode array to reset it to the initial charge level. A 2,048-bit counter 20 is shown connected to the output of the gate 14 to count the number of clock pulses supplied to the photodetector 10. Therefore, the flip-flop 18 will be reset in response to a pulse count of 2,048 bits by the output of the counter 20 to terminate the supply of clock pulses to the photodetector 10 (FIGS. 2E, 2F and 2G).

A video output is thus delivered from the photodetector 10 and supplied to a first input of a comparator 22 for comparison with a reference voltage to eliminate any ambiguous level signal components so that the comparator output is a clear-cut, black-and-white signal. This signal is clocked into a shift register 24 by the clock pulses passed through gate 14 and an OR gate 26.

A flip-flop 28 is shown connected to the output of counter 20 which triggers flip-flop 28 into a set condition upon the count of 2,048 pulses of drive clock. A gate 30 is shown connected to the Q output of the flip-flop 28 to pass discharge clock pulses on lead 32 to the photodetector 10 in the presence of the high Q output state of flip-flop 28. The output circuit of the gate 30 is connected to an input of a programmable counter 34 which counts a predetermined number of input pulses to reset the flip-flop 28. The programmable counter 34 is so conditioned by means of a circuit designated by numeral 36 as to count as many discharge pulses to be applied to the photodetector 10 as necessary depending on the scanning frequency selected.

Assume that the system is capable of transmitting signals at one of a plurality of selectable transmission speeds which correspond to line scanning frequencies F1, F2, . . . Fn where Fn is the maximum frequency. Each line path of document is transmitted at one of intervals T1, T2 . . . Tn which correspond to the cycle period of the frequencies F1, F2 . . . Fn, respectively. Therefore, Tn is the minimum transmission interval of the system.

Consider now the minimum time interval necessary for the photodetector 10 to produce a video output of acceptable amplitude level, and let us designate this minimum interval T.sub.min. This minimum interval T.sub.min may be equal to or smaller than the transmission interval Tn of the system and the following relation can hold:

where, M is an integer including zero and N is an integer at least unity.

Let Fcm to denote a frequency which is a common multiple of the frequencies F1, F2 . . . Fn, and let Fi to denote any one of the frequencies F1 through Fn. In the present invention, Fcm is equal to the frequency at which the photodetector 10 is discharged, i.e. discharge clock rate is equal to Fcm.

Therefore, the number of discharging operations that is required of the photodetector 10 before it starts to generate video signals is determined by the following Equation: ##EQU1##

For purposes of illustration, the system is assumed to have 3 Hz and 5 Hz scanning frequency modes so that Fcm is at 15 Hz, i.e. the discharge clock rate is at 15 Hz. Assume, for the sake of simplicity, that M=0, and that the system is operating in the 3 Hz mode, it will be appreciated that the photodetector 10 is discharged "twice" by the output from the gate 30.

The circuit 36 determines the K value that is used to program the counter 34 so that "two" discharge clock pulses may be passed through the gate 30 to the photodetector 10. The circuit 36 is shown as comprising a division circuit 44 which performs division of an electrial value representing the frequency Fcm by another electrical value representing a selected frequency Fi. A second division circuit 46 provides division of an electrical quantity representing Fcm by another quantity representing Fn. The output of the division circuit 46 is multiplied in a multiplier 48 by a quantity representing N/(M+N) provided from a source 50. The output from the multiplier 48 is used to subtract from the output of the division circuit 44 by means of a subtractor 52 to generate a subtraction output which corresponds to the K value of Equation (2).

The programmable counter 34 is thus instructed to count two discharge pulses supplied from the output of gate 30 and reset the flip-flop 28 to terminate the supply of discharge clock to the photodetector 10 (see FIGS. 2I, 2J and 2K).

In response to the absence of synchronization pulses, gates 38 and 40 are activated to pass transmission clock pulses to the shift register 24 via OR gate 26 and clock out the video information now stored in the shift register via gate 40 to a utilization circuit (not shown) where the video signal will be processed into a form suitable for transmission.

If the system is switched to the 5 Hz scanning mode, the programming circuit 36 generates a signal which instructs the counter 34 to immediately reset the flip-flop 28 and inhibit it from being set in response to the output from the 2,048-bit counter 20. Therefore, no discharging operations occur. With the system being switched to the 5 Hz mode, the timing signal will be so automatically adjusted that the synchronization pulses occur at intervals smaller than for the 3 Hz mode. The photodetector 10 thus operates to accumulate charge in response to each synchronization pulse.