Control Circuits for Windscreen Wipers for Road Vehicles

This invention relates to control circuits for windscreen wipers for road vehicles.

It is already known to employ a control circuit using switches and relays to provide normal screen wiper operation and so called flick-wipe operation in which momentary closure of a contact of the control switch causes the wipers to carry out a single wipe cycle and then stop. For such an arrangement the control switch has one or more on positions in which it is held by detent means for normal operation and a further on position for which there is no detent means.

It is also known to provide a windscreen wiper arrangement with a control circuit for intermittent operation, i.e. where the wipers operate for a single cycle and then pause before another single cycle.

It is an object of the present invention to provide a windscreen wiper control circuit in which intermittent operation and flick-wipe operation can be obtained from a simple control switch with provision for flick-wipe.

A windscreen wiper control circuit in accordance with the invention comprises a control switch assembly including main contacts associated with detent means for selecting normal operation and a further contact without detent means for selecting flick-wipe or intermittent operation, a pulse length recognition circuit operable by the further contact and arranged to cause the wipers to operate in the flick-wipe mode or the intermittent mode according to the length of time for which the further contacts are closed.

Preferably the arrangement is such that a longer closure of the further contacts is required to obtain flick-wipe mode than that required to obtain intermittent mode.

The control circuit conveniently includes an intermittent wipe timer which is energised only when intermittent wipe mode has been selected.

The pulse length recognition means may include a bistable circuit and a timer circuit, initial closure of said further contacts operating to change the state of the bistable circuit and the timer circuit operating to reset the bistable circuit after a predetermined interval if the additional contacts are still closed. When intermittent wipe has been selected by a closure of the further contacts for a duration shorter than said predetermined interval, a second short closure of the contacts will reset the bistable circuit.

An example of the invention is shown in the accompanying drawing which is an electrical circuit diagram of the control circuit.

In the drawing, there is shown a control switch 10 of known type having four terminals 11, 12, 13 and 14, a spring-loaded bridging contact 15 the spring loading of which causes it to remain in any of the three positions in which it bridges the terminals and a spring wire contact 16 which can only bridge the terminals 12 and 13. The contact 15 is movable in either direction between three distinct detent positions.

Terminal 13 of the switch 10 is connected to a 12 V supply rail 17. Terminal 14 is connected through a relay coil 18 to an earth 19 and controlling a changeover contact 18a to determine whether power is applied to a fast or slow running brush of the windscreen wiper motor. The contact 18a is connected via a contact 20a of a relay 20 either to the 12 V supply or to a limit switch incorporated in the mechanism and providing a separate connection to the 12 V rail when the wipers are out of their parked position and a path to earth when they are in their parked position.

The terminal 12 of the switch 10 provides for slow running, a flick-wipe mode operation and intermittent mode operation. To this end the terminal 12 is connected by a resistor R.sub.1 to the base of an n-p-n transistor T.sub.1 which has its emitter connected to the rail 19 and the relay winding 20 connected between the rail 17 and its collector.

The terminal 12 is also connected to the anode of a diode D.sub.1, the cathode of which is connected to the base of a transistor T.sub.2 via a resistor R.sub.2, a capacitor C.sub.1 being connected between the cathode of the diode D.sub.1 and the rail 19. The emitter of the transistor T.sub.2 is connected to the rail 19 and its collector is connected to one input terminal of a bistable circuit. This bistable circuit comprises two transistors T.sub.3 and T.sub.4 with their collectors connected via respective resistors R.sub.3 and R.sub.4 and series capacitors C.sub.2 and C.sub.3 to the collector of the transistor T.sub.2 and their emitters both connected to the rail 19. Diodes D.sub.2 and D.sub.3 connect the bases of the transistors T.sub.3 and T.sub.4 to the interconnections of the resistors R.sub.3, R.sub.4 with their respective capacitors C.sub.2, C.sub.3 and a capacitor C.sub.4 is connected between the base of the transistor T.sub.4 and the rail 19. The collectors of the transistors T.sub.3, T.sub.4 are connected by respective resistors R.sub.5, R.sub.6 to the rail 17 and switching feedback is provided by cross-connected resistors R.sub.7, R.sub.8 between the collectors of the transistors T.sub.3 and T.sub.4 and the bases thereof. A resistor R.sub.9 is connected between the rail 17 and the collector of the transistor T.sub.2.

The capacitor C.sub.4 ensures that when the circuit is connected to the 12 V supply the bistable circuit initially goes into the state in which the transistor T.sub.3 is on and the transistor T.sub.4 is off. When the contacts 12, 13 are bridged the transistor T.sub.2 starts conducting almost immediately and causes the bistable circuit to change state so that the transistor T.sub.4 is then conducting.

Furthermore, the terminal 12 is also connected to a timing circuit which comprises a diode D.sub.4, a resistor R.sub.10 and a capacitor C.sub.5 in series between the terminal 12 and the rail 19. The capacitor C.sub.5 is bridged by a discharge resistor R.sub.11 and the junction of the resistor R.sub.10 and the capacitor C.sub.5 is connected by a resistor R.sub.12 to the base of a Darlington pair T.sub.5, T.sub.6 with its emitter connected to the rail 19 and its collector connected to the base of the transistor T.sub.4.

Thus if the contacts 12, 13 are bridged for long enough to cause the transistors T.sub.5, T.sub.6 to switch on the bistable circuit will be reset even though the transistor T.sub.2 is still on.

The output of the bistable circuit is taken from the collector of the transistor T.sub.4 and is applied via a resistor R.sub.13 to the base of an n-p-n transistor T.sub.7 with its emitter connected to the rail 19 and its collector connected by a resistor R.sub.14 to the rail 17. The collector of the transistor T.sub.7 is connected to the cathode of a zener diode D.sub.5 with its anode grounded to rail 19 and also to the power supply terminal pin 1 of an integrated circuit timer type SFC 606B. Pins 5 and 6 of this timer i.c. are connected to the rail 19 by capacitors C.sub.6, C.sub.7 respectively and are interconnected by two resistors R.sub.15 and R.sub.16 with a diode D.sub.6 bridging the resistor R.sub.15, and these components determining the on and off time of the signal at the output terminal, pin 10 of the device. Pins 7 and 8 are grounded and the output terminal pin 10 is connected to the collector of the transistor T.sub.1.

In use, slow running is selected by bridging the contacts 12, 13 with the detent contact 15. Transistor T.sub.1 then energises the relay 20. For fast running contacts 13, 14 are bridged.

For intermittent wipe mode operation the spring contact 16 is used to bridge the terminals 12, 13 briefly to set the bistable circuit and provide power to the timer i.c. by ensuring that transistor T.sub.7 is switched off. The relay 20 is thus energised periodically causing the wipers to complete one cycle and then stop repeatedly. A further brief closure of the contact 16 resets the bistable circuit, switching on the transistor T.sub.7 and removing operating current from the i.c. device.

For flick-wipe mode operation, the contact 16 is closed and held long enough for the transistor T.sub.5, T.sub.6 to switch on, e.g. about 11/2 seconds. This resets the bistable circuit and prevents intermittent wipe mode operation from commencing.