Sports Timing System

In known sports timing systems the peripheral devices such as the starting pistol, starting gate or platform, photocell and arrival sensing means which provide electrical impulsions in response to the determining events, are coupled to a central processor which controls the operations as well as the processing of the information in each case through at least two conductive wires.

In the special case of swimming competitions to which the following detailed description will be limited the greatest difficulties seem to arise and the invention is revealed to its greatest advantage. Nevertheless, the invention may, without any particular difficulty, be adapted to other domains. In a swimming pool each swimming lane may be equipped with three peripheral devices, namely an arrival touch plate, a manual switch for duplicating the measurements by an official and a starting platform which moreover enables the determination of errors during relay races. For a swimming pool having ten lanes one may easily determine that a minimum of 31 conductive wires is necessary if it is acceptable to use one wire common to all devices and in most cases where such is not acceptable there will be a total of sixty wires.

The difficulties arising from such an arrangement are known . . . . The cabling is heavy and quite expensive, above all in the case of systems which are intended to be moved around from pool to pool. Moreover, numerous multipin connectors will be required and these are likewise expensive. Finally, all connections and connectors must be and remain watertight, this being furthermore an important element in the costs. The invention described in Swiss Pat. No. 572,250 which enables working with touch pads having contacts immersed in the water does not eliminate the necessity that all lines must be watertight after coming out of the electronics involved in such touch pads. In addition to their high price, known systems may thus have considerable and serious problems of reliability in view of the multiplicity of connectors and connections.

The present invention proposes to overcome these problems through the utilisation of a single common two-wire cable shared among the peripheral devices for communicating with the central processor.

In a special arrangement for competitions in which several competitors are simultaneously competing, each along a track reserved to such competitor, in particular a lane in a swimming pool, the peripheral devices equipping this track or lane are coupled to the two-wire cable by a common electronic module.

FIG. 1 is a schematic representation of a timing installation in accordance with the invention.

FIG. 2 is the schematic drawing of an electronic module for coupling a peripheral device to the two-wire cable.

FIG. 3 shows timing of electrical signals at various points in the schematic diagram of FIG. 2.

In FIG. 1 which represents an installation according to the invention, intended for swimming competitions, there is provided a plurality of parallel water lanes each one reserved to a competitor. The central processor 1 for controlling the functioning of the system and the processing of information for the determination of the performance of the competitors, is coupled by means of a single two-wire cable 2 to electronic modules 3, 3', etc. mounted in series along the two-wire cable 2 and corresponding each to a water lane. To each module 3 there are connected in parallel the peripheral devices associated with the water lane for example, an arrival touch pad 4, a manual switch 5, which may be operated by a member of the timing staff, and a starting platform 6. In the case of a manual timing installation one may have in place of the touch pad 4 and platform 6 two further manual switches identical to switch 5.

In view of the serial arrangement of modules 3, 3', etc. their connection to the two-wire cable 2 may be made by means of insertable plug connectors which greatly facilitate set up and replacement thereof in the case of defects. Each module 3 includes the necessary electronics for transmitting by means of cable 2 information in the form of pulses coming from the peripheral devices 4, 5, 6 to the central processor 1 and for transmitting to the peripheral devices instructions coming from the processor. In the same manner the energizing of modules 3 and of peripheral devices 4, 5 and 6 is effected from central processor 1 by means of the two-wire cable 2.

Each module 3 may moreover include the electronic circuit as described in Swiss Pat. No. 572,250 already mentioned, this permitting working with submerged contacts. However, from the connection of the peripheral devices 4, 5, 6 to modules 3 and thence to the central processor 1 the connections should be watertight. Also the electronic portions of modules 3 will be preferably sealed into molded rubber housings as will the two pin plugs for connections between modules 3, 3', etc. and cable 2.

FIG. 2 shows a schematic diagram of a possible arrangement of the electronics in a module 3 in order to form an interface for a peripheral device P.sub.i. Reference should be made to this schematic and to FIG. 3 for a better understanding of the functioning of the arrangement. The two-wire cable 2 is represented by its two conductors. It is traversed in both senses by the information "INF" in the form of logic pulses. The central processor 1 continuously feeds cable 2 with trains of thirty clock signals of a period t.sub.1 separated by intervals t.sub.2 each of which corresponds in duration to two periods t.sub.1. For each clock signal the logic level "0" is maintained during t.sub.3 and the "1" level during t.sub.4. These signals are received by a counter 7 and by a monostable device M.sub.1 which, as soon as no further signals are received, delivers a signal of duration t.sub.6 for resetting counter 7 to zero. The contents of counter 7 are compared with the code number "i" of the peripheral device P.sub.i by a comparator 8. The code "i" is prewired into the module 3 as indicated by block 9. When counter 7 reaches a count equal to code "i", which it maintains for the duration of a clock signal, comparator 8 as controlled by a second monostable device M.sub.2 which also receives clock signals, delivers an output signal during a period t.sub.7. The monostable device M.sub.2 thus functions to furnish an enabling signal of duration t.sub.7 which permits comparator 8 during this period to transfer its information. The monostable device M.sub.2 is triggered on each falling edge of a clock signal and remains set for the period t.sub.7 where t.sub.1 >t.sub.7 >t.sub.3. The comparator signal is transmitted to a NAND-gate the second input of which is coupled to the output of the peripheral device P.sub.i. The output of the NAND-gate is coupled to the base of a transistor T.sub.i of which the emitter and the collector are coupled respectively to each of the wires of cable 2.

During the period t.sub.7 the state of the peripheral device P.sub.i will be probed. If, for the duration of signal, P.sub.i does not provide any information, that is to say remains at the logic "0" level, the NAND-gate will not transmit a signal, the transistor T.sub.i remains blocked and the clock signals "INF" recommence immediately following t.sub.3. If, on the contrary, P.sub.i provides a logic "1" T.sub.i becomes conductive and imposes a "0" level to "INF" for the period t.sub.7. The clock signals or "INF" may not return to the "1" level until after the period t.sub.5 =t.sub.7 -t.sub.3 which follows the rising edge of the pulse. Precisely, during this period t.sub.5 the central processor may interrogate the line and determine if the information "INF" is at the "0" level indicative that the peripheral device P.sub.i has emitted a signal. At the end of each cycle ending with the interval t.sub.2 all elements are returned to their initial condition, counter 7 being reset to zero by the signal of duration t.sub.6 from monostable device M.sub.1.

The cycle repetition rate must be sufficiently high to ensure that the period t.sub.8, between the instant when the peripheral device P.sub.i gives forth its information and that when such information is recognized and recorded by the central processor 1, is negligible relative to the desired precision of the timing.

Each module 3 is energized from the central processor 1 by the two-wire cable 2. During the periods t.sub.4 at level "1" the central processor 1 provides a current which charges a capacitor 11 across a diode 10 and thus provides the system with the necessary energy during the periods t.sub.3 at the "0" level of the clock signals.

Where several peripheral devices P.sub.i are required as shown in FIG. 1 the portion of the circuit comprising the two monostable devices M.sub.1 and M.sub.2 and the counter 7 may be common to these particular devices, but the portion comprising comparator 8, the source for the code "i", the NAND-gate and the transistor T.sub.i are individual to the peripheral device under consideration.

In an alternative arrangement a module 3 may be associated with each peripheral device P.sub.i and may be made an integral part of such peripheral device which is thus coupled directly to the two-wire cable 2.