Junction-Storage JFET Bucket-Brigade Structure

The field of the invention is in the solid state transistor art and more particularly in the art of junction field effect transistors in bucket-brigade delay line circuits (JFET BBDL).

It is well recognized that the analysis of the high-speed operating characteristics of a JFET bucket-brigade circuit shows that the charge transfer inefficiency of the device is proportional to the square of the total storage capacitance, C.sub.s. Therefore, for efficient high frequency performance it is important to minimize C.sub.s within the system constraints imposed by processing design rules. In the prior art many innovations have been made to improve the operating characteristics of JFET BBDL circuits. The most applicable prior art, it is believed, may be found in the following U.S. Pat. Nos. 3,639,813 to patentees Kamoshida et al; 3,663,873 to patentee Yagi; 3,784,847 to patentees Kurz et al; 3,790,825 to patentees Barron et al; 3,825,995 to patentees Kurz et al; 3,825,996 to patentees Barron et al; 3,841,917 to patentee Shannon; and 3,896,483 to patentee Whelan.

The novel JFET bucket-brigade structure disclosed eliminates the need for the MOS overlap capacitance of a conventional JFET brigade, and thereby greatly reduces the total storage capacitance. In comparison with conventional prior art JFET BBDL structures the novel device herein disclosed provides larger contact areas for gate electrodes, it eliminates the prior need for close spacing between clock electrodes, and the need for thin oxides. The disclosed device is a less complex structure than the prior art and thus provides a higher yield during manufacturing. Typical eighty stage embodiments provide measured transfer efficiencies at 50 MHz that are approximately a factor of five times better than that previously measured for a 10-stage conventional prior art JFET bucket brigade.

FIG. 1 schematically illustrates a section of a typical embodiment of the invention;

FIG. 2 schematically illustrates a top view of an alternative structural layout of an embodiment of the invention; and

FIG. 3 schematically illustrates a section view of the alternative structure represented in FIG. 2.

An embodiment of the invention is schematically illustrated in section in FIG. 1. The novel structure typically comprises an n-type silicon epitaxial layer 11 conventionally formed on a p.sup.- conductivity type silicon substrate 12. The p.sup.+ type top gates 13 are conventionally diffused into the epi-layer 11 as illustrated. The p.sup.+ buried gates 14 are conventionally formed in the surface of the substrate and aligned with the source side of the top gates 13. Note that the diffusion of the top-gate 13 extends far into the drain region 15, thereby providing a large gate-drain storage capacitance C.sub.gd (relative to the gate-source capacitance G.sub.gs). It is essential that C.sub.gd be greater than C.sub.gs to achieve bucket-brigade action (otherwise directionality is lost). The channel region of the device is substantially defined by the dimensions of the buried gate. Embodiments may thus readily be designed for long or short channel devices (as is typical for conventional prior art JFET BBDLs). It is to be noted that there is no longer a requirement for thin oxides. The oxide thickness 16, can be of any convenient thickness thereby eliminating oxide pin-hole defects, a common potential yield hazard in the prior art devices. It is also to be noted that the gate spacing 17 no longer need to be a critically small dimension. The source region, the drain region, and the channel region are represented respectively at 23, 15, and 22 for the one element. (It is to be understood that while only the operation of the left hand element of FIG. 1 is being described, that it applies to all the plurality of similar elements contained on the integrated solid state semiconductor chip.)

Another embodiment is schematically illustrated by FIGS. 2 and 3. Both .phi..sub.1 and .phi..sub.2 top gates having contacts 30 and 31 are typically formed by depositing p-type polycrystalline silicon 32 and 33 on an n-epitaxial layer. In FIG. 3, the p-type polycrystalline silicon top gates are represented at 53 and the n-epitaxial layer at 51. The buried p.sup.+ gates shown at 54, in FIG. 3 do not show in the top view of FIG. 2. The active channel region of this structure is shown in cut-away area 35. Single aluminum contacts 30 and 31, are made to connect the respective phase excitation to the respective top gate. In these embodiments the gate electrode spacing 17 of FIG. 1 no longer exists. The packing density of the circuit is therefore improved, as one mask alignment step has been removed.

Conventional solid state fabrication techniques are used to form the structures which are then subjected to a conventional heat treatment to obtain good p-n junctions in the active chanel regions.

Typical 80-stage junction-storage JFET bucket-brigade embodiments of the invention, fabricated as taught herein, have been operated successfully at clock frequencies up to and including 50 MHz. The transfer inefficiency at that clock frequency (50 MHz) is typically approximately 6 .times. 10.sup.-3. This represents a five-fold improvement in performance (at 50 MHz) over that achieved with prior art 10-stage conventional JFET BBDLs. The linearity of these operating embodiments has been measured with the following results. At f.sub.c = 50 MHz, harmonic distortion was less than 1%. At f.sub.c = 5 MHz harmonic distortion measured less than 0.5%, corresponding to 45 dB linearity. The 3 dB bandwidth of the device was 4 MHz with f.sub.c = 50 MHz. By using conventional preemphasis, the 3 dB bandwidth can be increased to approximately 9 MHz.