Analog Signal Processing System

1. Field of the Invention

The present invention relates to an analog signal processing system which receives an input analog signal and performs various operations including addition, subtraction, multiplication and division by the use of processors such as micro-computers.

2. Description of the Prior Art

As a result of recent progress in digital circuit technology, processors such as small-sized micro-computers have been made available at lower cost, with consequent widening of the fields of application. In utilizing these processors with an analog system, it generally is necessary to provide an analog/digital converter (hereinafter referred to as A/D converter) on the input side of each processor for converting an analog signal to a digital signal, and also a digital/analog converter (hereinafter referred to as D/A converter) on the output side for converting a digital signal to an analog signal. Since the A/D converter is expensive and has a complicated circuit configuration, there exists a disadvantage that if an A/D converter and a micro-computer are employed to constitute a system, the entire equipment also turns out to be complicated, with increased cost. Particularly in the case where a plurality of input signals are processed, it is necessary to provide as many A/D converters as there are input signals, or to incorporate a multiplexer and perform analog-to-digital conversion after switching the input signals by the multiplexer, hence rendering the overall structure extremely intricate.

A principal object of the present invention is to provide an improved analog signal processing system which requires neither an A/D converter nor a multiplexer on the input side of a processor for dealing with input analog signals, thereby to achieve a simplified structure and low cost of construction.

A further object of the invention is to provide an improved analog signal processing system which is capable of holding the result of a computation even in the event of interruption of the power supply and, upon restoration of the power supply, continuously producing the result obtained immediately before such power interruption.

Yet another object of the invention is to provide an improved analog signal processing system capable of performing rapid and high-resolution conversion of an analog signal to a digital signal.

FIG. 1 is a block diagram of an exemplary system embodying the present invention;

FIG. 2 is a time chart for explaining the operation of the system shown in FIG. 1;

FIG. 3 is a flow chart showing an example of a converting procedure in the case where a processor converts an input analog signal to a digital signal;

FIGS. 4 through 6 are block diagrams of other embodiments of the invention;

FIGS. 7, 11 and 14 are block diagrams of further embodiments of the invention where circuits are additionally connected to enhance the resolution in analog-to-digital conversion;

FIG. 8 is a flow chart showing an example of the processor operation in the embodiment of FIG. 7;

FIG. 9 is an explanatory diagram plotting the operation in a count mode;

FIG. 10 is a conceptional diagram of a digital signal obtained through conversion;

FIG. 12 is a flow chart showing an instance where, in a count mode, the output of a D/A converter is varied stepwise in both positive and negative directions by two least significant bits; and

FIG. 13 plots the waveform representing the operation in FIG. 12.

In the block diagram of FIG. 1 showing an exemplary embodiment of the present invention, an analog signal el is applied to a comparator 10 through one input terminal, and the comparator output is supplied to processor 20 such as a micro-computer. A D/A converter 30 converts the digital signal of processor 20 to an analog signal fed to the other input of the comparator 10. An analog signal sample and hold means 40 also is provided in the form of a semi-conductor switch 41, a capacitor 42 and an amplifier 43.

The comparator 10 compares the analog signal el with the analog signal ef, and feeds the result of this comparison an an input signal to the processor 20. This processor includes an input port 21, a data memory 22 such as read-write memory, a central processor unit 23, a program memory 24 such as a read-only memory, and an output port 25. The input port 21 receives the output signal of the comparator 10 and keeps this signal therein until it is loaded by the signal from the central processor unit 23.

The data memory 22 temporarily stores the signal obtained from the input port 21 or stores the result of the computation in response to the signal from the central processor unit 23. The program memory 24 has previously stored in it the procedural steps for converting an analog signal to a digital signal, the procedural steps for controlling the peripheral circuits, various computing procedures and also data required for computation. The content of program memory 24 is read out by the signal from the central processor unit 23. The central processor unit 23 fetches the state of the signal fed to the input port 21 and writes the signal state into the data memory 22, or decodes the computing procedure from the program memory 24, or performs digital computation by using the data read out from the program memory 24 or the signal obtained from the data memory 22.

The output port 25 receives the digital signal from the data memory 22 or the central processor unit 23 and feeds a digital signal to the D/A converter 30 in response to the signal obtained from the central processor unit 23, or feeds a control signal to the analog signal hold circuit 40 to control the same. The D/A converter 30 converts the digital signal of the output port 25 to an analog signal and feeds it to the other input terminal of the comparator 10, and further functions to apply the analog signal to the analog signal hold means 40 when the switch 41 is turned on by an output instruction signal (control signal) from the processor 20.

The operation of the system having the above-mentioned structure now will be described below with reference to the time chart of FIG. 2. FIG. 2 (a) is an input analog signal e1, and FIG. 2 (b) is a sampling clock signal for general control of the operation in the digital processor 20. The period t of this sampling clock signal is determined in consideration of the variation speed and so forth of the input analog signal e1. First, as shown in FIG. 2 (c), the processor fetches the output signal of comparator 10 at the rise of the sampling clock signal in accordance with the signal (program) stored in the program memory 24, and the input analog signal applied to the input terminal of comparator 10 is converted to a digital signal by the analog/digital conversion loop consisting of comparator 10, processor 20 and D/A converter 30.

Among a variety of methods known for conversion of an input analog signal to a digital signal, there is, for example, sequential comparison in which conversion is performed as shown in the flow chart of FIG. 3. (1) The most significant bit in an A-register formed in a portion of the central processor unit 23 is set to "1", so that the digital amount corresponding to 50 percent of the total capacity of the A-register is set therein. (2) Subsequently, the content of the A-register is fed to the D/A converter 30, so that the digital amount corresponding to the said 50 percent is converted to an analog amount by the D/A converter 30, and the analog signal e.sub.f is applied to the other input terminal of comparator 10. (3) Then, the output signal of the comparator 10 is loaded for discrimination of its state. (4) If the state of the signal thus loaded is "0". or e.sub.1 <e.sub.f, the most significant bit of the A-register set to "1" initially is reset to "0". And if the signal state is "1", or e.sub.1 >e.sub.f, the most significant bit of the A-register set to "1" initially is left unchanged. (5) The A-register is checked to decide whether the above procedure is terminated for all the bits, and if it is not yet terminated, (6) the next bit or the second bit weighted half to the most significant bit is set to "1". This completes setting of the digital signal corresponding to 25 percent or 75 percent of the total capacity in the content of A-register. Here, the procedure returns to (2) again, and the steps from (2) to (6) are repeated in the same manner as the foregoing. This time, the third bit is set to "1" in step (6). In this manner, the steps from (2) to (6) are executed continuously until all the bits of the A-register are terminated, that is, until the least significant bit is set to "1" or "0". The procedure is completed upon termination of all the bits, and the content remaining in the A-register represents the value of the digital signal converted from the input analog signal e.sub.1.

The digital signal thus obtained is processed in a desired operation such as addition, subtraction, multiplication, division or square root extraction as shown in FIG. 2 (d) by using the data in the data memory 22 or the data in the program memory 24 in accordance with the program stored in the program memory 24. The operation to be executed depends on the content of the program stored previously in the program memory 24. Upon completion of the predetermined computation, the result is fed to the D/A converter 30 through the output port 25 as shown in FIG. 2 (e) and is converted to an analog signal. Subsequently, as shown in FIG. 2 (f), an output instruction signal is fed to the sample hold switch 41 so that the analog signal from the D/A converter 30 is applied to the analog signal hold means 40. Thus, the result of computation in the form of analog signal such as shown in FIG. 2 (g) can be obtained continuously from the output terminal 50. In this case, the analog signal from D/A converter 30 is applied also to the other input terminal of comparator 10, but it is not concerned at all since the output signal of comparator 10 is not loaded in the processor 20.

In the system of the present invention, constructed as described above, the processor performs time-sharing control on A/D conversion, predetermined computation, output to the D/A converter and control signal (output instruction signal) to the analog signal hold means, hence eliminating the necessity of installing any expensive A/D converter on the input side of the processor and consequently simplifying the whole structure with reduction of the cost.

FIGS. 4 through 6 are block diagrams of other examples embodying the present invention.

The embodiment of FIG. 4 shows the case where a plurality of input analog signals are received and a plurality of output analog signals are produced. In this system, three comparators 11, 12, 13 are installed on the input side of a processor 20, and analog signals e1, e2, e3 are applied to the corresponding comparators 11, 12, 13 individually through one input terminal thereof while an analog signal e.sub.f from a D/A converter 30 is applied to each comparator in common through the other input terminal. A terminal 15 is provided on the input side of processor 20 so as to apply an interrupt signal for changing instruction procedure or computing procedure from an operation control unit or to apply a digital input signal for effecting allocation by a program. Moreover, two analog signal hold means 40.sub.1, 40.sub.2 are installed on the output side of D/A converter 30.

In this embodiment, the processor 20 first converts the analog signals e1, e2, e3 sequentially to digital signals according to the procedure of FIG. 3, and then stores the digital signals in a portion of a data memory. Subsequently, the digital signals stored previously in the data memory are read out to execute predetermined computation. The result is written in a portion of the data memory or is delivered through the output port and the D/A converter 30. The result of adding e1 and 32, for example, is fed to the analog signal hold means 40.sub.1, and the result of multiplying the sum of e1 and e2 by e3, for example, is fed to the analog signal hold means 40.sub.2.

The procedure may be so changed that the processor 20 first converts the input analog signals e1, e2 to digital signals, then makes a computation using the digital signals representative of e1 and e2, subsequently converts the input analog signal e3 to a digital signal, and executes the predetermined computation again. Such a change of the procedure is achievable by the program stored in the program memory, or by the interrupt signal applied to the terminal 15, or by the digital input signal serving to effect allocation according to the program.

In the case where input analog signals are plural as in this embodiment, it is possible to economize on the capacity of the data memory by a procedure in which, instead of converting all the input analog signals in the beginning, an analog-to-digital conversion is performed of only the input analog signal required during computation and subsequently repeating the computation. Depending on the result of computation, it is further possible to omit the computation of the remaining input analog signals. In such a case, the computing speed can be increased.

According to the system of the present invention, even when the number of input analog signals is plural as in this embodiment, it is necessary merely to provide comparators on the input side of the processor. There exists another merit that even when the number of output analog signals is plural, it is necessary merely to provide an analog signal hold means on the output side of the D/A converter. Moreover, due to the terminal 15 provided on the input side of the processor, instruction procedure or computing procedure from the operation control unit is properly changeable by the interrupt signal or the digital input signal serving to effect allocation according to the program.

In the embodiment of FIG. 5, the output side of a processor 20 is equipped with a digital/pulse width converter 30 which is a kind of D/A converter to convert a digital signal to a pulse-width signal, and this signal is applied to the other input terminals of comparators 11, 12 in common through an isolation means 31 such as phototransistor and a smoothing circuit 32. The outputs of the comparators 11, 12 are fed to the processor 20 through an isolation means 33, and the output of digital/pulse width converter 30 is fed through an isolation means 34 to an analog signal hold means 40 including a smoothing circuit. Thus, it is another advantage of the system of the present invention that, as in this embodiment, the input side and the output side can be easily isolated from each other by conversion of the digital signal from the processor to a pulse-width signal.

In each of the foregoing embodiments, the result of computation is obtained through the analog signal hold means. However, if necessary, the structure may be so modified as to obtain the result in the form of digital signal from the processor 20.

The embodiment of FIG. 6 is equipped with means 60 to feed the output signal of an analog signal hold means 40 to one input terminal of a comparator 11. Furthermore, it is also equipped with an operation parameter setting circuit 65 consisting of variable resistors 66, 67 and a direct current source 68, wherein analog set signals e10, e20 obtained from the setting circuit 65 are applied to the corresponding comparators 13, 14 individually through one input terminal thereof.

Supposing now that a power source (not shown) connected to the processor 20 causes interruption of power supply in this embodiment, a switch 41 is turned off so that the result of computation immediately before the power interruption is held in the form of analog value in a capacitor 42. The value thus held is maintained substantially constant except for the change resulting from slight leakage of the capacitor 42. When the power source resumes its normal state to place the processor 20 into operation, the processor first loads the output analog signal e.sub.0 of the analog signal hold means 40, which represents the result of computation individually before the power interruption, through the comparator 11 and converts the signal e.sub.0 to a digital signal by an A/D conversion loop consisting of the comparator 11, the processor 20 and the D/A converter 30. The digital signal thus obtained is stored in a portion of the data memory, and is used as the initial value of computation when required or is fed as the hold output value to the analog signal hold means 40 through the D/A converter 30 and the switch 41. And even after restoration of the power supply, the result of computation immediately before the interruption can be produced continuously from the output terminal 50. The operation parameter does not become extinct at the occurrence of power interruption since it is set by the variable resistors as an analog value.

In the embodiment of FIG. 7, a slope signal generator 70 for generating a slope signal by changing the output of a D/A converter 30 stepwise in response to the signal from a processor 20 is connected to the output side of the D/A converter 30. The slope signal generator 70 comprises an integrating circuit, which consists of a resistor 71 and a capacitor 72, and a switch S connected in parallel with the resistor 71. A comparator 10 compares an analog signal e.sub.1 applied to one input terminal with a signal e.sub.f applied to the other input terminal from the slope signal generator 70, and feeds the result of comparison as an input signal to the processor 20. Here, the processor 20 employed is such that it has at least a sequential comparison function and a count function. The D/A converter 30 converts the output digital signal of processor 20 to an analog signal and feeds it to the analog signal hold means 40 through the switch 41 while feeding it simultaneously to the other input terminal of comparator 10 through the slope signal generator 70. In this embodiment, the slope signal is the one generated by utilizing the stepped output of the D/A converter, and it generally denotes a temporary lagging signal, a sawtooth signal or a triangular signal increasing and/or decreasing continuously with the lapse of time. The amplitude (final value) of such signal corresponds to an integral multiple of one LSB (least significant bit) of the A/D converter 30. In converting an input analog signal to a digital signal, the system of the above-described structure first performs an A/D conversion in a sequential comparison mode with no slope signal being generated, and then executes A/D conversion in a count mode with the generation of slope signal. At the time of A/D conversion, the switch 41 is kept turned off. Hereinafter the action of A/D conversion in this system will be described in detail with reference to the flow chart of FIG. 8. First, the system is placed in a sequential comparison mode for A/D conversion. In this mode, the processor 20 turns on the switch S of the slope signal generator 70 so as not to generate any slope signal, and converts the input analog signal e.sub.1 to a digital signal through sequential comparison by a loop including the comparator 10, the processor 20 and the D/A converter 30. In the sequential comparison mode, the steps (1) through (6) are the same as those in the flow chart of FIG. 3. At the termination of these steps in the sequential comparison mode, the content D1 remaining the A-register becomes the value of the digital signal obtained by converting the input analog signal e.sub. 1 through sequential comparison, and its resolution is equivalent to the number of bits of the D/A converter 30. Subsequently, the system proceeds to a count mode for A/D conversion. In this mode, the processor 20 first resets the content of a counter formed in a portion of the central processor unit 23 (Step (7)). The switch S of slope signal generator 70 is turned off, and simultaneously the output signal of D/A converter 30 is varied stepwise by, for example, one least significant bit of D/A converter (Step (8)). Thus, the output of D/A converter 30 is varied as shown in FIG. 9(a), and the output e.sub.f of slope signal generator 40 is shaped into a slope signal which has an amplitude of one LSB and, as plotted in FIG. 9 (b), increases toward the output signal of D/A converter with the lapse of time at the time constant of resistor 71 and capacitor 72. Next, the processor 20 loads the output signal of comparator 10, and discriminates the state of this signal (Step (9)). And if the state of the signal thus loaded is "0" or e.sub.1 >e.sub.f, 1 is added to the counter (Step (10)). Steps 9 and 10 are repeated until the state of the comparator output signal becomes "1", that is, until coincidence is attained between the input analog signal e.sub.1 and the signal e.sub.f from slope signal generator 40. When the condition e.sub.1 .ltoreq.e.sub.f is obtained, the count mode is terminated. At this time, the content D2 remaining in the counter represents t.sub.x (time required until coincidence is attained betweee.sub.1 and e.sub.f after generation of slope signal) shown in FIG. 9, and this value corresponds to e.sub.x (position of input analog signal e.sub.1 within one LSB). The relationship among them is expressed as follows:

consequently, as illustrated in FIG. 10, the processor 20 adds the digital signal D2 obtained in the count mode to the digital signal D1 obtained in the sequential comparison mode, hence enhancing the resolution by D2 to gain a high-resolution digital signal corresponding to the input analog signal e.sub.1. Subsequently, the processor 20 executes computation by using the digital signal thus obtained, so that a high resolution is attained also with respect to the result of computation.

In the embodiment of FIG. 11, the input side of a processor 20 is equipped with comparators 10, 11 each of which receives an input analog signal e.sub.1 through one input terminal thereof, and the output terminal of a D/A converter is connected to the other input terminal of comparator 10, while the output terminal of a slope signal generator 70 is connected to the other input terminal of comparator 11. And the output signal of comparator 11 is loaded so as to function as the switch S in the embodiment of FIG. 7. That is, in the sequential comparison mode, A/D conversion is executed at a high speed by a loop including comparator 10, processor 20 and D/A converter 30, while in the count mode, A/D conversion is executed by a loop including comparator 11, processor 20, D/A converter 30 and slope signal generator 40.

FIG. 12 is a flow chart showing the procedure in the case where, at the time of A/D conversion in the count mode in the embodiment of FIG. 7 and 11, the output of D/A converter 30 is varied stepwise in both positive and negative directions by, for example, two least significant bits; and FIG. 13 plots the waveform representing the operation in FIG. 12. In the procedure from Steps (7) through (10), a positive slope signal e.sub.f1 having an amplitude of two least significant bits is generated, and a time t.sub.a is found which is required until coincidence is attained between the positive slope signal e.sub.f1 and an input analog signal e.sub.1 after generation of the signal e.sub.f1. Subsequently, in the procedure from Steps (11) through (14), a negative slope signal e.sub.f2 having an amplitude of two least significant bits is generated, and a time t.sub.b is found which is required until coincidence is attained between the negative slope signal e.sub.f2 and the input analog signal e.sub.1 after generation of the signal e.sub.f2. And at Step (15), t.sub.a /t.sub.a +t.sub.b) is computed to obtain a digital signal D2 in the count mode.

According to the above procedure, the slope signal obtained from the signal generator 70 is such that it changes substantially linearly with the lapse of time as plotted in FIG. 13, and the inclination angles .theta. of both positive and negative slope signals become equal to each other. Consequently, since t.sub.a +t.sub.b corresponds to one least significant bit, the digital signal D2 corresponding to e.sub.x (analog value from D1 to e.sub.1) can be obtained accurately by computing t.sub.a /t.sub.a +t.sub.b. The above procedure is advantageous in the point that the accuracy of A/D conversion is not affected by a change in the value of any circuit element of slope signal generator 70 as long as symmetry is maintained in the positive and negative slope signals. Moreover, since the width of the stepwise change in the output signal of D/A converter is as large as two least significant bits, the comparing action is rendered accurate and the inclination angle .theta. of each slope signal is widened to accelerate the conversion speed in the count mode.

In the embodiment of FIG. 14, the D/A converter 30 employed is of the current output type, and the slope signal generator 70 comprises an amplifier 73 and a parallel circuit of a resistor 71 and a capacitor 72 connected between the input and output terminals of the amplifier 73. The switch S connected in series with the capacitor 72 serves to control timing of slope signal generation. According to this system, the slope signal obtained from the slope signal generator 70 is such that it varies linearly with the lapse of time.

In the embodiments of FIGS. 7, 11 and 14, the slope signal generator may be composed of other circuit configurations if the output signal of D/A converter is used for slope signal generation.

Thus, as mentioned hereinabove, the present invention makes it possible to implement an improved analog signal computing system of a simplified structure at low cost.