Burst Gating Signal Generating Circuit

This invention relates to chrominance processing circuitry in general and more particularly to the generation of a burst gating signal for the accurate extraction of the chrominance burst signal from the composite video waveform.

Color television receivers use the 3.58 MHz chrominance burst signal, generated by the transmitter, to synchronize and otherwise condition the receiver's locally-generated chrominance reference oscillator. Because only approximately eight cycles of the burst signal are provided on the "back-porch" of the horizontal synchronizing pulse, it is desirable to "gate" the burst signal so that only it, and not spurious signals or noise components, are allowed to reach the chrominance processing stages.

Historically this has been done by using the horizontal flyback pulse as the burst gating signal, relying on its coincidence with the burst period. Such systems have proved less than ideal because, inter alia, the horizontal flyback pulse typically has a width of approximately 13 microseconds, whereas the period of the burst signal is in the neighborhood of 2 microseconds. Furthermore, because of errors in the free-running frequency of the receiver's horizontal oscillator, there may be as much as a .+-.4 microseconds difference between the occurrence of the synchronizing pulses and the flyback pulses. As a result, the burst gate pulsewidth is necessarily made wider than the burst duration, to the detriment of the chrominance control characteristics of the receiver. This is especially evident when the first microsecond or so of an active line is allowed to pass through the burst gate. The reference oscillator will then possess an error component related to the signal that has erroneously passed through the burst gate. The color content of the picture will vary with the error component.

A more accurate burst gating pulse can be derived from the trailing edge of the horizontal sync pulse. In one form, the horizontal sync pulses can be differentiated and used to open the burst gate. However, because a differentiating circuit necessarily has the characteristics of a high-pass filter, noise pulses received with the composite video signal will also open the burst gate, thereby introducing erroneous information into the chrominance reference channel.

It is an object of this invention to develop an accurately-timed burst gating signal.

It is a further object of this invention to develop such a signal in a manner that maintains the noise immunity of the burst gate.

It is a further object of this invention to insure that erroneous signals do not enter the chrominance reference channel, thereby degrading the performance of the television receiver.

The above and other objects, advantages and capabilities are achieved in one aspect of the invention by a burst gating signal generating circuit which comprises circuitry for differentiating and clipping the horizontal sync pulses so as to develop single-polarity, exponentially-decaying pulses. These pulses are then applied to one terminal of a switch which has a second terminal coupled to ground. Horizontal flyback pulses are delayed and coupled, substantially coincidentally with the occurrence of the chrominance burst signal, to a third terminal of the switch so that the switch provides an appropriately-timed burst gating signal to the input of a burst gate.

FIG. 1 is a schematic diagram of the subject invention, showing significant waveforms developed therein. The shaded rectangular areas in waveforms 1A-1D represent the chrominance burst period and are intended to illustrate the relationship between those waveforms and the chrominance burst signal.

FIG. 2 is a timing diagram showing the temporal relationship of the waveforms depicted in FIG. 1.

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure in conjunction with the accompanying drawings.

As illustrated in waveform 1A, a source of horizontal synchronizing (Sync) pulses is coupled to an input terminal A of a differentiating circuit 10. The differentiating circuit comprises a series-connected resistor R1 and capacitor C1, connected, in turn, to a resistor R2 and coupled to a source of potential voltage B.sup.+. R2 is connected in parallel with a clipping circuit 20 in the form of a diode D1, having an anode connected to B.sup.+ and a cathode connected to the junction of R2 and C1.

As shown in waveform 1B, circuit 10 differentiates each sync pulse to form a negative-going pulse and a positive-going pulse. As the negative-going pulse approaches B.sup.+ -0.7 volt, D1 becomes conductive, thereby clipping the negative excursion to approximately B.sup.+ - 0.7 volt. Because D1 is back-biased by the positive-going pulses, these pulses are left substantially intact. As will be shown below, the width of the positive-going pulse determines the length of time the burst gate will be open; accordingly its width is preferably in the neighborhood of the burst signal period, approximately (assuming 8 cycles of burst) 8/3.58 microseconds. Persons skilled in the art are aware that the effective width of the positive pulse is determined by the magnitude of the sync pulses and the RC time-constant of the differentiating circuit.

The resultant differentiated and clipped sync pulses are coupled to a first terminal of a switching means 30, that is, the collector of transistor Q1. Means 30 has a second terminal, the emitter of Q1, connected to ground through B.sup.+, and a third terminal, the base of Q1, connected to a phase-delaying and biasing means 40.

Means 40 has an input terminal B coupled to source of horizontal flyback pulses which occur during the horizontal retrace period. As shown in waveform 1C, these pulses have a truncated or half-sinewave waveform with a period of approximately 13 microseconds and, in this embodiment, a peak amplitude of approximately 17 volts. The flyback pulses are AC coupled through a resistor R3 and a capacitor C2 to the base of Q1. The base of Q1 is also coupled, through the parallel combination of a resistor R4 and a capacitor C3, to circuit ground.

R3 and C3 operate to phase-shift the flyback pulses so that the waveform at the base of Q1 is delayed with respect to the waveform at terminal B. Their values are chosen so that the peak amplitude of the flyback pulse at the base of Q1 occurs coincidentally with the start of the chrominance burst period. R4 provides a source of base current for Q1 so that, in the absence of a flyback pulse, that is, during the horizontal scan period, Q1 is saturated and the voltage at its collector, as well as the voltage at the cathode of D1, is clamped at approximately B.sup.+, less the saturation voltage of Q1. When saturated, Q1 effectively shorts the resultant sync pulses through B.sup.+ to ground. Otherwise these pulses are AC coupled through R5 and C4 to the input of a burst gate illustrated as a transistor Q2. The timing diagram of FIG. 2 shows the manner in which the burst gating signal of waveform 1D is generated and made to be substantially coincident with the chrominance burst period.

Waveform 2A depicts a typical sync pulse at the output of the receiver's composite video detector circuit. Approximately 6-8 cycles of chrominance burst are present on the back porch of the sync pulse. Waveform 2B represents the separated sync pulse as it appears at terminal A. Due to processing within the receiver, the trailing edge of the sync pulse in 2B is somewhat delayed with respect to the pulse of 2A, but still occurs prior to the start of the burst period. Waveform 2C shows the flyback pulse that is applied to terminal B and waveform 2E shows the pulse that is applied to the base of Q1. As pointed out above, by virtue of R3 and C3 the flyback pulse at the base of Q1 has been phase-shifted, or delayed, so that its peak amplitude coincides with the start of the chrominance burst period. The arrowheads in 2E represent the time during which the voltage at the base of Q1 is of sufficient amplitude to assure that Q1 is turned off and the resultant sync pulses are allowed to pass through R5 and C4 to terminal C. Waveform 2D shows the resultant sync pulses at the collector of Q1. Note that, in the absence of the flyback pulse at the base of Q1, Q1 would be saturated and the resultant sync pulses shorted to ground. The leading edge of the positive-going pulse and the trailing edge of the sync pulse occur simultaneously, that is, slightly before the start of the burst period. The differentiating circuit is designed so that the positive-going pulse decays at an exponential rate during the burst period. The waveforms 2D and 2E cooperate to form the burst gating signal waveform, present at terminal C and shown in 2F. The burst gating signal waveform, in essence, represents a logical AND function of the differentiated pulses, 2D, and the delayed flyback pulses, 2E.

The period between the arrowheads indicates the time during which there is a positive voltage at that base of Q2, that is, the time when the burst gate will be open. As can be seen, the gate will be open shortly before the start of the burst period. Although it is shown as closing exactly at the end of the burst period, it may be open for a slightly longer period without an appreciable degradation in performance. As stated above, in order to achieve this result, it is necessary that the differentiating circuit 10 be designed to have the proper RC time constant. For a peak amplitude of the negative-going sync pulses equal to approximately 17 volts and for values of 1K ohm, 150 picofarads, and 12K ohm for R1, C1 and R2 respectively, the differentiating circuit provides a 5-volt positive-going pulse that decays as shown in 2D. The rate of decay and, hence, the width of the differentiated pulse are critical to the extent that, if the pulse is made to decay too rapidly, a portion of the burst period will be "gated out," thereby degrading the performance of the chrominance processing circuits. Conversely, if the pulse decays too slowly, the burst gate will be open for an excessive period of time and additional, undesired signals, possibly including video information on the subsequent horizontal line, may enter the chrominance processing circuits. However, a salient advantage of the invention disclosed herein is that, as shown in 2E, sometime near the end of the flyback pulse, Q1 will again become saturated, thereby assuring that burst gate will be closed.

Furthermore, although switching means 30 is illustrated in its simplest form, that is, a single PNP transistor, it is obvious that any device or combination of devices that effect a logical "AND" function with respect to the resultant sync pulses and the delayed flyback pulses will be satisfactory. The essential feature is that the burst gating signal be generated only during those intervals when both the resultant sync pulses and the delay flyback pulses are above a predetermined level, thereby obtaining the phase accuracy and noise immunity of each of these signals. For instance, in an alternate embodiment it might be convenient to apply the sync pulses to an input of an analog gate so that they appear at the output only when the flyback pulses are above a sufficient amplitude.

Accordingly, while there has been shown and described what is at present considered the preferred embodiment of the invention it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.