Method and Apparatus for Operating an Internally Timed Switching Regulator

This invention relates to internally timed switching regulators in general and more particularly to an improved method and apparatus for operating such a regulator.

The invention is particularly directed to a method of operating such a regulator in which a controllable switch is closed when the output voltage falls below a predetermined first set value and in which the controllable switch is opened when the output voltage exceeds a second set value and to an internally timed switching regulator for implementing this method comprising two input terminals and two output terminals, a controlled switch and a choke coupling the input terminals to the output terminals, with a capacitor shunted across the output terminals and a bypass diode shunting the L-C circuit comprising the capacitor and choke, and a limit indicator. The output of the limit indicator is connected to a control input of the switch and has an actual value input the voltage present at the output terminals and, as a reference value input, a line connected to a terminal and to the junction point of a series circuit consisting of a first resistor and a first Zener diode shunted across the bypass diode.

The basic method and an internally timed switching regulator of this nature are described in "Siemens-Zeitschrift" 48, (1974), Supplement "Integrated Building Block Systems SIMATIC", pages 76 to 79. They are used particularly in power supplies, e.g., in integrated circuit power supplies. In these internally timed switching regulators, the switch, which is in general a control transistor, is either completely conducting or completely open. The pulsating d-c voltage at the output of the switch is smoothed again by an L-C member following the switch. Through the choice of the first and second set value, periodic operation of the switch is obtained, the duty cycle being responsible for the magnitude of the constant d-c voltage which is present at the output terminals. The two set values are generally given by two settable limits of a limit indicator, the hysteresis of which thereby determine the switching frequency of the internally timed switching regulator. In the known method, however, the switching frequency remains dependent on various other parameters, for instance, the input voltage, the ambient temperature and the load. It is therefore scarcely possible to keep the switching frequency of a switching regulator operating in accordance with the known method constant, which is important, for instance, if the switching frequency is to remain outside the audible range, i.e., above 20 kHz, in order to eliminate acoustical interference.

The problem thus arises to develop a method of the type mentioned at the outset and apparatus for implementing this method in such a manner that the switching frequency remains at least approximately constant.

According to the present invention, this problem is solved by feeding a function exponentially varying in time as the second reference value. With an exponentially decaying second reference value, a constant "on" time is obtained and with an exponentially rising second reference value a constant "off" time is obtained.

With the method according to the present invention, a switching frequency at least independent of the ambient temperature is obtained for constant "on" time or a switching frequency independent of the ambient temperature as well as largely independent of the input voltage and the load for constant "off" time. Thereby, a constant frequency corresponding to the specified requirements can be realized, with which acoustical interference can also be eliminated. It should be noted that this constant frequency is achieved with only a few additional passive components, whereby only little cost accrues. Using the method according to the present invention, synchronization of the switching frequency of parallel connected switching regulators can also be carried out without beat frequencies being generated as is done in known switching regulators. Thereby, the advantages of an externally timed switching regulator is obtained in addition to those of an internally timed regulator.

In one advantageous apparatus for implementing the method acording to the present invention, the reference value input of the limit indicator is connected to the tap of an R-C member which is shunted across the first Zener diode. With this embodiment, constant "on" time and therefore, independence of the switching frequency from the ambient temperature can be realized.

In a second advantageous embodiment, a second series circuit consisting of a second resistor and a second Zener diode is shunted across the bypass diode, the second resistor of the second series circuit being shunted by an R-C member, to the tap of which the reference input of the limit indicator is connected. A diode can be shunted across the resistor of the R-C member. In this embodiment, the "off" time depends only on the input voltage. With increased input voltage, the "off" time increases and one thereby obtains independence of the switching frequency from the ambient temperature as well as essential independence from the input voltage and the load. For stabilizing the hysteresis of the limit indicator in this embodiment, the second resistor in the second series circuit consisting of the second resistor and the second Zener diode can have a tap to which, on the one hand, the R-C member and, on the other hand, a further, third Zener diode are connected, the further, third Zener diode being shunted across a partial resistor and the second Zener diode of the second series circuit. The "off" time is then also independent of the input voltage. Thus, however, the switching frequency is dependent on the input voltage. If the ratio of the input voltage to the output voltage is large, however, this dependence is negligibly small.

FIG. 1 is a schematic diagram of a prior art internally timed switching regulator.

FIGS. 2a and 2b are waveform diagrams illustrating the operation of the circuit of FIG. 1.

FIG. 3 is a schematic diagram of a switching regulator according to the present invention.

FIG. 4 is a waveform diagram illustrating the operation of the circuit of FIG. 3.

FIG. 5 is a schematic diagram of a further embodiment of the present invention.

FIG. 6 is a waveform diagram illustrating operation of the circuit of FIG. 7.

FIG. 7 is a schematic diagram of an embodiment of the present invention which is a modification of FIG. 5.

To illustrate the problems which are the basis of the present invention, FIG. 1 shows the schematic circuit diagram of an internally timed switching regulator which is known, for instance, from the above-mentioned literature reference as a power supply for integrated circuits. Input terminals 1, to which the input d-c voltage U.sub.1 is applied, are connected to a controllable switch 2 which may be, for instance, a transistor. The switch 2 is followed by an L-C member 3 consisting of a series circuit of a choke 4 and a capacitor 5 acting as a smoothing filter or lowpass filter. The output terminals 6, to which the load 7 is connected, are coupled to the electrodes of the capacitor 5. As an equivalent circuit, the equivalent series loss resistance of the capacitor 5 is shown as a resistor 8 connected in series with the latter. In general, electrolytic capacitors are used in switching regulators and the capacitor 5 of the L-C member 3 will be such. The series loss resistor 8 is then the equivalent resistance of the electrolytic capacitor, also called the equivalent series resistance (ESR). The L-C member 3 is shunted by a bypass diode 9.

For driving the switch 2, its control input 2a, e.g., the base of a transistor, is connected to the output of a limit indicator or control amplifier 10 with two point behavior. The output voltage U.sub.6 present at the terminals 6 is fed to the actual value input 10a of the limit indicator 10 via the line 11. The reference value 10b is connected via a resistor 12 to a terminal 13, to which a reference voltage U.sub.r1 is applied as the first set value. In addition, the reference value input 10b of the limit indicator 10 is connected via a variable resistor 14 to the junction point 15 of a series circuit 16, which consists of a resistor 17 and a Zener diode 18, which are shunted across the bypass diode 9. With the resistor 14 and the series circuit 16, a second set value U.sub.r2 which is larger than U.sub.r1 is established. At the output of the limit indicator 10, a signal is present, by which the switch 2 is closed when the actual value falls below the reference value U.sub.r1. This signal disappears and the switch 2 is opened when the second set value U.sub.r2, obtained from the series circuit 16, is exceeded.

The operation of the switching regulator according to FIG. 1 will be explained with reference to FIGS. 2a and 2b, in which the voltage U.sub.3 present at the input of the L-C member 3 and the current I.sub.4 flowing in the choke 4 are plotted versus the time t. The limit indicator 10 of the circuit according to FIG. 1 compares the output voltage U.sub.6 with the reference voltage U.sub.r1. If U.sub.6 becomes smaller than U.sub.r1, then the switch 2 is closed at the time t.sub.1 by the output signal of the limit indicator 10. During the "on" time .DELTA.t.sub.1, a current I.sub.2 now flows via the switch 2 into the storage choke 4 until at the time t.sub.2 the output voltage U.sub.6 has risen to the upper set voltage given by the resistor 14, or the upper tripping point U.sub.r2, and the switch 2 is opened at the time t.sub.2 via the output signal of the limit indicator 10. During the subsequent "off" time .DELTA.t.sub.2, the energy stored in the choke 4 continues to drive the current I.sub.9 through the load 7, the capacitor 5 and the bypass diode 9 until the output voltage U.sub.6 reaches the lower return tripping point given by the reference voltage U.sub.r1 again and the switching cycle begins over again.

For the hysteresis .DELTA.U determined by the tripping point and the return tripping point, we have ##EQU1## and the current I.sub.4 in the choke 4 is given by:

where U.sub.18 is the voltage dropping across the Zener diode 18 and R.sub.12 and R.sub.14, the resistances of the resistors 12 and 14 respectively.

A triangular a-c current flows via the capacitor 5: .DELTA. I=I.sub.4 -I.sub.6, where I.sub.6 is the smoothed current which flows via the output terminals 6 and which corresponds to the mean value of I.sub.2 and I.sub.9. Because of the series loss resistance 8, one obtains, with the current .DELTA.I flowing via the capacitor 5, a corresponding triangular voltage drop which is equal to the hysteresis .DELTA.U, at least if the capacity of the capacitor 5 is large enough:

where R.sub.8 is the resistance of the resistor 8 and U.sub.6 the mean value of the output voltage. The hysteresis .DELTA.U thus appears as the ripple of the output voltage U.sub.6.

During the "on" time .DELTA.t.sub.1, one obtains as the slope of the current in the choke relation: ##EQU2## wherefrom the "on" time .DELTA.t.sub.1 and the ripple or hysteresis .DELTA.U results: ##EQU3## where L.sub.4 is the inductance of the choke 4. The decrease of the current in the choke 4 during the "off" time .DELTA.t.sub.2 is given by: ##EQU4## wherefrom, with Equation (3), the following relations are obtained for .DELTA.t.sub.2 and .DELTA.U: ##EQU5## From this, the switching frequency F can be calculated from

and one obtains: ##EQU6##

It can be seen from this relation that in internally controlled switching regulators according to FIG. 1 with predetermined, constant hysteresis .DELTA.U, the switching frequency F depends on the series loss resistance 8 and the input voltage U.sub.1, the switching frequency F being proportional to the resistance R.sub.8 of the resistor 8. For higher input voltages, the "on" time .DELTA.t.sub.1 is shorter, while the "off" time .DELTA.t.sub.2 remains constant. The frequency change resulting therefrom is small, however, as the "on" time in general is substantially shorter than the "off" time. Thus, with an input voltage U.sub.1 of 24 V and an output voltage U.sub.6 of about 5 V, for instance, the ratio .DELTA.t.sub.1 /.DELTA.t.sub.2 is approximately 1:4. The switching frequency can also change with the inductance of the choke 4. The inductance of the storage choke 4 can change by 10% for a current which is about 0.1 times the nominal current. According to the relations above, the switching frequency will thus also decrease proportionally.

In the switching regulator shown in FIG. 1, the switching frequency at which the switch 2 is driven, is therefore dependent on the input voltage U.sub.1 as well as on the resistance R.sub.8 of the series loss resistor 8 and thus, on the ambient temperature. This can lead particularly to acoustic interference, as was already explained.

An embodiment of a switching regulator according to the present invention, in which the influence of the series loss resistor 8 is compensated, is shown in FIG. 3. The switching regulator according to FIG. 3 differs from the switching regulator according to FIG. 1 by the compensating arrangement 19. In the compensating arrangement 19, the Zener diode 18 of the series circuit 16 is shunted by an R-C member 20 consisting of a capacitor 21 and a resistor 22, which in the illustrated embodiment is variable, and the tap 23 of which is connected via a decoupling diode 24 to the reference input 10b of the limit indicator 10.

The operation of a switching regulator according to FIG. 3 will be explained in conjunction with FIG. 4, in which the voltage U.sub.10 appearing at the reference value input 10b of the limit indicator 10 is plotted versus the time t. With the R-C member 20, one obtains an exponentially decaying hysteresis. Under the assumption that the input resistance of the limit indicator 10 goes toward infinity, one obtains for the voltage U.sub.10 at the reference value input 10b of the limit indicator 10 the relation ##EQU7## where R.sub.22 is the resistance of the resistor 22 and C.sub.21 the capacity of the capacitor 21. In first approximation, U.sub.10 has a linear waveform during the "on" time .DELTA.t.sub.1 and its slope N.sub.1 is: ##EQU8## The slope N.sub.2 of the output voltage U.sub.6 during the "on" time .DELTA.t.sub.1, because of Equation (7), is given by ##EQU9## where N.sub.1 is large as compared to N.sub.2. With an input voltage U.sub.1 = 24 V, and output voltage U.sub.6 of 5 V, a reference voltage U.sub.r1 of 5 V, an inductance of the choke 4 of 100 .mu.H, a resistance of the series resistor 8 of 50 mohm and a switching frequency F of 20 kHz, for instance, one gets N.sub.1 = -1 V/.mu.s and N.sub.2 = 0.0095 V/.mu.s. With this, the reference value voltage U.sub.10 and the actual value voltage U.sub.11 can be expressed in first approximation by:

At the upper tripping point of the limit indicator 10, we have U.sub.10 = U.sub.11 with the result: ##EQU10##

The "on" time .DELTA.t.sub.1 is thus constant in first approximation and independent of the slope of the output voltage as well as of the actual value voltage. With Equations (7) and (9) one obtains for T: ##EQU11## and as a result, for the switching frequency: ##EQU12## Thus, the switching frequency F is only still inversely proportional to the input voltage U.sub.1, as .DELTA.t.sub.1 and U.sub.6 are constant. Dependence on the resistance R.sub.8 of the series loss resistor 8 and thus, dependence on the ambient temperature no longer exists. However, with increasing load, a voltage drop can also occur in the switch 2, which causes an additional change of the switching frequency F.

FIG. 7 illustrates an embodiment of the switching regulator of the present invention in which the "off" time is constant, and the switching frequency therefore becomes independent of the series loss resistance 8 and also substantially independent of the input voltage U.sub.1 and the load 7. The embodiment according to FIG. 7 differs from the switching regulators according to FIGS. 1 and 3 by the compensating circuit 25. The compensating circuit 25 contains a second series circuit 26 consisting of a resistor 27 and a Zener diode 28, this second series circuit again being shunted across the bypass diode 9. The resistor 27 comprises two partial resistors 27a and 27b in series with a tap therebetween. The resistor 27b is shunted by an R-C member 29, comprising capacitor 31 and a resistor 30. The series circuit comprising the resistor 27b and Zener diode 28 is shunted by a further zener diode 35. The tap 32 of the R-C member 29 is connected via a decoupling diode 33 to the reference value input 10b of the limit indicator 10. So that the capacitor 31 can discharge fast when switching on, a diode 34 is shunted across the resistor 30.

Upon switching off at the time t.sub.2, the R-C member 29 generates an exponentially rising reference value voltage or hysteresis, which is fed via the diode 33 to the reference value input 10b of the limit indicator 10. The peak value of this hysteresis voltage is stabilized by the Zener diode 35. This exponentially increasing hysteresis cooperates with the hysteresis generated by the resistor 14, whereby a constant "off" time .DELTA.t.sub.2 is obtained, independent of the resistance of the series loss resistor 8, the input voltage U.sub.1 and the load. Since however, the "on" time .DELTA.t.sub.1 changes as a function of the input voltage U.sub.1, the switching frequency F depends on the input voltage U.sub.1. Since the "on" time .DELTA.t.sub.1 is small compared to the "off" time .DELTA.t.sub.2 if the ratio U.sub.1 /U.sub.6 is large, this dependence is negligibly small for a large ratio of U.sub.1 /U.sub.6.

The operation of the switching regulator according to FIG. 7 will be explained in conjunction with FIG. 6, in which the reference value voltage U.sub.10 present at the input 10b of the limit indicator 10, is plotted versus the time t. The constant "off" time .DELTA.t.sub.2 and the switching frequency F are calculated similarly as in connection with FIG. 3. It follows from the exponentially rising hysteresis during the off time .DELTA.t.sub.2 that U.sub.10 increases linearly with a slope ##EQU13## Where U.sub.H is the hysteresis voltage, U.sub.28 the Zener voltage of the Zener diode 28, U.sub.x the Zener voltage of the Zener diode 35, and U.sub.r1 the first reference voltage applied to the terminal 13. Because of equation (10), the slope of the output voltage U.sub.6 and, therefore, the actual value voltage U.sub.11, during the "off" time, .DELTA.t.sub.2 is as follows: ##EQU14## where .vertline.N.sub.3 .vertline. >> .vertline.N.sub.4 .vertline.. For an input voltage of 24 V, an output voltage of 5 V, a reference voltage U.sub.r1 of 5 V, a voltage U.sub.28 at the Zener diode 28 of 10 V, a resistance R.sub.8 of 50 mohm and a switching frequency of 20 kHz, for instance, one obtains the slope N.sub.3 = 0.325 V/.mu.s and the slope N.sub.4 = 0.0025 V/.mu.s. During the "off" time .DELTA.t.sub.2 for U.sub.10 and U.sub.11 one obtains therewith:

and at the intersection of U.sub.10 and U.sub.11, which represents the return tripping point or the lower reference value, it follows from U.sub.10 = U.sub.11 : ##EQU15## Thus, .DELTA.t.sub.2 is constant if N.sub.3 is constant. From this, the switching frequency F can be calculated, using Equations (6) and (10), and one obtains ##EQU16## Thus, the switching frequency F is also independent of the series loss resistor 8 in the embodiment according to FIG. 5. However, it remains dependent on the input voltage U.sub.1, but this dependence is slight and can generally be neglected, since for U.sub.1 > U.sub.6, the expression (U.sub.1 - U.sub.6)/U.sub. 1 is approximately constant. For U.sub.1 >> U.sub.6, the dependence disappears practically entirely, since the fraction given above becomes approximately 1.

A modification of the embodiment according to FIG. 7 is shown in FIG. 5. In this embodiment, the compensating circuit 25 is designed without a Zener diode 35. The hysteresis voltage U.sub.H is therefore not constant but increases with the input voltage U.sub.1. Thereby, the "off" time .DELTA.t.sub.2 is also increased at higher increased voltages U.sub.1 and the frequency dependence still existing in the embodiment of FIG. 7 is further reduced.

It should further be mentioned that the switching regulators according to the present invention as per FIGS. 3, 5 and 7 can be connected parallel via the terminals 36 and synchronize each other. Thus, the switching regulator according to the present invention combines the advantages of an externally timed switching regulator with those of an internally timed one.