Audible Speed Indicator

The invention relates to an apparatus for producing audio pulses whose frequency varies as a function of the speed of a vehicle above a predetermined speed.

It is quite demanding on the driver of an automobile to control the speed of his automobile using the visual speedometer. Having to continuously glance at the visual speedometer interferes with the more important task of watching the road and steering the automobile. Controlling the speed of the automobile with the visual speedometer demands constant and annoying interruptions in the task of watching the road, making the job of driving safely more difficult. Moreover, while a driver's vision is overloaded, his hearing capabilities are underused in driving his automobile.

The present invention relates to an apparatus which employs a simple and effective electronic circuit to produce a train of audio pulses having a frequency which varies as a function of the speed of the vehicle, at least above a predetermined speed. The frequency of the audio pulses increases and the amplitude decreases with increases in the speed of the vehicle. Since one's hearing is very sensitive to changes in the frequency of the sounds, the driver reacts very sensitively and accurately to changes in the speed of the vehicle. The driver's speed control with such an apparatus becomes reflexive and he can give all his attention to watching the road and steering, controlling the speed of the vehicle without the necessity of watching the speedometer at the same time.

The audio speed indicator sounds are not annoying because they are so powerfully useful to the driver. When the automobile changes speed, the driver wants to know that change and the audio pulses produced by the apparatus are the best way to do this. The sounds are reassuring and comforting because they respond predictably and sensitively to the speed of the automobile, increasing the pleasure and safety of driving.

In the specific embodiment of the invention described in detail below, the circuitry includes a speed sensor for producing a pulse train having a frequency which is directly proportional to vehicle speed. This can be accomplished, for example, with the conventional magnetic pick-ups of the types utilized to produce electrical signals for speed controllers. A second pulse train is produced having a frequency which varies as a function of a manual setting and is accordingly related to a specific desired speed. The frequencies of these two pulse trains are compared and a third pulse train is produced to drive a speaker to produce an audio pulse train which has a frequency which is directly proportional to the difference between the frequencies of the first two pulse trains and which is produced only when the frequency of the pulse train corresponding to the desired speed is exceeded by the frequency of the pulse train of the vehicle speed.

More particularly, the first pulse train circuit preferably includes a pulse shaping Schmitt trigger circuit driven by pulses from a magnetic pick-up on the speedometer cable. The pulse shaping circuit output is one input of an RS flip-flop which may be a pair of cross-connected NAND gates. The second pulse train circuit may be a blocking oscillator connected to a potentiometer, the position of which can be adjusted in accordance with a desired manual setting corresponding to any desired speed. The output of the blocking oscillator is by way of a JK flip-flop the other input of the RS flip-flop. The output of the RS flip-flop after going through a simple lumped delay circuit is one input to a third NAND gate and the inverted output of the pulse shaping circuit connected to the magnetic pick-up is the other input to this NAND gate. The NAND gate output frequency is directly proportional to the difference frequency between the pulses produced by the magnetic pick-up in response to the vehicle speed and the pulses produced by the JK flip-flop connected to the blocking oscillator as a function of the manual setting of the potentiometer.

The output of this NAND gate is applied to another JK flip-flop to produce pulses which trigger an SCR which drives a tweeter speaker to produce a series of audio pulses having a frequency which indicates to the vehicle driver, when he has exceeded his desired speed, the amount by which he has exceeded it. No sound is produced by this audible speed indicator when the vehicle speed is less than the desired speed, although the circuitry can be modified to provide a different type of audio or other indication for that condition.

Many other objects and purposes of the invention will be clear from the following detailed description of the drawings.

FIG. 1 shows a block diagram of the unique circuitry of this invention;

FIG. 2 shows a detailed schematic of one embodiment of the apparatus of this invention; and

FIG. 3 shows a timing diagram illustrating the operation of the embodiment of FIGS. 1 and 2.

Reference is now made to FIG. 1 which is a block diagram of one embodiment of this application. "A" pulses which can be varied in frequency by a manual setting are applied to the R input of flip-flop 10. "B" pulses whose frequency is directly proportional to the vehicle speed are applied to the S input of flip-flop 10. "A" pulses shift flip-flop 10 to the state where a logical 1 appears at the "Q" output and a logical 0 at the "Q" output. Similarly "B" pulses shift flip-flop 10 to the state where a logical 1 appears at the "Q" output and a logical 0 at the "Q" output. The "Q" output of flip-flop 10 is delayed by lumped delay circuit 12 and then applied as enabling input to gate 14. The "B" pulses are also applied to gate 14 which produces an output pulse on output 16 only when the output of the lumped delay circuit 12 is logical 1. The delay circuit prevents gate 14 passing the "B" pulses which shift flip-flop 10. For gate 14 to pass a "B" pulse, two "B" pulses on the S input must be received without receipt of an "A" pulse on the R input. The frequency of the output of gate 14 thus is the difference in frequency between the two pulse trains which are applied to flip-flop 10 when the frequency of the "B" pulses is greater than the frequency of the "A" pulses.

Referring now to FIG. 2, which illustrates one detailed schematic of the arrangement illustrated in block diagram in FIG. 1, pulses produced by magnetic pick-up 100 are applied to the input of a type of Schmitt trigger pulse shaping circuit 104. Circuit 104 produces and applies steep wavefront rectangular pulses to the differentiating circuit comprising capacitor 105 and resistors 107 and 108. The output of this differentiating circuit is the pulse train "B" in FIGS. 1 and 3 and the input to NAND gate 106 which together with NAND gate 124 comprises RS flip-flop 10 in FIG. 1. Differentiation of the output of pulse shaping circuit 104 is necessary because flip-flop 10 requires very short pulses to work properly.

A conventional blocking oscillator 108 having a frequency substantially independent of the "B" pulses and the source voltage is connected by transistor 110, which makes the timing capacitor current independent of the voltage across the timing capacitor, to potentiometer 112 which constitutes a manual control and which can be set at any number of taps or positions each corresponding as illustrated to a predetermined set speed. Resistors 114 and 116 are adjustable in order to calibrate the manual control.

The output of blocking oscillator 108 is applied by transistor 120 to the clock input of JK flip-flop 122 which produces and applies steep wavefront rectangular pulses to the differentiating circuit comprising capacitor 123 and resistors 125 and 127. The output of this differentiating circuit is the pulse train "A" in FIGS. 1 and 3 and the input to NAND gate 124 which together with NAND gate 106 comprises the RS flip-flop 10 in FIG. 1. The output of RS flip-flop 10 is applied via a lumped delay circuit comprising inductor 126, capacitor 128, and resistor 130 to NAND gate 16 in FIG. 2.

Gate 16 also has applied to it the "B" pulses from circuit 104 which are inverted by NAND gate 132. When the output of the lumped delay circuit is high, pulses from NAND gate 132 are applied to the clock input of JK flip-flop 140. The output of JK flip-flop 140 triggers SCR 146 to produce audible pulses from tweeter speaker 142. Resistor 150 connecting the SCR to the supply voltage via the tweeter speaker causes the SCR to switch off.

As can be seen with reference to FIG. 3, each time two "B" pulses occur between adjacent "A" pulses, gate 14, FIG. 1, produces an output pulse and accordingly the frequency of the pulse train at the output of gate 14 is directly proportional to the difference in frequency between the "A" and "B" pulse trains when the frequency of the "B" pulse train is greater than the frequency of the "A" pulse train.

There is another aspect of this invention which is significant. The circuitry is purposely designed so that the sound intensity of the audio output decreases as the frequency of the output audio pulse train produced by speaker 142 increases. The reason for this reduction in sound intensity is that as the frequency of the audio pulse train increases, the pulses would sound louder if the intensity of the pulses was kept the same for all frequencies and the audio pulse train usefulness decreases at the higher frequencies of the audio pulse train.

This sound intensity reduction with frequency is accomplished by the RC circuit comprising resistor 150 and capacitor 152.

Many changes and modifications in the above described embodiment can, of course, be carried out without departing from the scope thereof. Accordingly, that scope is intended to be limited only by the scope of the appended claims.