Multi-Frequency Digital Wave Synthesizer for Providing Analog Output Signals

1. Field of the Invention

This invention relates to digital wave synthesizers and more particularly to sine wave synthesizers in such devices as frequency shift keying transmitters.

2. Description of the Prior Art

In the prior art, it has been common practice to represent digital data in the form of a high frequency pulse train. Digital computers, for example, operate at extremely high speeds utilizing digital data in the form of bi-level pulses. Transmission of the pulses is generally done by changing from digital to analog.

In the past, producing a symmetrical analog waveform in response to a series of periodic pulses has been expensive in terms of necessary hardware and time. Also, when a change is made in the input from a "mark" to a "space", the sudden change in frequency causes an inordinate amount of noise. Also, such a shift in frequency often results in a sudden change in voltage, also contributing to noise.

Other prior art systems were devised wherein a separate generator provided one frequency for the "mark" input digital signal and another generator provided a second frequency for the "space" digital input. However, the point at which switching is done is unknown and therefore the noise problem as indicated above exists in this system as well.

In the instant invention, by assigning a predetermined voltage to each of the n segments irrespective of which of the plurality of output analog signals is being formed, and simply by varying the period of the segment as determined by which analog output signal is being formed, the above problems are minimized, if not eliminated.

The preferred embodiment of this invention is for the synthesizing of a sine wave in a frequency shift keying transmitter wherein a binary "1" or "mark" results in a sine wave output of a given frequency and a binary "0" or "space" results in a sine wave of a different frequency. A plurality of pairs of frequencies corresponding to input digital signals are available and identification information is stored in a combination of read-only-memory (ROM) and programmable logic array (PLA). A selection of the frequency pair provides one address input to the ROM-PLA combination for either the "mark" frequency or the "space" frequency. A second address input is that of the segment number. The segment number plus the particular frequency desired provides an output of a binary representation of the period of the particular segment. Each segment of each available analog sine wave output has the same voltage assigned to it in the voltage distribution network output. Furthermore, the sequence of segments is never altered. Therefore, when a "mark" input appears to replace a "space" input, or vice versa, the next segment will follow with the same output voltage, but with a different period.

Each sine wave output is made up of n segments. The segments have periods of A and B. In any of the output sine waves x+y = n where x is a number of segments having a period of A duration and y is a number of segments having a period of B duration.

In the preferred embodiment, n = 16 and x and y are integers. A and B are also integers, measured in microseconds with B equal to A+1.

By incorporating two distinct segment periods in a given output sine wave, the integrity of the sine wave can be vastly improved so that the frequency developed is almost exactly equal to the desired frequency.

FIG. 1 is a block diagram depicting the digital wave synthesizer.

FIG. 2 illustrates the positional relationship between FIGS. 2a-2d which are a schematic diagram of FIG. 1.

FIG. 3 is a schematic diagram of a stage of the counter to segment decoder and switch inverter S1 of FIG. 2.

FIG. 4 is a schematic diagram of the clocked ground biased node 150 of FIG. 2.

FIG. 5 illustrates, in exaggerated form, a decrease in frequency of a synthesized sine wave from a "mark" to a "space".

FIG. 1 illustrates the multi-frequency digital wave synthesizer 10 in block form. A register select 70 is shown having an output 21 to amplitude register 12 which in turn has an output 23 to amplitude adjust 18 which functions to provide a predetermined reference voltage on its output to wave generator 19.

Another output 22 of register select 70 is an input to frequency register 13 which has an output 25 to address latch 14. The digital data input in the form of binary "1's" or "0's" ("mark" or "space") appears on input line 24 which provides another input to address latch 14. Address latch 14 has an output 28 which serves as an input to logic array 40, an array of two read-only-memories (ROM's) and one programmable logic array (PLA). The array has an output 29 to down counter 16 which has an output 20 to segment counter 17 and also has an output 31 connected as an input to the down counter 16 itself and also an output 27 serving as another input to address latch 14. Segment counter 17 has an output 26 serving as still another input to address latch 14 and also has an output 32 serving as another input to wave generator 19. The down counter 16 has an output 33 also serving as an input to wave generator 19. The output of wave generator 19 is the desired synthesized wave.

In broad operational terms, the register select 70 receives information from the selection circuitry of the system in which the synthesizer is employed. In this preferred embodiment, the system is a modem for connection to a telephone line to provide communications in both directions and is fully described in copending U.S. patent application Ser. No. 811,657, filed June 30, 1977, entitled "CCD Filters and Modems Incorporating Such Filters" and assigned to the assignee of this invention. For example, the particular amplitude desired is selected and output 21 from the register select 70 provides the amplitude register 12 with this selection in binary form. Amplitude register 12 then provides a signal on output 23 to the amplitude adjust 18 which then, through a well known network of weighted, series resistive attenuation, provides a particular output reference voltage.

Having set the output voltage desired, the particular frequency pair required is selected by the system. For example, a common frequency pair consists of a 1070 Hz signal for the "mark" and a 1270 Hz signal for the "space". Then when a binary "1" is received on input 24, the output frequency to be provided is 1070 Hz. When a binary "0" is received on input 24, a sine wave having a frequency of 1270 Hz is provided. Address latch 14 provides the necessary addresses resulting from the signal on input 24 as well as the frequency pair information on line 25, segment count on line 26, and an end of segment indication on line 27. The logic array 40 then responds to the signals on output 28 from address latch 14 by providing on output 29 information to down counter 16 as to the period of the particular segment to be generated. Down counter 16 provides a signal to segment counter 17 over output 20 after each segment has been completed so that segment counter 17 maintains the current segment identification or count. Wave generator 19 is provided with the particular segment identification from segment counter 17 on output 32 and is also provided with the timing information from down counter 16 on output 33. Down counter 16, activated by a system clock having a frequency of 1 MHz counts in one microsecond intervals so that when the counter has counted down, for example, 58 or 59 (for a "mark" at 1070 Hz -- to be described later) -- it provides a signal to the segment counter signifying that the segment has ended and the next segment is now going to be counted. This information is also sent back to the down counter 16 itself to permit reloading it, and to the address latch 14 to provide a new address so that the next segment information is obtained from logic array 40. The segment sequence is never changed, nor the voltage amplitude assigned to it -- only the period is a variable.

In FIG. 2, register select 70 shown is a well known programmable logic array (PLA) which need not be explained in detail. Shown in block form are inputs A0 through A4 with input A0 being inverted through inverter 71 to provide A0 directly to PLA 70 and also inverted again through inverter 72 to provide A0 to PLA 70. A1 through A4 are treated exactly the same, that is, the particular signal and its inverse are provided. Inputs A0 through A4 come from the modem system itself and ultimately select the amplitude of the output sine wave and the pair of frequencies representing mark and space desired. Input "CRU-CLK" is a clock input from the communication register unit employed in the system which is inverted through inverter 73 and connected as an input to NOR circuit 76 whose output is inverted through inverter 77 for entry into PLA 70. This input is used for gating out of information from PLA 70.

Another input is "CS" which is a chip select input used for selecting one of a plurality of wave generators and is inverted twice through inverters 74 and 75, serving as another input to NOR circuit 76 and also as a gating signal for amplitude register 12 and frequency register 13.

Another input "CRU-OUT" is a signal from the communication register unit mentioned above which is inverted through inverter 78 to provide signal "D" and again through inverter 79 to provide signal "D" which enable the gates in amplitude register 12 and frequency register 13.

The outputs of PLA 70 are applied to amplitude register 12 and frequency register 13 as shown. Significant to this invention are outputs B5, B6 and B7 which are connected to frequency register 13. Amplitude register 12, to which outputs B1, B2 and B3 are connected is simply part of the apparatus for providing a desired amplitude of output waveform. Having the circuitry for selectively providing one of a plurality of available output amplitudes is an advantageous feature of this waveform generator, but is not germaine to the invention described herein. The remaining outputs are not of interest to this invention.

Output B1 is applied to stage 45 of frequency register 13. Output B1 is applied as an input to AND circuits 34 and 36, each of which also have an enabling input, D and D, as mentioned above. AND circuit 34 serves as an input to NOR circuit 35 and AND circuit 36 serves as an input to NOR circuit 37. The output of NOR circuit 35 is applied as another input to NOR circuit 37, the output of which is applied as another input to NOR circuit 35, forming a latch. The channel of field effect transistor (FET) T1 connects the output of NOR circuit 35 to the input of inverter 38 whose output is designated L0. The gate of T1 is activated by the signal CS from the output of inverter 75.

Stages 46 and 47 which receive outputs B2 and B3, respectively, are identical to stage 45 and provide outputs designated L1 and L2, respectively. L0, L1 and L2 are outputs that are used to adjust to voltage level of the output waveform by application to the amplitude adjust 18.

Outputs B5, B6 and B7 are applied to frequency register 13, the stages of which are identical to stage 45 of amplitude register 12. Stages 48, 49 and 50 receive outputs B5, B6 and B7, respectively, and have outputs 25a, 25b, and 25c, respectively, which are applied to stages 58, 59 and 60, respectively, of address latch 14. Outputs 25a, 25b and 25c are also inverted and applied to NOR circuit 41 whose disable output (DIS) is applied to counter-to-segment decoder 140. Stage 57 of address latch 14 is identical to the other stages and therefore its description applies as well to stages 54-56 and 58-60.

FET T2 has its channel connected at one end to input line 24 and to the input of inverter 51 at the other, as well as to one end of the channel of FET T3. The output of inverter 51 serves as an input to inverter 52 whose output is connected to the other end of the channel of FET T3 and also serves as an input to ROM 41 of logic array 40. The gate of FET T2 is activated by a signal on line 27 clocked by clock pulse .phi.A. The gate of FET T3 is activated by a clock pulse .phi.B. Pulses .phi.A and .phi.B are provided by the system (not shown) and are two non-overlapping 1 MHz pulse trains. The inputs to stages 53, 54, 55 and 56 of address latch 14 are provided from segment counter 17 on lines 26a, 26b, 26c and 26d, respectively. Outputs 28a, 28b, 28c and 28d coming from stages 53 through 56, respectively, are applied directly and inverted to ROM 41. Outputs 28e, 28f, 28g, and 28h coming from stages 57, 58, 59 and 60, respectively, are applied directly and inverted to PLA 42. The outputs of PLA 42 are applied to ROM 43. ROM's 41 and 43 and PLA 42 form logic array 40. ROM's 41 and 42 are well known read-only-memories and need not be described in detail. PLA 42 is a programmable logic array and is also well known and need not be described in detail. Suffice it to say that the combination of devices provides storage for the pertinent information relating to the particular segments required for the corresponding frequencies. Outputs 29a through 29h from ROM 43 are applied to stages DC1 through DC7 of down counter 16. Stage DC1 is shown in detail and is identical to the remaining stages of down counter 16. Output 29a from ROM 43 is connected to the channel of FET T5, the other side of which is connected to one end of the channel of FET T6, and as an input to inverter 84 whose output is connected to one end of the channel of FET T4, the other end of which serves as an input to inverter 85, whose output is connected to stage DC 2 and which serves as one input to NOR circuit 62. The other end of the channel of FET T5 is connected as an input to NOR circuit 87. The output of stage DC7 serves as the other input to NOR circuit 62 and also serves as an input to AND circuits 63 as does the output of inverter 85 which is the output of stage DC1. The output of NOR circuit 62 serves as one input to NOR circuit 61 and the output of AND circuit 63 serves as the other input to NOR circuit 61 whose output is connected to the other side of the channel of T6. The gate of FET T5 is connected to line 31 which is connected to one end of the channel of FET T8. The gate of FET T6 is connected to one end of the channel of FET T7. The output from each of stages DC2 through DC6 are applied directly as additional inputs to NOR circuit 87 with the output from stage DC7 being inverted and then applied as an input to NOR circuit 87. The output of NOR circuit 87 serves as an input to NOR circuit 88 whose other input is simply a power up control pulse from the system.

The output of NOR circuit 88 is inverted through inverter 89, the output of which is connected to one end of the channel of FET T9 whose gate is activated by pulse .phi.A and the other end of whose channel is inverted and applied to the gate of FET T7, the other end of whose channel is connected to the source of pulse .phi.B. The other end of the channel of FET T9 is also inverted and connected to one end of the channel of FET T11 and inverted once more and connected to the gate of FET T8. The other end of the channel of T8 is connected to the source of pulse .phi.B. The other end of the channel of FET T11 is connected to the gate of FET T12 and is also inverted and applied to the gate of FET T13. The one end of the channel of FET T12 is connected to line 33b and the other end is connected to the source of pulse .phi.A. One end of the channel of FET T13 is also connected to the source of .phi.A and the other end is connected to line 33a. Down counter 16 is a well known "psuedo-random" counter. The operation of this counter is also well known, and in this particular application the number of microseconds of the period of a particular segment is entered into the counter which then begins to decrement in one microsecond decrements. When counter 16 reaches "0", a signal is sent out on lines 31, 20a and 20b from FET T8 at time .phi.B, on line 27 from FET T13 at time .phi.A, and on lines 33a and 33b from FET's T13 and T12, respectively, at time .phi.A.

Segment counter 17 is an ordinary counter having an input from down counter 16 on output 20 (lines 20a and 20b) as mentioned above so that each time down counter 16 reaches 0, a pulse is sent over line 20a at time .phi.B and over line 20b at time .phi.A to segment counter 17. Line 20a is connected to the gates of FET's T15, T16, T17, and T18. Line 20b is connected to the gates of FET's T21, T22, T23 and T24. NOR circuits 116, 117, 118 and 119 each have one input connected to the source of a system pulse for presetting the counter. The other input to NOR circuits 116 and 117 is through inverters 121 and 122, respectively, each of which is connected to the one end of the channel of FET's T21 and T22, respectively. The other input to NOR circuits 118 and 119 are connected to the one end of the channels of FET's T23 and T24, respectively. The output of NOR circuit 119 serves as the input to AND circuit 106 and is also connected to one end of the channel of FET T18. The output of NOR circuit 118 is connected as an input to NOR circuit 113 and as an input to AND circuit 106. The output of NOR circuit 117 is inverted through inverter 115 whose output is connected as an input to NOR circuit 112 and as an input to AND circuit 105. The output of NOR circuit 116 is inverted through inverter 114 whose output is connected as an input to NOR circuit 111 and as an input to AND circuit 104. The output of NOR circuit 113 is connected as an input to NOR circuit 103 and is also inverted through inverter 108 and applied as an input to AND circuit 105. The output of AND circuit 106 is applied as an input to NOR circuit 103 whose output is connected to one end of the channel of FET T17. The output of NOR circuit 112 and the output of AND circuit 105 serve as the inputs to NOR circuit 102 whose output is connected to one end of the channel of FET T16. The output of NOR circuit 112 also is inverted through inverter 107 and applied to AND circuit 104 as an input. The output of NOR circuit 111 and of AND circuit 104 serve as inputs to NOR circuit 101 whose output is connected to one end of the channel of FET T15.

The other end of the channel of FET T18 is connected as an input to inverter 130 whose output is inverted through inverter 131, and also connected to the one end of the channel of FET T28 whose gate is activated by pulse .phi.A and whose other channel is connected in parallel with the output of inverter 131 to line 26a which is one output from segment counter 17. The other end of the channel of FET T17 is connected to one end of the channel of FET T27 whose gate is activated by pulse .phi.A, and to inverter 128 whose output is inverted through inverter 129, the output of which is connected to the other end of the channel of FET T27 to output line 26b. The other end of the channels of FET's T15 and T16 are connected in a like manner to supply outputs on output lines 26c and 26d. Output line 26d is connected to one end of the channel of FET T29 whose gate is activated by pulse .phi.A and the other end of whose channel is inverted through inverter 132 and connected to one end of the channel of FET T31 whose gate is activated by pulse .phi.B. The other end of the channel of FET T31 is inverted through inverter 133 whose output is connected to line 32.

Segment counter 17 is a typical counter which, in this preferred embodiment, is capable of counting from 0 through 15, for a total count of 16.

Amplitude adjust 18 of FIG. 1 which receives outputs L0, L1, and L2 from stages 45, 46 and 47 of amplitude register 12 provides a voltage reference amplitude to wave generator 19 and is not important to this invention. Therefore, no description of amplitude adjust 18 is made herein. It is a weighted, series resistive attenuation circuit, well known in the art.

Wave generator 19 of FIG. 1 is comprised of counter to segment decoder 140 of FIG. 2d, inverter switches S1 through S7, capacitors CA through CG and clocked ground biased node 150. Counter to segment decoder 140 is connected to output 32 from segment counter 17 and also to output 33a and 33b from down counter 16. Stages of counter segment decoder 140 are connected, respectively, to switches S1, S2, S3, S4, S5, S6 and S7, the output of which are connected respectively to one terminal of capacitors CA, CB, CC, CD, CE, CF and CG, the other terminals of which are connected together on line 148 to one end of the channel of FET T32, the other end of which provides the output of the wave generator and is connected to clocked ground biased node 150. The gate of FET T32 is activated by an inverted signal on the DIS line.

Counter segment decoder 140 is a simple shift register which, when activated by a pulse, stores a "1" until another pulse is received at which time the first "1" is shifted and a second "1" is also stored, continuing in this fashion until completely filled with "1's". This type of register is also referred to as a "Jones" counter.

Referring now to FIG. 3, the first stage of counter segment decoder 140 together with switch S1 is illustrated schematically. A DIS input is connected to the gate of FET T33, one side of whose channel is grounded, the other side being connected to output 32 from segment counter 17. Output line 32 is connected to one end of the channel of FET T34, the other end of which is inverted through inverter 141 and again through 142 and connected to the gate of FET T40 of switch S1. The other end of the channel of FET T34 is also connected to one end of the channel of FET T35 whose gate is activated by pulse .phi.B, the other end of whose channel is connected to the gate of FET T40. Output line 33a from down counter 16 is connected to the gate of FET's T34 and T37. Output line 33b from down counter 16 is connected to the gate of FET T36. One end of the channel of FET T36 is connected to the gate of FET T40 and the other end is inverted through inverter 143 and again through 144 and connected to one end of the channel of FET T37. The other end of the channel of FET T37 is inverted through inverters 145 and 146 and is also connected to one end of the channel of FET T42 whose other end is connected to the output of inverter 146 which is then connected to switch S2.

One end of the channel of FET T40 of switch S1 is connected to ground and the other end is connected to the one end of the channel of FET T38 and also to the gate of FET T39. The other end of the channel of FET T38 is connected to a source of voltage and to its gate. One end of the channel of FET T39 is connected to a reference voltage, setting the maximum amplitude of the output sine wave. The other end of the channel of FET T39 is connected to one plate of capacitor CA and to one end of the channel of FET T41, the other end of which is grounded. The other plate of capacitor CA is connected to line 148. The remaining stages of counter-to-segment decoder 140 are identical to that described above as are the remaining switches S2 through S7 to switch S1.

FIG. 4 is a schematic diagram of the blocked ground biased node 150 of FIG. 2. The circuit is used simply to prevent a DC component from building up and thereby shifting the output waveform. The output line which carries the output waveform is connected to one side of the channel of FET T50 whose other side is connected to one plate of capacitor C1 whose other plate is connected to ground. The other side of the channel of FET T50 is also connected to one side of the channel of FET T51, the other side of which is connected to ground. FET's T50 and T51 are used for charging capacitor C1 and discharging it, respectively. The gate of FET T50 is connected to one end of the channel of FET T54 and the gate of FET T51 is connected to one end of the channel of the FET T52. The other ends of the channels of FET's T52 and T54 are connected to a voltage source. The gate of FET T52 is enabled by pulse .phi.B and the gate of FET T54 is enabled by pulse .phi.A. FET T56 has one end of its channel connected to the channel of FET T57 and to the gates of FET's T57, T55 and T53. The other end of the channel of FET T56 is connected to its gate and to ground. The other end of the channel of FET T57 is connected to another voltage source. One end of the channel of FET T55 is connected to the gate of FET T50 and one end of the channel of FET T53 is connected to the gate of FET T50 and one end of the channel of FET T53 is connected to the gate of FET T51. The other ends of the channels of FET's T53 and T55 are connected together to the other voltage source.

FET's T53, T55, T56 and T57 are used for biasing of this circuit so that a reference is established at the gates of FET's T50 and T51 so that those FETs are turned completely on and off.

As indicated above, pulses .phi.A and .phi.B are non-overlapping. When FET T54 is turned on by .phi.A, FET T50 is turned on. The output is connected to the capacitors CA through CG and when FET T50 is turned on, some of the charge from those capacitors charges small capacitor C1. Then FET T52 is turned on by pulse .phi.B, after FET T54 has been turned off. When T52 is turned on, FET T51 is also turned on, thus discharging capacitor C1 to ground. These two FET's T50 and T51 form switches with capacitor C1 between them. The circuit then simulates an RC network. The two switches, FET's T50 and T51, together with capacitor C1, may be considered as an equivalent resistance of high and precise value. This type of network therefore isolates the AC components from ground, but keeps the DC level at ground. In this way, the output waveform is centered around ground as a reference and remains centered around ground.

The capacitors CA through CG of the waveform generator 19 of FIG. 1 are selected to provide predetermined points on the desired output waveform. In this preferred embodiment, a total of 16 segments makes up one cycle of the output sine wave. Therefore, there are eight steps from the highest positive value from ground to the highest negative value from ground. Going from the highest negative value to the highest positive value is a mirror image of the aforementioned eight steps. A total of only seven capacitors is therefore necessary. The steps on the output sine wave are calculated on the basis of area. The basic integral for area is expressed as: ##EQU1## For the specific waveform, sin.omega.t, equal x increments dictate that T = (.pi./2-0)/4 = .pi./8 rad or 221/2.degree..

On the basis of a 221/2.degree. spacing: ##EQU2##

Using the same calculation technique, ##EQU3##

Having determined these values of areas for the stages forming the sine wave, the values of capacitors CA through CG may be determined. The first step

Assume a convenient value of capacitance of 1.0 pf for capacitor CA to cause .DELTA.1 = 0.14835. This value is selected because of manufacturing and size restraints, and for impedance matching to the next stage. Then the capacitance values can all be proportioned based on CA = 1.0 pf and .DELTA. = 0.14835. ##EQU4##

Referring to FIG. 3, when there is a "1" present in stage one of the counter-to-segment decoder 140 and when S1 is activated, capacitor CA discharges causing .DELTA.1 which provides the first step down on the generated wave. Similarly, when there is a "1" in stage two of the counter-to-segment decoder 140, capacitor C2 discharges providing .DELTA.2. The counter-to-segment decoder 140 is loaded sequentially with "1's" and "0's" as follows:

FIG. 5 illustrates the synthesized sine wave showing the 16 segments forming a space, followed by a shift from space to mark illustrating, in exaggerated form, a lower frequency corresponding to a mark.

As an example to illustrate the operation of the wave generator, assume that the mark frequency is 1070 Hz and that the space frequency is 1270 Hz. The respective total waveform periods are: ##EQU5## As set out earlier:

In the case of the mark, to calculate A: ##EQU6##

Empirically, let x = 9 and y = 7

Substituting in equation (1) above,

Calculating in the same fashion for space,

Empirically, let x = 13 and y = 3.

Then, substituting in equation (1),

From the above calculations, it is apparent that by having segments of two different periods to form a waveform, the period of the waveform can be very accurately synthesized, thereby forming a highly accurate output frequency. It should be understood that other pairs of frequencies are required to be generated by this type of waveform generator. For example, 1180 Hz and 980 Hz, 1850 Hz and 1650 Hz, 2025 Hz and 2225 Hz. In all cases, the segment periods are determined in exactly the same fashion as described above for 1070 Hz and 1270 Hz.

The A and B period information for all of the pairs of frequencies that will be required are stored in the logic array 40. Although corresponding segment periods differ, the amplitudes do not. For example, segment 4 of a space signal at 1270 Hz is 49 or 50 microseconds. Segment 4 of the corresponding mark frequency of 1970 Hz is 58 or 59 microseconds. For a space frequency of 1850 Hz, the segment 4 period is 34 or 35 microseconds. The period of segment 4 for the corresponding mark frequency of 1650 Hz is 38 or 39 microseconds. Very important is the fact that for each of these number 4 segments, the amplitude is exactly the same, assuming that the same reference voltage is applied to the waveform generator. This feature is very important when frequencies are shifted. Also, because of commonality between the segments with respect to mirror images and identify of amplitude, it is possible and practical in logic array 40 to use a programmable logic array 42 which permits some logic manipulation, thereby reducing the total number of components required for storage.

Referring now to FIGS. 2 and 5, assume first that the frequency pair selected is 1270 Hz for space and 1070 for mark. Further, assume that a digital "0" is applied on line 24, signifying a space. If this is the first signal entry after having applied power to the modem, then it can be assumed that the output from the segment counter is zero and that zeros are on all of lines 26a-26d. Those four outputs to stages 53-56 of address latch 14 determine that segment 1 is addressed. Outputs 25a-25c from frequency register 13 are applied to stages 58-60 of address latch 14 to select the frequency pair of 1270-1070 Hz. Finally, line 24 is an input to stage 57 of address latch 14 to establish that the input binary signal is a space as indicated in FIG. 5. Address latch 14 provides inputs 28a-28h with segment number, space signal and frequency pair information so that the appropriate segment period designation is transmitted from logic array 40 on lines 29a-29h to down counter 16. The number 49, in this instance, is entered into down counter 16. The clock input of one MHz to down counter 16 causes down counter 16 to count down in one microsecond intervals. During the time that the counting is being carried on, segment counter 17 remains in its original preset state and the appropriate combination of switches S1-S4 are activated, as shown in the preceding chart, together with the first four stages of counter-to-segment decoder 140, with capacitors CA-CD thereby being included. The appropriate voltage output level then is output on line 48 through FET T32, with the DC ground being kept constant by the clock ground biased node 150.

When down counter 16 reaches 0, segment counter 17 is activated by pulses on lines 38a and 33b to increment by 1. Such incrementing provides new information on lines 26a-26d, thereby providing a changed address in stages 53-56 of address latch 14. This results in segment number 2 period information in the form of a binary word being transmitted into down counter 16. Thus, segment 2 would be presented at the output with a voltage level dependent upon the combination of switches S1-S5, stages 1-5 and capacitors CA-CE.

Segment counting then would continue until point M on FIG. 5 when the input information on line 24 changes from a "space" to a "mark". On FIG. 5, it is seen that the change occurs at approximately the midpoint of segment 2 of the second space waveform. No change occurs in the output of logic array 40 at that time. However, at the end of that particular segment 2, the new segment 3 address is presented to address latch 14, together with the new binary information input. The new binary information input signifying a mark, together with the frequency pair information and the address information results in a different segment 3 from that ordinarily following in the space mode. It should be understood that the time for response to such a change may be as described, or may be one later, depending upon the number of stages and types of hardware implementation. It is important to understand that, in any event, there is no change in the sequence of segments.

As described, segment number 3 period of 58 microseconds is loaded into down counter 16. Down counter 16 then counts down until it gets to 0 and the cycle is repeated with segment number 4 being next selected. The segments, as discussed above are in periods of 58 and 59 microseconds. Nine of the 58 microsecond segments have interspersed strategically between them seven of the segments having 59 microsecond periods. Likewise, in the mark case, thirteen of the segments have periods of 49 microseconds having three segments of 50 microseconds strategically interleaved therewith to provide a smooth sine wave output.

The output waveform is almost totally free of harmonics and noise as a result of the careful frequency generation and the lack of noise when shifting from one frequency to another.

The particular invention involved herein employs MOS transistors. It is contemplated that other type field effect transistors and bilateral transistors could be employed. Also, different types of ROM's and PLA's could be used and certainly other types of registers, counters and logic configurations. These deviations are contemplated and do not depart from the scope of this invention.