Drain Extensions for Closed COS/MOS Logic Devices

In the Drawings:

FIG. 1 is a top view of a portion of a COS/MOS integrated circuit of the type employing a closed structure and including the present invention;

FIG. 2 is a cross-section of the portion of the COS/MOS integrated circuit of FIG. 1 taken along the lines 2--2 of FIG. 1;

FIG. 3 is a cross-section of the portion of the COS/MOS integrated circuit of FIG. 1 taken along the lines 3--3 of FIG. 1; and

FIG. 4 is a cross-section of the portion of the COS/MOS integrated circuit of FIG. 1 taken along the lines 4--4 of FIG. 1.

Referring to FIGS. 1-4, a portion 10 of a COS/MOS integrated circuit device of the type which employs closed gate geometry insulated gate field effect transistors (IGFETs) 12, 14 and 16 is shown. The three IGFETs 12, 14 and 16 are N-channel devices. The IGFETs 12, 14 and 16 are formed in a P well 48 formed in the N- substrate 50. The transistor 12 has a closed gate geometry gate 18, transistor 14 has a closed geometry gate 20, and transistor 16 has a closed geometry gate 22. The region 24 which surrounds the gates 18 and 20 is an N+ source plane which extends from the surface of the portion 10 down into the P well 48. The N+ source plane 24 provides a common source for transistors 12 and 14. Transistor 16 is formed with its gate 22 completely surrounded by the gate 20 of transistor 14. A region 26 serves as the drain of the transistor 12, a region 28 serves as the drain of the transistor 14 and a region 30 serves as the drain of transistor 16. The region 28 also serves as the source of transistor 16 which is formed concentric with transistor 14. In accordance with the present invention the drain region 26 of transistor 12 has a highly doped portion 32 which is surrounded by a lightly doped portion 34. The highly doped portion 32 is used to facilitate making contacts to the drain region 26. A portion is considered highly doped if its sheet resistance is less than about 50 ohms/square.

A lightly doped portion is comprised of an N-region having a resistivity of about 1000 ohms/square or greater. Since the distance between the edge of the polycrystalline gate 18 and the highly doped N+ portion 32 is relatively small, the resistance developed across the high resistance lightly doped portion 34 is not high enough to significantly affect the operation of the transistor 12. However, the utilization of the lightly doped portion 34 enables the voltage rating of the transistor to be increased from 13 volts to about 20 volts.

The structure comprising the two concentric IGFETs 14, 16 which will be used in such circuits as transmission gates and certain functional gates presents a problem in that the entire drain region 28 of the transistor 14 (also the source of transistor 16) cannot be lightly doped. If the region 28 were completely lightly doped with N- conductivity, only those areas of the outer IGFET 14 immediately adjacent to the contacts 36, 38 would be effective in supplying the high resistance of the remaining N- diffusion which effectively isolates the remaining portions of the IGFET.

In order to provide drain extensions for concentric transistor structures, such as those used in IGFETs 14, 16, it is adequate if the drain extension N-regions surround the contacts 36, 38. The series resistance to the contacts provides a ballast which limits current surges into the contact region. Accordingly, where two contacts are used in the common source-drain region 28 they should each be surrounded by an N- region 40, 42 respectively. The other portions 44, 46 of the common source-drain 28 are highly doped N+ regions in order to allow current to flow through the entire active areas of the source-drain region 28.

In order to manufacture the integrated circuit 10 one starts with a lightly doped substrate 50 of N-conductivity type. Using a first photomask (not shown), a P well 48 is defined and acceptor impurities are introduced into the P well 48 by any suitable means, such as by diffusing or ion implantation. Thereafter, an oxide is grown over the surface of the substrate and a conductive layer is formed on the surface of the oxide to act as the gates of the various devices. The conductive layer is preferably a polycrystalline silicon layer which may be deposited by any well known method. Then, the polycrystalline silicon gates and the underlying oxide layers are defined using a second photomask, and the remaining portions of the polycrystalline silicon and oxide layers are removed exposing the surface of the substrate 50. Using additional photomasks and standard photolithographic techniques, the N-, N+, P- and P+ regions which comprise the drain extensions, ohmic contacts and source planes are defined. Impurities are introduced into the substrate by the techniques of diffusion and/or ion implantation. In particular, it has been found that to be beneficial to use the various gates as masks and to ion implant impurities into the surface of the substrate thereby assuring that the gates are properly aligned with the sources and drains while allowing the gates to become conductive as a result of the ion implantation into the polycrystalline silicon. In view of the fact that the techniques of photolithography, diffusion and ion implantation are already well known in the art, further explanation herein is not required.

Another important application of the present invention which is illustrated by the contacts 36, 38 in the common source-drain region 28 is that the source-drain region may be used as a "tunnel" in order that a low resistance path be provided through the source-drain region 28 between the contacts 36, 38.