Floppy Disc Data Separator for Use With Single Density Encoding

This invention relates to detection of single density encoded data, and more particularly to utilizing a phased lock loop circuit for data separating wherein the rate of data flow might be susceptible to substantial variations.

The subject invention is designed for efficient and easy data separation of a data signal from a storage medium such as a floppy disc. It is particularly adapted for separating "single density encoded" data, wherein a single data bit is encoded between successive clock pulses. This data scheme is a prevalent scheme for encoding data on floppy discs. While other arrangements have been utilized, such as schemes having the clocks and data condensed, and higher density encoding is possible, this arrangement presents a favorable compromise, or trade-off, of various system considerations. The single density encoding arrangement enables relatively simple circuitry for use in conjunction with the floppy disc. However, in the prior art this arrangement has been vulnerable to system performance variations, and in particular variations in the speed of the motor that drives the floppy disc. In short, if the motor drive of the floppy disc experiences speed changes, there are resulting time variations in the data flow from the floppy disc pickup, resulting time variations must be accounted for in the data separating circuitry. A typical conventional separator circuit comprises a series of monostable multivibrators which are sensitive to the timing of the received signals, and which require adjustment when and if there occur variations in the rate of data flow from the floppy disc pickup. Such prior art separator systems, because they are sensitive to the timing, make it difficult to achieve the degree of reliability that is required for the overall system.

It is an object of this invention to provide a data separator for separating the data from a single density encoded signal, which separator circuit is simple and reliable, and relatively immune to variations in the rate of the data signal being operated upon.

It is another object of this invention to provide a circuit for separating data from a single density encoded signal, comprising a phase lock loop circuit in combination with logic circuitry to provide a separator circuit which automatically adjusts to maintain proper alignment when variations occur in the rate of the encoded signal.

It is another object of this invention to provide a data separating circuit for use in conjunction with a floppy disc type storage device, the separator circuit being designed to receive signals from the storage device and to separate the encoded data from the clock pulses, the separator circuit being relatively insensitive to variations in the rate of the signal caused by system variations such as changes in the speed of the floppy disc drive.

It is a further object of this invention to provide a data separator for separating data from a signal containing periodic clock pulses and encoded data, which data separator is simple, reliable and is adaptive to remain time synchronized with the clock pulses in the signal.

In accordance with the above objectives, there is provided a circuit for separating data from an encoded signal, and in particular a single density encoded signal, comprising a circuit for tracking or following the timing of the clock pulses in such signal, and further circuit means for generating a data window which is maintained in time coincidence with the occurrence of the encoded data and not in time coincidence with the occurrence of the clock signals, and gating means utilizing the data window to gate only the encoded data, thereby separating the encoded data from the clock pulses in the signal. In the preferred embodiment, the data separator utilizes a phase lock loop circuit and accompanying logic circuitry to track any variations in the rate of the clock signals, thereby continuously maintaining the proper time relationship, or alignment, between the data window and the encoded data, thereby ensuring proper data separation independently of variations in the rate of the encoded signal.

FIG. 1 is a circuit diagram of the data separator of this invention.

FIG. 2 comprises a plurality of waveform diagrams illustrating signal levels at specified points of the circuit of FIG. 1.

Referring now to FIG. 1, there is shown a circuit diagram of the data separator of this invention. The circuit has two inputs, labeled CLOCK & DATA and LOCK respectively. There are two output terminals, labeled SEPARATED DATA and SEPARATED CLOCK respectively. The CLOCK & DATA waveform is illustrated on the CLOCK & DATA line, FIG. 2, it being seen that the single density encoded waveform has alternating clock and data signals. The CLOCK & DATA signal is provided from the read head of a floppy disc, not shown, and is connected to the circuit of this invention after desirable amplification and other processing. As seen in the CLOCK & DATA line of FIG. 2, the clock signal is a periodic high level pulse, and the data signal is either in the form of a high level pulse representing a 1 or the absence of a pulse representing a 0, the data signal occurring nominally midway between successive clock signals.

The CLOCK & DATA signal is inputted into a first input terminal of AND gate 25. The second input to gate 25 represents the DATA WINDOW signal, which is generated as described hereinbelow. The CLOCK & DATA signal is also inputted to a first input terminal of AND gate 35, which gate has a second terminal to which is connected the DATA WINDOW signal. As seen in FIG. 2, the dashed lines break up the clock plus data signal, timewise, into successive equal portions which correspond to the DATA WINDOW and the DATA WINDOW respectively. The DATA WINDOW is centered about the time when the data signal is scheduled to appear, and the DATA WINDOW is centered about the clock pulses, as is seen from the DATA WINDOW and DATA WINDOW waveforms.

The output of gate 25, which is defined as being the separated clock signal, is inputted as IN 2 to phase locked loop circuit 27. Phase locked loop circuit 27 is suitably provided by Motorola Integrated Circuit MC 14046B. A second input to phase locked loop circuit 27, IN 1, is taken from the Q output of FF 1, and represents a squarewave having its rising edge aligned with the leading edge of the input clock signal, as seen in FIG. 2. The output of circuit 27, designated OSC. OUT, is a periodic signal at about twice the frequency of the clock pulse, with the rising edge of the OSC. OUT signal being aligned with the rising edge of the clock pulses. The OSC. OUT signal is inputted to the clock input of FF 1, which is a conventional D-type flip-flop connected to act as a divide-by-two circuit. Additionally, the OSC. OUT signal is inverted through inverter 33 and connected to the clock input terminal of FF 2, which is likewise a D-type flip-flop utilized to perform the divide-by-two function. The Q output of FF 2, which is the data window signal, is connected to gate 35 as described above, to gate through only the data component of the CLOCK & DATA signal, while the Q output of FF 2, which is the DATA WINDOW signal, is connected to an input of gate 25 to gate only the clock signal through to phase locked loop circuit 27.

The lock signal, which represents the beginning of a floppy disc sector, is connected to the rest terminal of FF 2. In conventional operation of floppy discs, a first plurality of the data positions of a new sector are filled with 0's, and the lock signal is generated, suitably with a monostable flip-flop, to be high for about 25% of the "zeros" time. The high lock signal causes FF 2 to reset at the beginning of the sector, thereby causing all data to be interpreted as clock signals for the duration of the reset period. Note that when FF 2 is reset, Q is high and Q is low, so that the DATA WINDOW line remains high and all signals entered at the CLOCK & DATA input terminal are passed through on the IN 2 line. This causes the timing of the circuit to be referenced to clock signals, establishing the relationships shown in the waveforms of FIG. 2. Note that during this period the Q terminal of FF 2 is low, such that nothing gets gated through gate 35, and no signal appears at the SEPARATED DATA terminal.

In operation, when a high signal, or pulse is gated through gate 25, it is inputted to phase locked loop circuit 27. Circuit 27 contains a comparator which compares signals IN 1 and IN 2, and produces a tristated output, i.e., high, low, or free. The output of the comparator is connected through a low pass filter to a VCO circuit which normally produces a pulse signal. If the output from the comparator is "high", the output frequency (OSC. OUT) increases; if "low", OSC. OUT decreases; and if "free", OSC. OUT remains unchanged. The time relationship of the clock pulses with the IN 1 signal causes edge alignment of the clock signals and the OSC. OUT signals, which alignment in turn fixes the relationship of the DATA WINDOW signal relative to the clock pulses. The OSC. OUT is the clock input to FF 1, causing FF 1 to change state when OSC. OUT goes high. When the OSC. OUT signal goes low, the clock signal to FF 2, which has been inverted, goes high, causing FF 2 to change state. When this happens, the DATA WINDOW signal, at the Q output of FF 2, and the DATA WINDOW at the Q terminal of FF 2, change state. These conditions hold for a full cycle of the OSC. OUT waveform, at which time FF 1 is again switched. A low level signal connected to the D input terminal of FF 2, combined with a positive transition of the OSC. OUT signal changes the DATA WINDOW signal to a low level and the DATA WINDOW signal to a high level. The procedure is repeated, and as seen from the waveform of FIG. 2, the leading edge of the IN 1 signal being aligned with the leading edge of each clock pulse. The data window is centered about the occurrence of the data signal, while the DATA WINDOW signal is centered about the clock pulses. Changes in the rate of the CLOCK & DATA signal are tracked by circuit 27, causing a corresponding adjustment of the timing of the DATA WINDOW. Thus, the phase locked loop circuit optimally positions the DATA WINDOW with respect to the CLOCK & DATA pulses. The DATA WINDOW is always maintained centered between the clock pulses, and accordingly the system is not vulnerable to variations in the performance of the drive motor which drives the floppy disc. The circuit thus renders the overall floppy disc system tolerant of wide variations in disc drive rotary motor speed.

It will be understood that a preferred embodiment of the invention has been shown and described and various modifications may be made which fall within the true spirit and scope of the invention as set forth in the appended claims. For example, the separator circuit may be arranged to act upon a CLOCK & DATA signal wherein the pulses are negative going, i.e., the signal is normally high and goes low at the time of a clock or data pulse. In such case, negative logic is employed, gates 25 and 35 being NOR gates instead of AND gates. The signal from the Q terminal of FF 2 is DATA WINDOW and the signal from the Q terminal of FF 2 is DATA WINDOW, such that DATA WINDOW is periodically high coincident with the data in the signal and periodically low coincident with the clock pulses.