Thermal Recording Head and Drive Circuit

The present invention relates to a recording apparatus and more particularly to a thermal recording apparatus.

Recently, facsimiles, printers and the like have employed as recording means a thermal recording apparatus for recording information on a heat sensitive paper by using a recording head with a number of heating resistors serially arranged.

In such a recording apparatus, several hundreds to one thousand recording units are arranged in a row, so that connection between the recording units and its drive circuit is considerably complicated. For simplification of the complicated connection, a diode matrix circuit as shown in FIG. 1 is used to successfully reduce the connecting portions. As shown, a plurality of unit recording blocks UB.sub.1, UB.sub.2, UB.sub.3, . . . are serially arranged in a given direction. Each recording unit includes n recording units successively arranged in the block arrangement direction each of which further includes a heating resistor R and a diode D with the polarity as shown these being connected in series. The recording units of n are connected collectively at one ends to a selection terminal of the corresponding unit recording block. For example, one ends of the recording units of the first unit recording block UB.sub.1, i.e. one ends of the heating resistors R.sub.11 to R.sub.1n, are connected to a selection terminal C.sub.1 ; one ends of the recording units of the second unit recording block UB.sub.2, i.e. one ends of the heating resistors R.sub.21 to R.sub.2n to a selection terminal C.sub.2 ; likewise, one ends of the heating resistors R.sub.21 to R.sub.2n to a selection terminal C.sub.3. Recording signal feeding lines L.sub.1 to L.sub.n are correspondingly connected to the cathodes of the diodes of each unit recording block, as shown in FIG. 1. These cathodes form the other ends of the first to nth recording units of each unit recording block. A drive circuit (not shown) is connected at the recording signal feeding terminals to the lines L.sub.1 to L.sub.n and the unit recording block selection terminals to the corresponding selection terminals C.sub.1 to C.sub.n of the recording unit blocks. In this connection scheme, number of connection lines connecting heating resistors to diode matrices equals to that of all the heating resistors, however. The connection scheme still suffers from complex connection work. Directed to overcome this problem, another method was developed in which the respective ends of a flexible cable with parallel conductors densely printed thereon are pressured onto the other ends of the heating resistors and a substrate on which the diodes matrices circuit is printed and the diodes are mounted. However, this method provides another new problem of bulkiness of the recording head, being still accompanied by the above-mentioned problem of complex connection work.

A multilayer printing method by using thick film technology was developed to solve such the complexity of the connection, see FIG. 2. In this method, diodes are mounted on an insulating substrate 1 and the matrices wiring associated with the diodes are printed thereon by using the multi-layer wiring method. In the figure, only the multi-layered wiring is depicted. First conductors 1.sub.11 to 1.sub.1n, 1.sub.21 to 1.sub.2n, . . . are connected to the diodes D.sub.11 to D.sub.1n, D.sub.21 to D.sub.2n, . . . , respectively, and these conductors are printed with the same interval as of the heating resistors. The conductor density is 4 lines per mm to 6 lines per mm so that the interval P.sub.1 of the first conductors is 167 to 250.mu.m. The terminals 2 of the first conductors belonging to a unit recording block are disposed aligning with a dotted line 3 slanted. Insulating layers 4 are printed so as to cover these lines 3. Second conductors (recording signal feeding lines) L.sub.1 to L.sub.n are printed on these insulating layers 4. Each of these second conductors is disposed normal to the corresponding conductor (with the same line order as of the first conductor) of each unit recording block at the terminal 2 of the first conductor. At these cross points, holes 5 are formed to the insulating layer 4. By inserting a conductor into each of these holes 5, the first conductors with the same order of the conductor disposition of the respective unit recording blocks are connected commonly to a single second conductor with the corresponding disposition order.

To ensure the connection of the first conductors with the second conductors, the diameter of each hole 5 must be larger than the width of the first conductor. Therefore, there is a possibility that the periphery of the hole 5 comes in contact with the first conductor neighbouring with the hole 5. The experiment conducted by the inventors of the present application showed that, when the interval P.sub.1 between adjacent first conductors is less than 200.mu.m, the contact accidents take place very frequently, reducing the yield of the recording head manufacturing. Further, to reduce the contact accidents, the interval P.sub.1 must be at least 300.mu.m. As previously stated, the interval P.sub.1 is 167 to 250.mu.m and therefore, in order to secure more than 300.mu.m of the interval P.sub.1, the intervals of the first conductors must be widened midway between the extremes of interval. Adversely, the widening of the intervals lead to bulkiness of the recording head, however.

As seen from the foregoing, the conventional techniques are troubled with a contradiction that the miniaturization of the recording head reduces the yield of its manufacturing while improvement of the yield brings about bulkiness of the recording head.

Accordingly, the primary object of the present invention is to provide a recording apparatus of which the recording head may be made small in size and with improved yields.

According to the present invention, there is provided a recording apparatus comprising a recording head including a plurality of main blocks arranged in a given direction each main block having first and second unit recording blocks arranged in the given direction each unit recording block further including n recording units each recording unit further including a series-connected diode and recording element pair, a plurality of unit recording block selection terminals each of which is connected to one ends of the n recording units, a plurality of first conductors for connecting the other ends of the ith (n.gtoreq.i.gtoreq.1) recording units of the first unit recording block with the other ends of the (n+1-i)th recording units of the second unit recording block, and a plurality of second conductors for connecting commonly the corresponding first conductors among the main blocks and for supplying signals to be recorded to the recording units; and a drive circuit including first means for selecting a desired one of the unit recording blocks and second means for supplying recording signals in the order of the recording units arrangement to the recording units of the selected unit recording block.

Other objects and features of the invention will be apparent from the following description taken in connection with the accompanying drawings, in which:

FIG. 1 shows a wiring diagram of a recording head of a conventional recording apparatus;

FIG. 2 is an enlarged view of a part of the connection scheme of the recording head shown in FIG. 1;

FIG. 3 is a wiring diagram of a recording head of a recording apparatus according to the present invention;

FIG. 4 is an enlarged view of a part of the connection scheme of the FIG. 3 recording head;

FIG. 5 is a plan view of a modification of the FIG. 4 wiring scheme shown in FIG. 4;

FIG. 6 is a perspective view of an enlarged view of a part of the FIG. 5 connection scheme;

FIG. 7 is circuit diagram illustrating one form of the connection schemes of the recording head shown in FIG. 3 with a drive circuit for it, in which number of the recording units in each unit recording block is 7;

FIG. 8 is a circuit diagram illustrating the details of a part of the FIG. 7 circuit;

FIG. 9 is a set of timing charts for illustrating the operation of the FIG. 7 circuit;

FIG. 10 is a modification of the drive circuit of FIG. 7; and

FIG. 11 is another modification of the drive circuit of FIG. 7.

In the following figures, the same parts are denoted by the same reference numbers as those of FIGS. 1 and 2.

As shown in FIG. 3, main blocks MB.sub.1 and MB.sub.2 are arranged successively to the right as viewed in the drawing. The main block MB.sub.1 includes first and second unit recording blocks UB.sub.1 and UB.sub.2 disposed in consecutive order to the right as viewed in the drawing. This is correspondingly applied to the other main blocks MB.sub.2 and MB.sub.3. A heating resistor, for example, R.sub.11 and a diode, for example, D.sub.11 are connected in series and these constitute a recording unit. Each of the recording blocks includes n recording units arranged in series order as in the same direction as of the respective unit recording blocks UB.sub.1 and UB.sub.2 disposition. One ends of the n recording units of each unit recording blocks are connected a selection terminal C.sub.1, C.sub.2, . . . of each unit recording block. In each main block, the other end of the ith (n.gtoreq.i.gtoreq.1) recording unit of the first unit recording block, for example, UB.sub.1 and the other end of the (n+ 1-i)th recording unit of the second unit recording block are connected by a first conductor. In the figure, the first portion of the first conductor includes conductors 1.sub.11 and 1.sub.2n and the second portion thereof is illustrated including a conductor connecting the free ends of the conductors 1.sub.11 and 1.sub.2n. The corresponding second portions of the first conductors in the respective main blocks MB.sub.1, MB.sub.2, . . . are connected to recording signal feeding lines L.sub.1, L.sub.2, . . . L.sub.n. The diode may be inserted between a recording element and a unit recording block selection terminal.

FIG. 4 shows a plan view of the matrix wiring portion of the recording head shown in FIG. 3 when it is fabricated by the thick multi-layer printing method. On an insulating substrate 11, recording elements R.sub.11 to R.sub.1n, R.sub.21 to R.sub.2n, . . . and diodes D.sub.11 to D.sub.1n, D.sub.21 to D.sub.2n, . . . (not shown) are provided and the first portion 1.sub.11 to 1.sub.1n, 1.sub.21 to 1.sub.2n, . . . of the first conductor which are connected to respective cathodes of diodes D.sub.11 to D.sub.1n, D.sub.21 to D.sub.2n, . . . , are formed thereon by means of the thick film printing technology. The first portion, i.e. conductors 1.sub.11 to 1.sub.1n, 1.sub.21 to 1.sub.2n, . . . , are disposed in parallel and the interval P.sub.1 therebetween are selected 167 to 250.mu.m (the interval density 4 lines per mm to 6 lines per mm). The second portion of the first conductor is disposed normal to the first portion. The interval P.sub.2 of the second portion is selected 300.mu.m or more. An insulating layer 12 is formed by the thick film printing method so as to cover the entire of the second portion. The first conductor group of the main blocks MB.sub.1 and MB.sub.2, . . . are designated by character l. The insulating layer 12 is provided with a hole 13 at the portion corresponding to the almost center of the second portion of each first conductor. The hole 13 is filled with a conductor. On the insulating layer 12, second conductors L.sub.1, L.sub.2, . . . L.sub.n (recording signal feeding lines) are formed by the thick film printing method. These second conductors pass through the hole 13 and coupled with the conductors of the holes and parallel with the second portion of the first conductor. The group of the second conductor is designated by character L.

As seen from FIG. 4, the distance between the connecting portion 13 connecting the first conductor l with the second conductor L and the first portion of the first conductor closest to the connecting portion 13 may be substantially three times that of the FIG. 2 case. Therefore, the interval P.sub.1 of the first portion of the first conductor satisfactorily prevents shortcircuiting between the first conductors, even with its value of 167.mu.m. This enables the yield of the recording head manufacturing to be improved and the size of the recording head to be small. As seen from FIG. 3, number of the connecting points between the first conductor l and the second conductor L in n.times.m/2 (n is number of the recording units in each unit recording block and m is number of the unit recording blocks), the number is half that of the FIG. 1 or FIG. 2 case. This means that the manufacturing process of the recording head is simplified, the yield is improved and the reliability of it is enhanced.

The recording head of the invention may be modified to those shown in FIGS. 5 and 6. In FIG. 5, the printing process of the first conductor l onto the insulating substrate 11 (FIG. 4) is much the same as that of the previous case, thus omitting the illustration of it. In this embodiment, flexible film 15 is used instead of an insulating layer 12. (See FIG. 4). The flexible film 15 is a polyimide film of 30 to 100.mu.m thick. The film 15 is printed on the insulating substrate 11 (FIG. 4) so as to cover the entire of the second portion of the second conductor l in FIG. 4. On the film 15, a copper film with 50 to 100.mu.m thick is formed and then unnecessary portion thereof is removed by etching method, to form the second conductor L. The film 15 is provided with an elongated hole 16 at the portion corresponding to the hole 13 of FIG. 4. The first conductor l and the second conductor L are connected by soldering through the elongated hole 16. FIG. 6 shows an enlargement of the connecting portion of the first conductor l and the second conductor L. In the figure, the number n of the recording units is assumed to be 6.

In the FIG. 5 embodiment, the film 15 includes extensions 15a and 15a. On the major land of the film 15, the second conductor L are alternately portioned out to the right and left sides and directly connected at both ends to connectors (not shown). The alternate portioning out makes substantially uniform the resistances of the conductors extending to the heating resistors. Therefore, the density of the recording information on the recording paper may be made uniform.

As seen from FIG. 3, the connection orders of the recording units to the second conductor L in the respective adjacent unit recording blocks are reversed each other. More specifically, the 1st to nth recording units in the first recording block UB.sub.1 are connected to the L.sub.1 to L.sub.n conductors of the 2nd conductors, respectively. In the second unit recording block UB.sub.2, the 1st to nth recording units are correspondingly connected to the L.sub.n to L.sub.1 conductors, respectively. Therefore, if a series of recording signals to be fed in the order of the recording unit arrangement (for example, image formation signal) is applied to the second conductors in the order of L.sub.1, L.sub.2, . . . L.sub.n, the image formed by the odd numbered unit recording blocks UB.sub.1, UB.sub.3, . . . and that by the even numbered unit recording blocks UB.sub.2, UB.sub.4, . . . are related in reversed fashion. Accordingly, the recording head shown in FIG. 3 must be driven so as not to avoid the image inversion.

Turning now to FIG. 7, there is shown one form of connection schemes of the recording head RH shown in FIG. 3 and a drive circuit DR. In this example, number n of the recording units is 7. The drive circuit DR includes; first and second shift registers SR.sub.1 and SR.sub.2 ; a unit recording block selection circuit 20; drive means to drive first and second shift registers SR.sub.1 and SR.sub.2 ; AND gate groups 21 and 22 for reading out the outputs of shift registers SR.sub.1 and SR.sub.2, respectively; an OR gate group for receiving the outputs of the AND gate groups 21 and 22; and a transistor circuit 24 driven by the output of the OR gate group 23. The unit recording block selection circuit 20 received a selection circuit control signal SC and produces unit recording block selection signals UBC.sub.1, UBC.sub.2, . . . . These unit recording block selection signals are applied to the gate terminals of transistors TR.sub.1, TR.sub.2, . . . , respectively. The emitters of these transistors are commonly connected to +V source. The collectors are coupled with the unit recording block selection terminals C.sub.1, C.sub.2, . . . . The outputs of the OR gates of the OR gate group 23 are connected to the gates of the corresponding transistors of the transistor driving circuit 24, respectively. The emitters of the transistors 24-1 to 24-7 are earthed and the collectors are connected to the second conductors L.sub.1 to L.sub.n in this order, respectively.

The first and second shift register SR.sub.1 and SR.sub.2, their driving means and the gate groups at the output side thereof are detailed in FIG. 8. As mentioned above, 7 recording units are used in this example so that the contents of the shift registers SR.sub.1 and SR.sub.2 are each constructed by 7 bits. A picture signal S.sub.O is binary signals serially supplied and is supplied to the shift registers SR.sub.1 and SR.sub.2. Assume here that the signal supply is made in the serial order of Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7. S.sub.1 is a shift pulse which is used when the picture signal S.sub.O is loaded into the respective registers, and is applied to one of the inputs of each AND gates G.sub.1 and G.sub.2. S.sub.2 is a selection pulse for selecting either of the shift registers SR.sub.1 and SR.sub.2 and applied to the other input of the AND gate G.sub.1, an inverter G.sub.3 and the AND gate group 22. The output of the inverter G.sub.3 is applied to the other input of the AND gate G.sub.2 and the input of the AND gate group 21. The outputs of the AND gates G.sub.1 and G.sub.2 are applied as shift pulses to the shift registers SR.sub.1 and SR.sub.2. Each shift register produces outputs from the respective stages thereof and in this example it produces 7 outputs. As shown, the shift registers each produce 1st to 7th outputs as counted from the right hand side. The ith (n.gtoreq.i.gtoreq.1) output of the shift register SR.sub.1 and the (n+1-i)th output of the shift register SR.sub.2 are coupled with the corresponding first conductor through a single OR gate. With an arrangement, as shown, of the AND gate group 21 including AND gates G.sub.11 to G.sub.17, the AND gate group 22 including AND gates G.sub.21 to G.sub.27, and the OR gate group including OR gates G.sub.31 to G.sub.37, the outputs of the OR gates G.sub.31 to G.sub.37 are correspondingly coupled with the first conductors L.sub.1 to L.sub.n, respectively. The recording signal with the contents Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7 are fed to the drive circuit in the order of Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7. The shift register SR.sub.1 and SR.sub.2 are shifted in an arrow direction.

The operation of the apparatus shown in FIG. 7 will be described with reference to FIGS. 8 and 9. An example to be given is the case where the unit recording blocks UB.sub.1, UB.sub.2, . . . are successively selected in the order of the designations of the blocks. When the unit recording block selection circuit 20 is driven, it produces pulses UBC.sub.1, UBC.sub.2, UBC.sub.3, . . . to successively select the unit recording blocks which in turn drive transistors TR.sub.1, TR.sub.2, TR.sub.3, . . . to select sequentially the unit recording blocks UB.sub.1, UB.sub.2, UB.sub.3, . . . . The shift register selection signal S.sub.2, in order to drive the shift registers SR.sub.1 and SR.sub.2, is transferred to the gate G.sub.1, the inverter G.sub.3 and the gate group 22. As shown in FIG. 9, the selection signal S.sub.2 has alternately and serially arranged "1" and "0" and the time widths of "1" and "0" are equal. The shift register selection signal S.sub.2 and the unit recording block selection pulses UBC.sub.1, UBC.sub.2, UBC.sub.3, . . . are synchronized in a predetermined relation. That is, the unit recording block selection pulses UBC.sub.1, UBC.sub.2, UBC.sub.3, . . . are produced at the time period S.sub.22, S.sub.23, S.sub.24, . . . , respectively. During each time period S.sub.21, S.sub.22, . . . , seven shift pulses S.sub.1 and seven recording signals S.sub.O are applied to the respective shift registers. At time t.sub.1, when the register selection signal S.sub.2 is "1", the shift register SR.sub.1 is selected and shifted in the arrow direction by the shift pulse S.sub.1 fed through and AND gate G.sub.1. The recording signal S.sub.O is serially supplied to the shift register SR.sub.1 so that the bits Q.sub.1 to Q.sub.7 of the recording signal S.sub.O are loaded into the shift register SR.sub.1 at the time periods S.sub.21, as shown in the figure. At time t.sub.2, when loading of it is completed, the register selection signal S.sub.2 is "0" which passes through the inverter G.sub.3 to reach as "1" the AND gates G.sub.11 to G.sub.17. Therefore, the recording signals Q.sub.1 to Q.sub.7 are transferred to the second conductors L.sub.1 to L.sub.7 through the OR gates G.sub.31 to G.sub.37. At time t.sub.2, the unit recording block selection signal UBC.sub.1 is "1" and therefore the recording signals Q.sub.1 to Q.sub.7 are supplied to the recording elements R.sub.11 to R.sub.17 to be recorded on a recording paper (not shown). At time t.sub.2, the register selection signal S.sub.2 is "0" and is inverted in the inverter G.sub.3 to be "1". The inverted "1" signal is applied to the AND gate G.sub.2. Upon the reception of the signal "1", the AND gate G.sub.2 permits the shift register SR.sub.2 to shift in the arrow direction and the recording signal Q'.sub.1 to Q'.sub.7 to be loaded into the register as shown in the figure. At time t.sub.3, when the loading of it is completed, the shift register selection signal S.sub.2 becomes again "1" and thus the recording signals Q'.sub.1 to Q'.sub.7 are applied through the AND gates G.sub.21 to G.sub.27 and the OR gates G.sub.37 to G.sub.31 to the second conductors L.sub.7 to L.sub.1. At time t.sub.3, the selection signal UBC.sub.2 of the unit recording block UB.sub.2 is produced, and therefore the recording signals Q'.sub.1 to Q'.sub.7 are applied to the writing elements R.sub.21 to R.sub.27 of the unit writing block UB.sub.2. In other words, the recording signals Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7 are applied to the recording elements R.sub.11 to R.sub.17 and R.sub.21 to R.sub.27. In this manner, it is avoidable to reverse the records made by the unit recording blocks UB.sub.1 and UB.sub.2. Then, when the unit recording block UB.sub.3 is selected, the signals to be recorded are successively supplied from the shift register SR.sub.1 to the second conductors L.sub.1 to L.sub.7. In other words, the order in which serially incoming recording signals are supplied to the second conductors is reversed each time the unit recording block is selected with the result that the recording is normally made, i.e. avoiding the picture inversion.

In the description referring to FIG. 7, the unit recording blocks are selected in the order of the arrangement thereof; however, any one of the unit recording blocks may be selected. In this case, when the odd numbered unit recording block is selected, the contents of the first shift register SR.sub.1 is recorded and when the even numbered unit recording block is selected, the contents of the second shift register SR.sub.2 is recorded.

In the embodiment of FIG. 7, in order to alternately supply the outputs of the shift registers SR.sub.1 and SR.sub.2 to the second conductor L, the OR gate group 23 is provided between the shift registers SR.sub.1 and SR.sub.2 and the second conductor L. A modification of this is shown in FIG. 10, in which only the output of the shift register SR.sub.2 is supplied to the second conductor L. This modification simplifies the circuit construction of the drive circuit and therefore is advantageous in the manufacturing process and the cost saving.

In FIG. 10, the recording signal S.sub.O is inputted to the first shift register SR.sub.1. Shift pulses S.sub.a with first frequency and another shift pulses S.sub.b with second frequency higher than the first one are applied to an OR gate G.sub.40 of which the output is applied as shift pulses to the first shift register SR.sub.1 of seven bits. Shift pulses S.sub.b are applied as shift pulses to the second shift register SR.sub.2 (Buffer Register). A recording signal S.sub.4 fed from the first shift register SR.sub.1 is applied to one of the inputs of each AND gate G.sub.42 and G.sub.43. A pulse S.sub.3 for switching the shift direction of the second shift register SR.sub.2 is applied to the second shift register SR.sub.2 while at the same time to the other input of the AND gate G.sub.42. The same pulse S.sub.3 is applied to the other input of the AND gate G.sub.43 through an inverter G.sub.41.

Output pulse S.sub.5 (a right-shift pulse) of the AND gate G.sub.42 switches the shift direction of the shift register SR.sub.2 to the right and serves as an input to the shift register SR.sub.2 to load into the position shown in the figure the input signals Q.sub.1 to Q.sub.7, through the first shift register SR.sub.1. Output pulse S.sub.6 (a left-shift pulse) of the AND gate G.sub.43 changes the shift direction of the shift register SR.sub.2 to the left, thereby to load the input signals Q'.sub.1 to Q'.sub.7 into the position shown in the figure. The outputs of the 1st to 7th stages as counted from the right on the drawing are coupled with the bases of transistors TR.sub.1 to TR.sub.7, through resistors R.sub.1 to R.sub.7. The emitters of transistors TR.sub.1 to TR.sub.7 are connected commonly and the collectors thereof are connected to the second conductors L.sub.1 to L.sub.7. The recording signal S.sub.O, for example, Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7, are serially inputted into the first shift register SR.sub.1. In this case, the recording signals Q.sub.1 to Q.sub.7 are firstly loaded into the register SR.sub.1 by the shift pulse S.sub.a. When the loading of it into the shift register SR.sub.1 is completed, the pulse S.sub.3 becomes "1" to change the shift direction of the shift register SR.sub.2 to the right. At the same time, the shift pulse S.sub.b feeds the recording signals Q.sub.1 to Q.sub.7 (S.sub.4) stored in the register SR.sub.1 to the AND gate G.sub.42 and G.sub.43. At this time, the shift direction switch pulse is "1" and therefore the AND gate G.sub.42 is enabled. The output S.sub.5 of the AND gate G.sub.42 is connected to the right shift input of the register SR.sub.2. For this, the shift pulse S.sub.b transfers the contents Q.sub.1 to Q.sub.7 of the register SR.sub.1 from the shift register SR.sub.1 to SR.sub.2 at high rate, through AND gate G.sub.42.

The contents Q.sub.1 to Q.sub.7 of the register SR.sub.2 are supplied to the second conductors L.sub.1 to L.sub.7. At this time, as described referring to FIG. 7, the odd numbered unit recording block, for example, UB.sub.1, is selected so that the recording signals Q.sub.1 to Q.sub.7 are supplied to the writing elements R.sub.11 to R.sub.17 (see FIG. 7). Then, the recording signals Q'.sub.1 to Q'.sub.7 are loaded into the first shift register SR.sub.1 by the shift pulse S.sub.a. Upon the completion of the loading, the pulse S.sub.3 becomes "0" to change the shift direction of the register SR.sub.2 to the left as viewed on the drawing. And the pulse S.sub.3 passes through the inverter G.sub.41 to one of the inputs of AND gate G.sub.43, thereby to enable the gate G.sub.43. Accordingly, the recording signals Q'.sub.1 to Q'.sub.7 (S.sub.4) becomes an output signal S.sub.6 to be applied as a left shift input signal of the shift register SR.sub.2 to the register SR.sub.2. At this time, the shift pulse S.sub.b is applied to the registers SR.sub.1 and SR.sub.2 to permit the recording signals Q'.sub.1 to Q'.sub.7 to be transferred to the position shown in the FIGURE of the shift register SR.sub.2. Accordingly, the recording signals Q'.sub.1 to Q'.sub.7 are delivered to the second conductors L.sub.7 to L.sub.1.

At this time, the unit writing block, for example, UB.sub.2 (FIG. 7), is selected so that the recording signal Q'.sub.1 to Q'.sub.7 are applied to the writing elements R.sub.21 to R.sub.27. In this way, while the shift direction of the first shift register SR.sub.1 is fixed, the shift direction of the second shift register SR.sub.2 is reversed each time the unit recording block is selected. Through that operation, the recording signal may be recorded on the recording paper with normal relative positions of the pictures recorded.

FIG. 11 shows an example to reverse the shift direction of the first shift register SR.sub.1 each time the unit recording block is selected. In the figure, the recording signal S.sub.0 provides bit signals Q.sub.1 to Q.sub.7 and Q'.sub.1 to Q'.sub.7 in this order to the first shift register SR.sub.1. The writing shift pulse S.sub.1 is coupled with the shift register SR.sub.1. The recording signal S.sub.0 is supplied to one of the inputs of each AND gate G.sub.42 and G.sub.43, and the shift direction switching pulse S.sub.3 is supplied to the other input of the AND gate G.sub.42 and with the other input of the AND gate G.sub.43 through an inverter G.sub.41. The pulse S.sub.3 is also coupled with the register SR.sub.1 in order to change the shift direction of the register SR.sub.1. The output S.sub.5 of the AND gate G.sub.42 is applied to the shift register SR.sub.1 to be shifted to the right direction while the output S.sub.6 of the AND gate G.sub.42 is applied to the shift register SR.sub.1 to be shifted to the left direction.

The contents of the shift register SR.sub.1 are simultaneously transferred in parallel to the second shift register SR.sub.2 by a writing control pulse S.sub.7. The contents of the respective stages of the second shift register SR.sub.2 are delivered to the second conductors L.sub.1 to L.sub.7, in response to the writing control pulse S.sub.7. The shift direction switching pulse S.sub.3 "1" and the output of the AND gate G.sub.42 cooperate to load the recording signals Q.sub.1 to Q.sub.7 into the position as shown of the register SR.sub.1. The writing control pulse S.sub.7 transfers in parallel the loaded contents to the second conductors L.sub.1 to L.sub.7. At this time, the odd numbered recording block, for example, UB.sub.1, is selected so that the recording signals Q.sub.1 to Q.sub.7 are applied to the writing elements R.sub.11 to R.sub.17. Then, the shift direction switching pulse S.sub.3 becomes "0" so that the AND gate G.sub.43 is enabled and the recording signal S.sub.0 goes to the input of the first shift register SR.sub.1 to be shifted in the left, through the AND gate G.sub.43. The shift direction switch pulse S.sub.3 shifts the register SR.sub.1 to the left so that the recording signals Q'.sub.1 to Q'.sub.7 are loaded into the position as shown. After this, the writing control pulse S.sub.7 transfers the contents of the first shift register SR.sub.1 to the second shift register SR.sub.2, in parallel fashion, from which the contents are delivered to the second conductors L.sub.7 to L.sub.1. At this time the odd numbered unit recording block, e.g. UB.sub.2, is selected and therefore the recording signals Q'.sub.1 to Q'.sub.7 are supplied to the recording elements R.sub.21 to R.sub.27.

While the description thus far described relates to the thermal recording apparatus, the invention may also be applied to electrostatic recording apparatuses, the discharge recording apparatuses and the like.