Brain Wave Responsive Programmable Electronic Visual Display Systems

The present invention relates to programmable electronic visual display systems. More particularly the present invention relates to systems of that type in which multiple dimensional displays are provided for visually connecting in a logical manner visual displays with, for example, an audio, input signal such as from a musical sound source. It is also anticipated that input sources other than audio can be used with the system of the present invention. One other example which is given is a system driven by brain wave inputs.

The basic concept of providing visual light displays to accompany musical programs has been employed in several prior art systems. One such system is illustrated in the applicant's prior U.S. Pat. No. 3,806,873 which issued on Apr. 23, 1974. The system described in this patent provided a means for achieving a variation of color according to the frequency content of a musical score in the visual display together with special synchronization of the movement of the display according to the beat of a musical score. In other words, this prior patent has taught the creation of a visual display system which achieves a color spectrum of the musical score together with motion of the spectral display in synchronization with the beat or tempo of the music in a manner which is determined by the musical score.

Such prior art systems as described in the applicant's aforementioned patent have provided the first intelligent visual communication of the audio content of a musical score. Systems of this type have proven extremely useful, for example, in communicating the intelligence of a musical score to those such as handicapped persons who can not perceive the auditory content of the musical score per se.

Systems such as that in the applicant's aforementioned prior patent have relied to a great deal on the rhythm content and frequency content of the audio input itself to produce pleasing displays in the visual display portion of the system. The present invention retains the advantage of such prior art systems while in addition introduces the capability of providing multiple displays which may be located in spacially significant parts of a setting such as a concert hall but, moreover, provide for predetermined pleasing patterns to be introduced in the visual display portion of the system which patterns may be of any character designed and which are not solely determined according to the rhythmatic and frequency content of the input portion of the system. While the systems to be described are described in terms of audio input signals, it is anticipated that other types of input sources can be used. The following descriptions are intended as being exemplary in this sense, rather than limitative.

Thus, programmable visual display systems according to the concepts of the present invention provide a new dimension in communication of the intelligence conveyed in an input such as a musical score in the sense that such intelligence may be interpreted through the motion, tempo of the motion, frequency content, and intensity of an audio input. A system contemplated by the present invention can provide a much more subtle and aesthetic conveyence in a visual display of the intent and mood of an audio composition such as a musical score than in any system afforded in the prior art.

A programmable electronic visual display system in accordance with the concepts of the present invention includes at least two basic logic systems. These logic systems comprise an amplitude dependent logic system and a frequency dependent logic system, both of which are responsive to an input signal. Both logic system components of the programmable electronic visual display system of the present invention superimpose logical selection of visual display patterns which may be preselected in a predetermined manner upon both the amplitude and frequency content of the input. The logical operations performed in response to both the amplitude information and the frequency information contained in an audio input such as musical score may be of various types. These logical functions are selectable by the user or the designer of the system and may be selected in order to accomplish multiple ends in the conveyance of the mood, frequency content, and intensity of the input audio signals and are always superimposed upon the visual interpretation of the audio input signals. There is a pattern to the display or multiple displays of the system which may be predetermined according to whatever concept is desired in a particular system. Moreover, there may be crossover logic components used in a system according to the concepts of the present invention to interconnect the logical operations of both the amplitude and frequency content dependent logic portions of the system. The net result of a programmable visual electronic display system of the type of the present invention is to provide a much more subtle and pleasing conveyance of the information content of the audio input signal than has theretofore been possible with any prior art visual display system for use in conjunction with an audio input.

Other features and advantages of a programmable electronic visual display system in accordance with the concepts of the present invention will become more apparent from the following detailed description of systems in accordance with the concepts of the present invention when taken in conjunction with the drawings appended hereto which include:

FIG. 1 is a simplified schematic block diagram illustrating a programmable visual display system in accordance with the concepts of the present invention and having a single visual display.

FIG. 2 is a simplified schematic block diagram of a programmable visual display system in accordance with the present invention and having multiple visual displays.

FIG. 3 is a more detailed block diagram of a visual display system in accordance with the concepts of the present invention having multiple displays and illustrating a particular type of logic function for display selection and motion.

FIGS. 4a and 4b are more detailed but still schematic block diagrams illustrating a multiple display system in accordance with the concepts of the present invention and having still further logical functions associated with the display selection in motion logic.

FIGS. 5a and 5b are illustrations of one element of a visual display showing details of its construction, a matrix display comprising a plurality of elements of the type of FIG. 5a.

FIG. 6 is a schematic illustration showing three types of visual displays having different pattern and motion characteristics.

FIG. 7 is a simplified schematic block diagram of a visual display system in accordance with the invention, this system having a separately programmable display duration portion.

FIGS. 8a and 8b are simplified block diagrams of a visual display system utilizing a brain wave input.

FIG. 9 is a circuit diagram of a brain wave input device.

FIG. 10 is a simplified schematic diagram of a visual display system utilizing brain wave amplitude and frequency content to control visual displays.

Referring initially to FIG. 1, an audio signal is input on line 11 to a programmable visual display system in accordance with the concepts of the present invention. A portion of the signal provided on line 11 is coupled through a bass filter 12 which separates the high frequency content portion of the signal therefrom and which may comprise, for example, a typical LC filter network designed for this purpose. The output signal from the bass filter 12 is an amplitude dependent signal (i.e. carries the amplitude information) of the audio input signal. This signal is supplied as an input to an audio sychronized variable frequency clock oscillator circuit 13. The clock circuit 13, which will be described in more detail subsequently, provides a variable frequency clock pulse output whose pulse rate is determined by the amplitude of the input audio signal provided on line 11. Thus a sequence of clock pulses is provided as an output from the audio frequency synchronized variable clock oscillator circuit 13 and this output is coupled to an address counter 14.

The address counter 14 comprises a binary up-down counter which is used to access memory locations according to their addresses in a pattern memory 15. The pattern memory 15 may comprise, for example, a programmable read only memory (PROM) which contains a number of memory locations each of which has a specified address and is accessible through indexing via the address counter 14. The output signals from the pattern memory 15 comprise a plurality of bit patterns which correspond to the lights in a visual display which are to be illuminated, for example. Thus as the address counter 14 contents changes as a function of the clock rate provided by the audio synchronized variable frequency clock 13, different memory locations in the pattern memory 15 are addressed by the address counter 14 in a seqential manner. Thus different patterns of lights indicated by the output signals from the pattern memory are signalled in a display unit 19 to be described in more detail later via a logic mask 16.

Simultaneously with this operation, the audio input signal provided on line 11 is coupled to an automatic gain control circuit 17. This circuit functions to amplify the signal to a relatively constant output level without distorting the frequency content thereof. Thus an output signal is provided from the automatic gain control circuit 17 which contains all of the frequency information present on the input audio signal on line 11. This frequency content dependent signal is supplied to a programmable frequency content selection logic circuit 18.

The programmable frequency content selection logic circuit 18 may comprise any of a number of types of frequency content selection logic circuits, but generally may be stated to include a plurality of frequency filters which separates the frequency content of the input signal into a plurality of different frequency channels. Thus a plurality of output signals are provided from the programmable frequency content selection logic circuit 18 which are also supplied to the logic mask 16 and used to determine, for example, the color of the lights which will be illuminated on the display unit 19.

The logic mask 16 may comprise, for example, a logic circuit which combines the amplitude dependent pattern signal from the pattern memory together with the frequency dependent signal from the programmable frequency content selection logic circuit 18 in order to produce output signals which contain a combination of pattern and color information to be provided on the visual display unit 19.

It will be noted in the system of FIG. 1 that the pattern of lights to be displayed on the display panel 19 is largely determined by the preprogrammed contents of the pattern memory 15. This pattern memory 15 may be, for example, a 256 eight binary digit (or bit) word programmable read only memory or PROM in which each bit position in each of the eight bit words corresponds to a particular light in a horizontal, diagonal, or vertical row of lights on the display means 19. If a particular light in a given pattern is specified by both the pattern memory and simultaneously by the programmable frequency content selection logic (as determined by logical action of the mask 16) then that light will be illuminated on the display panel 19. Different patterns will appear on the display according to contents of the memory locations of the pattern memory 18 at a time which is determined by the contents of the address counter 14.

It should also be noted that the programmable frequency content selection logic circuit 18 could also contain pattern logic similar to that described with respect to the audio portion of the circuit, but for the purposes of the description of FIG. 1 it will suffice to say that this logic circuit 18 may comprise merely a plurality of frequency filters each having independent outputs.

Referring now to FIG. 2 a programmable visual display system in accordance with the concepts of the present invention is illustrated schematically. The system of FIG. 2 is similar to that described with respect to FIG. 1, with the exception that multiple displays are generated simultaneously in the system of FIG. 2.

An audio input signal is supplied on line 21. A portion of this signal is coupled to a bass filter 22 which is analogous to the bass filter 12 of FIG. 1. An amplitude dependent output signal is supplied from the bass filter 22 to an audio synchronized variable frequency clock oscillator 23. The clock oscillator 23 frequency varies at a rate which is determined by the amplitude of the audio signal input on line 21. Clock pulses are provided as output from the clock oscillator 23 to an address counter 24. The address counter 24 may comprise a binary up-down counter which serves to count and accumulate a number of clock pulses generated by the audio synchronized variable frequency clock oscillator 23. The contents of the address counter 24 is used to index memory locations in three different display pattern memories, 25, 26, and 27 in a manner analogous to that used to index the memory locations of the pattern memory 15 of FIG. 1. Memory locations in the pattern memories 25, 26, and 27 determine (in conjunction with frequency information logic circuit outputs) the pattern to be displayed on three displays 33, 34 and 35. Again the pattern memories 25, 26 and 27 may comprise, for example, 256 word, 8 bit programmable read only memory (PROM) circuits, which each contain independent pattern information in the memory words comprising the PROMS. The memory location which is addressed in each of the three PROMS 25, 26 and 27 supplies parallel line outputs to three logic masking circuits 28, 29 and 30 where they are combined with the information from the frequency content logic channel in a manner analogous to that of FIG. 1.

With regard to the frequency content information portion of the circuit, a portion of the input signal supplied on line 21 is coupled to an automatic gain control circuit 32. Gain control circuit 32 serves to amplify the signal to a relatively constant amplitude level independent of its frequency content. The frequency content dependent signal output from the automatic gain control circuit 32 is supplied to a programmable frequency content selection logic circuit 31 which may serve, for example, to break this signal up into a plurality of different frequency component voltage levels depending upon the instantaneous frequency content of the input signal supplied on line 21. The plurality of output signals supplied from the programmable frequency content selection logic circuit 31 is supplied to the logic masks 28, 29 and 30, where they are combined with the three pattern signals from the pattern memories 25, 26 and 27 in order to determine the actual lights to be illuminated on three separate independent display panels 33, 34 and 35.

In order to better appreciate the operation of the systems described with respect to FIG. 2, reference is now made to FIG. 6 which illustrates generally three separate matrix display systems of the type which may correspond to the displays 33, 34 and 35 of FIG. 2. The three displays of FIG. 6 are labeled Display 1, Display 2 and Display 3. Each consists of a rectangular array of lights, of a type to be described in more detail subsequently arranged in a 10 .times. 15 matrix array. The different colored lights in the display arrays of FIG. 6, are illustrated by the different cross-hatching arrangements shown there. A particular pattern of lights in a display is generated by a particular word of memory in the pattern memory 15, and the corresponding color information which is supplied from the programmable frequency content selection logic circuit 31, as determined by the logic masks 28, 29, and 30. Thus, assuming for example that the output signals from the programmable frequency content selection logic circuits 31 is such as to turn on all colors of lights, then a pattern of lights which is determined by the content of the particular pattern memory location addressed by the address counter 24, in pattern memories 25, 26 and 27 would be illuminated at a particular instant of time. As the contents of the address counter 24 change, this pattern would proceed across the display array having an apparent motion in the direction illustrated by the arrows in FIG. 6. In the display labeled Display 1 of FIG. 6, for example, the pattern would proceed from right to left, or left to right, in the display. (Assuming, for example, the pattern to be displayed is a straight line). In the display labeled Display 2 in FIG. 6, the pattern generated by the contents of the pattern memory would proceed to progress along diagonal lines as indicated by the arrows. Finally, in the display labeled Display 3, the pattern generated by the pattern memory would proceed in the vertical direction indicated by the arrows.

The rate at which this pattern would move across any of the displays of FIG. 6 would be determined by the rate at which the address counter 24 of FIG. 2 is updated. This rate in turn is controlled by the audio synchronized variable frequency clock oscillator circuit 23, which is responsive to the amplitude information of the input signal supplied on the line 21. Thus, in the system illustrated in FIG. 2, three separate displays 33, 34, and 35 corresponding to displays labeled Display 1, Display 2, and Display 3 of FIG. 6 can be driven simultaneously in response to the audio input signal.

In connection with the displays of FIG. 6 it should be noted that while the three independently controlled visual displays of the light arrays of FIG. 6 are illustrated separately as three separate 10 .times. 15 arrays that, if desired, the three display systems of FIG. 6 could be superimposed upon each other in one large rectangular array 10 .times. 15 in dimension and having at each location in the array three separate lights mounted coincidently. Thus in the type of display described with the superimposed three displays of FIG. 6 it would be possible to have a combination effect of the motions of the three independently controlled displays simultaneously into one apparent 10 .times. 15 rectangular array of lights. It should also be noted that while the display patterns discussed with respect to FIG. 6 have been described in their simplest terms in terms of straight lines of lights corresponding to the preprogrammed pattern in the pattern memories and having straight lines procede in either horizontal, vertical, or diagonal motion across the display, that it is, of course, possible to have other than straight line patterns generated by the pattern memories 25, 26 and 27. Thus a variety of motion and kaliedoscopic effects are obtainable with a visual display system of the type illustrated in FIG. 2. The variety and motion of patterns is only limited by the imagination of the programmer placing the information into the contents of the PROM's 25, 26 and 27. As will be discussed further with respect to the subsequent figures, it is also possible to have more diverse logic functions for determining the patterns and the motion of the patterns together with the color selection logic which may also be made as variable as desired. Indeed one of the major advantages of a programmable visual display system in accordance with the concepts of the present invention is that such a system may be preprogrammed to respond in a desired manner to a particular musical score, for example with varied patterns, rate of motion and direction of motion of the patterns determined by the contents of the preprogrammed pattern memories.

Referring now to FIG. 5a the visual display system individual lighting components is illustrated in more detail. A geometrically shaped, frosted, plastic or glass diffuser cover 42, 43 is used to diffuse the light from a colored light bulb source 44 which is mounted in a conventional light socket 45 on the display base board 41. The diffuser cover 42, 43 is frosted so that it emanates the light bulbs' color uniformly across its entire surface. Thus each light in the display array of FIG. 6 allows a uniformly pure color emanation without producing a point source effect. Moreover, the display light covers 42 and 43 may be made in a variety of geometrical shapes and sizes as illustrated in the matrix of FIG. 5b. These diffuser covers also serve to conceal the shape and color of the bulb contained therein so that when a particular bulb is not illuminated in a display its color remains concealed from external visual contact. The diffuser covers 42 and 43 comprise a translucent, frosted or matte finish plastic. The height of the diffuser covers may be different for each of the different colored lights which they conceal, for example, red lights could have the tallest covered diffuser covers 42, 43 while blue lights may have smaller or shorter diffuser covers. The three dimensional effect given by such an arrangement is shown in FIG. 5b in more detail. The separability of the covers into two portions 42 and 43 as illustrated in FIG. 5a enables easy replacement of a light bulb should the bulb need replacement. Electrical connections 46 are supplied to the bulb via the screw in bulb socket 45 which may be of a conventional type.

Visual displays utilizing diffuser light sources as illustrated in FIG. 5b have many advantages over prior art light displays in that through the use of different dimension diffuser covers a three dimensional effect may be given to the array when viewed from a side or obtuse angle. This presents a pleasing effect which has been attempted in the prior art, without much success, by the placement of conventional colored light bulbs at different distances behind a single diffuser screen of some sort.

While a particular display matrix utilizing conventional light bulbs has been illustrated with respect to the systems of the present invention, it will be appreciated by those skilled in the art that light emmitting diode (LED) sources could be used, if desired, or other more conventional visual displays including color cathode ray tubes (CRT) could be used as desired for the display portion 33, 34, 35 of the system of FIG. 2. The novel three dimensional display system described with respect to FIGS. 5a and 5b, however, gives an effect heretofore unknown in the prior art.

It should be mentioned that if the superimposed three displays on a single matrix board as discussed with respect to FIG. 6 are utilized, that all three bulbs for each position of the 10 .times. 15 matrix may be placed inside a single diffuser cover. Alternately, there may be three separate diffuser covers for each bulb at each matrix location if so desired. Similarly the three displays may be completely spacially separated as in the illustration of FIG. 6 itself. Such separated displays may be positioned at different locations in the vicinity of the viewing audience as desired.

Referring now to FIG. 3 another embodiment of a visual display system in accordance with the concepts of the present invention is illustrated in more detail, but still schematically. In the system of FIG. 3, two three-stage ring counters determine the pattern to be displayed, while a shift direction detection circuit determines the direction of motion of the pattern across the display matrix. The color content of individual lamps in the display pattern is determined by the frequency content of the audio input in the system of FIG. 3.

In the system of FIG. 3, audio input is supplied at 51. A portion of this audio input is coupled via a filter 52 and a coupling transformer 53 to an amplitude, or frequency synchronized clock 54. The amplitude, or frequency synchronized clock is a precision oscillator circuit whose operating frequency is synchronized with either the amplitude information contained on the input audio input signal supplied at 51, or on the frequency content of the signal supplied on the audio input 51. If frequency content synchronization is desired, the filter 52 could be a band pass filter, which uniformly passes the range of frequencies in the audio region without distortion to the coupling transformer 53. For purposes of the present description of the system of FIG. 3, however, it will be assumed that the clock 54 is amplitude synchronized as previously described. It should be noted, however, that the clock 54 could be made frequency synchronized if desired.

Output clock pulses are provided from the synchronized clock 54 to a clock pulse stretcher 55, which shapes and lengthens the clock pulses. The clock pulses from the pulse stretcher 55 are supplied to a three-stage motion ring counter 58. The pulse stretcher 55 output is also supplied via a clock divider 56 to a three-stage display ring counter 59. The three-stage motion ring counter 58 and the three-stage display ring counter 59 are also responsive to an input from a shift direction detection circuit 57, which will be described in more detail subsequently.

The logical product of the contents of the two ring counters 58 and 59, form the pattern to be displayed on three independent displays via NAND logic masking arrays 75, 76 and 77, which are conventional NAND masks, analagous to those previously described with respect to FIGS. 1 and 2.

The motion ring counter 58 is supplied with clock pulses from the pulse stretcher 55 to an input NAND up-down determining network 60. The second input of the NAND up-down count determining network 60 is supplied from the output of the shift direction detection circuit 57. The up-down determining network 60 supplies a logic level output on either the down, or up count lines, as labeled in FIG. 3 to a binary up-down ring counter 61. The clock pulses are supplied thus, to either the up or down input of the counter 61 depending on the alternate input signal from the shift direction detection circuit 57 as supplied to the NAND up-down determining network 60. Thus, the motion counter 61 is responsive to both the amplitude information contained on the input signal and the shift direction signal supplied from the shift direction detection circuit 57. The contents of the up-down counter 61 is extracted in parallel form by decoder 62 and supplied as parallel input to a NAND feedback circuit 63, which is also conditioned by an output signal from the up-down counter 61, such that it supplies an output signal on its three output leads to the NAND masks 75, 76, and 77, during the duration of a clock pulse, as determined by the up-down counter 61.

Similarly, clock pulses from the pulse stretcher 55 are provided via a clock divider 56 to a NAND up-down determining network 71 in the display ring counter 59. The display ring counter 59 is also supplied with alternate up-down count determining signals from the shift direction detection circuit 57 via a command divider 70. The clock dividers 56 and 70 are provided with manual multiple switches 56a and 70a, which may be used to control the rate at which pattern and direction of motion are altered by the user by slowing down the effective rate of the clock 54 or the shift direction detection circuit 57 by dividing circuits 56 and 70.

Thus, the NAND up-down determining network 71 in the display counter 59 provides output pulse signals on either its up or down count lines as labeled in FIG. 3, according to the frequency of pulses supplied from the clock pulse stretcher 55 and the output signals from the shift direction circuit 57. These signals are supplied to a binary up-down counter 72, which counts the clock pulses as they are supplied to it, either in an upward or downward direction determined by the NAND up-down determining network 71. The contents of the display ring counter 72 are extracted by the serial to parallel decoder 73 and supplied to a NAND feedback circuit 74, which is also conditioned by an output signal from the binary up-down counter 72 to supply outputs from the NAND feedback circuit 74 during the existance of a clock pulse. Thus, the output signals are provided on the three output lines from the display ring counter 59 to the NAND masks 75, 76 and 77, where the logical product of these display output signals and that from the motion ring counter 58 are formed to determine the selection of the pattern of lights to be displayed on each of the three displays.

A second portion of the audio input signal supplied at 51 is coupled to an automatic gain control circuit 69, which serves to amplify the signal uniformly as a function of frequency to a constant amplitude. Output signals from the automatic gain control circuit 69 are supplied to a five channel translator circuit 78 and to the shift direction detection circuit 57.

The five channel translator 78 may comprise a plurality of bandpass frequency filters producing five output signals labeled high, mid-high, mid, mid-low, and low which determine the color combination to be displayed according to the frequency content of the audio signal input at 51. This arrangement is illustrated in FIG. 5b.

The frequency dependent signals supplied from automatic gain control circuit 69 is also coupled to the input of a shift direction detection circuit 57. An input bandpass filter 64 is used to select a particular frequency range or band of interest for controlling the direction of motion of the display. This may be any band of audio frequencies chosen for this purpose as desired. The filtered audio signal is supplied to a DC level converter 65 which samples the peak amplitude at the chosen frequency or band of frequencies and supplies an output logic level signal to a Schmitt trigger 66. A free running sample clock oscillator 67 provides clocking signals to one input of a type D flip-flop 68. The output signals from the Schmitt trigger 66 are supplied to the opposite input of the type D flip-flop 68. When a sample clock signal from the clock 67 is present at one input to the flip-flop 68 simultaneously with the existance of a logic level signal from the Schmitt trigger 66 a change of state of the flip-flop 68 occurs. This corresponds to a reversal of the direction of motion of the pattern to be displayed. This change of state signal is supplied to both the motion ring counter 58 and the display ring counter 59 as previously described in order to determine the direction of count in the binary counter 61 and 72. In this manner the shift direction detection circuit samples a particular range of frequencies and upon the occurence of an output signal or lack of output signal in the chosen band of frequencies (as determined by the filter 64) causes a reversal of the directional motion of the display. The effect obtained by this circuitry is to provide a pattern of lights corresponding to the amplitude and frequency content of the audio signal which is input at 51 and to produce motion of this pattern which reverses periodically according to the presence or absence of a particular range of frequencies in the audio input.

The logic product signals which are output from the NAND masks 75, 76 and 77 are coupled to opto isolator and trigger and power control circuits 79, 80 and 81. These circuits are described in more detail in the previously mentioned issued U.S. Patent of the applicant. It will suffice to state therein that they control, by means of solid state switching devices, the supply of power to the lamps on the display boards.

Turning now to FIGS. 4a and 4b yet another embodiment of a programmable visual display system in accordance with the concepts of the present invention is illustrated schematically. In the system of FIGS. 4a and 4b, four separate visual displays are provided. In this system the display pattern and the motion in each of the four displays are determined by the contents of programmable read only memories (PROM's). Moreover, alternate logics are provided for determining the shift of the direction of motion either as a function of the amplitude or frequency of the audio input signal or as a direct function of a rate clock signal supplied for this purpose.

In the system of FIGS. 4a and 4b the audio signal is input at 101. A portion of the input audio signal is coupled through a filter 102 to an amplitude or frequency synchronized clock 103. The amplitude or frequency synchronized clock 103 of FIG. 4a is analagous to that clock 54 previously discussed with respect to FIG. 3. The output signal from the clock 103 is a succession of clocking pulses whose frequency is determined by either the amplitude or frequency content of the audio signal input at 101. These clock signals are supplied as one input to a motion program counter 104. The opposite input of the motion program counter 104 is provided from alternate logic circuits selected by switch 121. This input to motion program counter 104 determines the direction of motion of the display on each of the four individual display matrix panels. Additionally, the output signals from the clock 103 are supplied via a line 122 (in FIG. 4b) to display clock divider 123. A switch 125 is provided to select the divider output of the display clock divider 123 to provide a clock input to a display program counter 127 via the switch 125. When the switch 125 is in any of the positions except position A shown in FIG. 4b, the output of display clock divider is sampled under manual control. When switch 125 is in position A the clock rate is placed under program control of the contents of a divider clock memory 129 whose function will be discussed in more detail subsequently.

Assuming the switch 125 to be in any of its other positions than position A the clock signal from the amplitude or frequency synchronized clock 103 is provided to the clock input of the display program counter 127 via the display clock divider 123 according to the manually selected position of the switch 125. The opposite input of the display program counter 127 is supplied with an up or down count signal from a command divider 126 which is provided by a shift direction and detection circuit 119. The shift direction and detection circuit 119 is similar to that discussed with respect to the circuit 57 of FIG. 3. Thus the contents of the display program counter 127 is updated according to the output of the amplitude or frequency synchronized clock 103 and the shift direction detection circuit 119 as scaled by dividers 123 and 126 respectively.

The display pattern is chosen on the basis of the contents of the display program counter 127. The counter 127 is used to index an appropriate memory location in the display pattern PROM 128. The contents of the PROM memory location which is indexed by the content of the display program counter 127 is supplied as output signals to the four NAND masks 107, 108, 109 and 110 which function in the same manner as discussed previously with respect to the embodiments shown in the other figures.

The motion of the chosen display pattern supplied from display PROM 128 is determined by the contents of motion PROMS 105 and 106 as indexed by the contents of the motion program counter 104. The contents of the memory locations indexed by the motion program counter 104 in motion PROMs 105 and 106 is supplied to the NAND masks 107, 108, 109 and 110 as indicated in FIG. 4a. The NAND masks 107, 108, 109 and 110 perform the logical product of the contents of the memory locations in display PROM 128 and motion PROMs 105 and 106 thereby providing the light display pattern and motion information as output signals therefrom. These output signals are coupled to the trigger and power control circuits 111, 112, 113 and 114 to drive the display lights in the manner previously discussed.

Returning to consideration of the audio input signal at 101 of FIG. 4a, a second portion of this signal is coupled via a filter 115 to a second amplitude or frequency synchronized clock circuit 116. This clock circuit runs at a rate determined by either the amplitude or frequency content of the input signal and thus provides output pulses to a command clock divider 117 at a rate which is proportional to either of these chosen quantities. If, for example, it is chosen to run the amplitude or frequency synchronized clock 103 at a rate controlled by the amplitude of the input signal, then it would provide a pleasing effect to control the amplitude or frequency synchronized clock 116 at a rate controlled by the frequency content of the input signal or vice versa. When the switch 121 is placed in position B, the output of the amplitude or frequency synchronized clock 116 is used to control the reversal of the display motion by causing the motion program counter 104 to reverse direction at a rate determined by the output signals provided from the command clock divider 117.

The portion of the audio input signals supplied at 101 is also coupled to an automatic gain control circuit 118 where the amplitude at all frequency ranges of the input signal is amplified to a uniform constant value. The output from the automatic gain control circuit 118 is supplied to a five channel translator 120 which is similar to that discussed with respect to FIG. 3. The five channel translator 120 serves to break down the signal into its five frequency band components which are used to control the color of the lights displayed on the four separate matrix displays of the system of FIGS. 4a and 4b. For this purpose the output signals from the five channel translator 120 are provided directly to the displays as well as to trigger and power control circuits 111, 112, 113 and 114.

Similarly the output signals from the automatic gain control circuit 118 is supplied to a shift direction and detection circuit 119 which is analogous to the corresponding circuit 57 previously discussed with respect to FIG. 3. The shift direction detection circuit 119 provides output logic levels which are supplied to a command divider 126 and to the motion program channel 104 via switch 121 if the switch 121 is placed in its position A. Thus by means of the shift direction detection circuit 119 the motion of the chosen display may be reversed depending on the frequency content of the audio signal input at 101. Similarly the contents of the display program counter 127 may be made to run in a reverse direction according to the frequency content of the audio signal input at 101.

Returning now to consideration of the switch 125 of FIG. 4b it will be recalled that if the switch is placed in any of the positions other than position A, that the display clock divider 123 outputs are manually selected by the switch 125. When the switch 125 is placed in position A, however, the contents of a divider clock PROM 129 places the display clock under program control. The contents of the display program counter 127 are, for this purpose, used to index the contents of the divider clock PROM 129. The contents of the memory location indexed by the display program counter 127 are provided to a 16 input and/or circuit 124 via a decoder circuit 130 and an inverter circuit 131. Simultaneously with this the output signals from the display clock divider 123 (which comprise a plurality of divided down values of the output of the clock pulses provided from the amplitude or frequency synchronized clock 103) are supplied to the 16 input and/or circuit 124. Thus, when the switch 125 is placed in position A the contents of the indexed memory location of divider clock PROM 129 determines which output from the display clock divider is provided to the clock input of display program counter 127 via switch 125. In this manner the rate at which the display patterns are changed on the four visual displays may be preprogrammed by whatever bit pattern is loaded into the memory locations of the divider clock PROM 129.

Referring now to FIG. 7 another embodiment of a visual display system in accordance with the concepts of the present invention is illustrated schematically. In the system of FIG. 7a particular display pattern, which is chosen according to the amplitude content of the input signal, is displayed from a motion register 218 for a duration controlled in a preprogrammed manner according to the contents of a duration memory PROM 216. This provides yet another dimension of programmable flexibility for deriving displays according to the concepts of the invention.

A portion of the audio signal input via line 211 is coupled through a band pass filter 212 to provide an amplitude dependent output signal. This output signal is coupled to an audio synchronized variable frequency clock oscillator 213 of the type discussed previously. Clock signals .phi.. from the clock 213 are supplied to a clock divider, multiplexer and latch circuit 214 and to a timing and delay control logic circuit 219.

The clock divider, multiplexer and latch circuit 214 has a clock divider circuit analagous to clock divider 123 of FIG. 4b and contains multiplexing and latch circuits necessary to interface MOS type and TTL type integrated circuitry to assure timing compatibility. Clock signals output from the clock divider 214 are supplied to an address counter 215 and to the timing and delay control logic circuit 219.

The address counter 215 is used to index a pattern memory PROM 217 and a duration memory PROM 216. The contents of the pattern memory PROM 217 are loaded via a data buss into a motion register 218, but can only be so loaded into the motion register 218 upon receipt of a mode control signal from the timing and delay control logic circuit 219. Such a signal cannot be generated by the logic circuit 219 until it receives a corresponding mode control signal from the clock divider, multiplexer and latch circuit 214, which generation is controlled by the contents of the current memory location indexed in the duration memory PROM 216.

The motion register 218 is a recirculating shift register which shifts one bit either left or right upon receipt of a motion clock pulse from the timing and delay pulse circuit 219. These pulses are supplied each time a .phi.. clock pulse is input from the variable frequency clock 213 to the timing and delay control logic circuit 219. The result of the aforedescribed sequence of signals is for a pattern to be selected from pattern memory PROM 217 which is loaded into motion register 218 and is held there for a time duration specified by the contents of the duration memory PROM 216. Motion of the displayed pattern is created by the generation of motion clock pulses from timing and delay control logic circuit 219 causing the motion register to circulate clockwise or counterclockwise under the control of a shift direction detection circuit 220. Shift direction detection circuit 220, automatic gain control circuit 224 and programmable frequency content selection logic circuit 221 all perform in an analogous manner to their counterparts described with respect to the previous Figures.

When the duration period supplied from the duration memory PROM 216 expires, the timing and delay control logic circuit 219 resets the latches of circuit 214, clear the clock register of circuit 214 and conditions the motion register 218 for reloading with the next addressed display pattern contained in pattern memory PROM 217.

For display purposes the output of the programmable frequency content selection logic circuit 221 and the motion register 218 are combined logically by the mask circuit 222 in the manner previously described with respect to the other Figures and supplied to the display device 223. It will be apparent to those of skill in the art that this system utilizing a motion register such as register 218 can be extended to a plurality of pattern and duration memory PROM's, if desired.

The programmable visual display system described in respect to FIGS. 4a and 4b provides much more versatility than the simple system described with respect to FIG. 1. However, both systems operated from a common principle. That principle is that the display pattern of lights may be determined in a preprogrammed pleasing manner according to the contents of a programmable read only memory. Options are provided for changing the direction of motion and the duration of a particular display pattern of the displays in several different manners according to the various embodiments of the invention which have been discussed herein. The amplitude or the frequency information carried on an input signal may be used for this purpose or separate free running clocks may be used for this purpose. Thus the systems described in the present application provide a great variety of ways of presenting and interpreting an audio input signal. Systems according to the present invention have artistic merit but also provide means for communicating the intelligence carried in the amplitude and frequency components of the input signal such that persons who may not respond to the input signal such as deaf persons to an audio signal may still have the beauty and intelligence of an audio signal such as a musical score provided to them by such systems.

To this point all of the display systems according to the invention which have been discussed have dealt with systems which could be used in response to an audio input signal. As previously stated the present invention, however, contemplates the use of other than audio input signals in forming visual display. One other such type of input signal which may be used for this purpose is a brain wave input signal. It has long been known that the brain produces electrical voltages which may be sensed by electrodes placed on the surface of the skull of an individual. These brain waves may be thought of as similar to low frequency audio signals. The frequency content of the brain waves emanated by the brain of an individual may vary according to the mood or state of relaxation or thought activity of such an individual. Extremely low frequency waves in the range of from 3 to 7 hz may be termed .theta. brain waves. Brain wves in the frequency range from 7 to 13 hz may be termed .alpha. brain waves and brain waves in the frequency range above 13 hz to approximately 35 hz may be termed .beta. waves.

The amplitude and frequency content of the brain waves of a subject reflect his state of mental activity and physical relaxation. Thus, a visual display device according to the concepts of the present invention, which is driven by the brain waves of a subject, could be usefully used by such a subject to obtain pleasing visual display patterns by the control of his thought patterns and physical relaxation. Thus, such a visual display device according to the concepts of the invention may be utilized to assist users to relax or to stimulate thought activities by providing visual displays which are keyed to either .alpha., .beta., .theta. brain wave activity. By learning to control the pattern provided by the visual display, such a subject may be able to reach states of physical and mental relaxation or activity in a controlled manner which would not be possible without the use of such a visual display device.

Referring now to FIG. 9, a transducer system is illustrated which is provided for detecting and amplifying to a useful level the .alpha., .beta., and .theta. brain waves for use in a visual display according to the present invention. An elastic headband member 401 is provided for encircling the skull of a user. The headband 401 may be comprised of elasticized cloth or the like, and has three electrodes 402, 403 and 404 attached thereto. Electrode 402 is situated on the elastic headband member 401 in such a manner as to be located on the right frontal lobe of the skull of the user. Electrode 403 is situated on the headband member 401 so as to be situated on the left frontal lobe of the skull of the user and electrode 404 is situated so as to be located on the rear or occipital lobe of the skull of the user. The electrodes 402, 403 and 404 are electrically insulated from each other by the material forming the elastic headband member 401. However, these electrodes are electrically coupled via a shielded cable 410 to an integrated circuit differential amplifier 405. The differential amplifier 405 and its associated circuitry serves to amplify the very low level brain wave signals picked up by electrodes 402, 403, and 404 to a more usable level. The output from the differential amplifier 405 is coupled via a load resistor R.sub.1 to an optosiolator circuit 406. The optoisolator circuit 406 is the same as that previously described with respect to the foregoing figures and is described in more detail in the applicant's prior U.S. patent. The signal is coupled from the optoisolator 406 via another amplifier stage 407 to a unity gain forth order low pass filter 408. The low pass filter 408 has an upper frequency limit cutoff of 35 hz and thus passes only the .alpha., .beta., and .theta. brain waves as detected by the electrodes 402, 403 and 404. The output of filter 408 is delivered across a load resistor 409, which could comprise a potentiometer is desired, to provide input to a visual display system of the type shown in FIG. 8.

Thus, the transducer circuitry of FIG. 9 provides low frequency alternating current electrical output in the frequency range under 35 hz which corresponds to the .alpha., .beta., and .theta. brain waves of the user. The brain wave signals are input to a visual display system in accordance with the concepts of the present invention which is illustrated in FIG. 8.

Referring now to FIG. 8 an embodiment of a visual display system for providing displays according to the brain wave pattern of a subject user is illustrated in schematic block diagram form. In FIG. 8 a particular display pattern which is chosen according to the amplitude or frequency content of one of either the .alpha., .beta. or .theta. brain waves present in the input signal is displayed from a motion register 308 for a time duration which is controlled in a pre-programmed manner according to the contents of a duration memory PROM 310. Logic circuits are provided in the system of FIG. 8 for shifting the direction of motion of the pattern according to yet another variable, to wit either the .alpha., .beta. or .theta. brain wave content of the user, and additionally the predominant display color is controlled according to the .alpha., .beta. or .theta. brain wave content of the user. This provides yet another dimension of programmable flexibility for deriving displays according to the concepts of the invention.

The input brain wave signals present on line 301 are coupled through a brain wave filter 302 to provide an amplitude dependent output signal which is supplied as input to a brain wave synchronized variable frequency clock 303. The brain wave synchronized variable frequency clock 303 is analogous to the amplitude synchronized variable frequency clocks in the previous figures. The brain wave filter 302 is a bandpass filter chosen to isolate either the .alpha., .beta. or .theta. brain wave present in the input signal as desired by the user in order to control the clock frequency. Clock signals .phi. from the clock 303 are supplied to a clock divider counter and multiplexer circuit 305 and to a delay timing and control logic circuit 304. The clock divider multiplexer circuit 305 is analogous to the clock divider 123 of FIG. 4b and clock divider 214 of FIG. 7. The delay timing and control logic circuit 304 contains multiplexing and latch circuits necessary to interface MOS type and TTL type integrated circuitry to assure timing compatibility between these two different types of integrated circuitry. Clock signals from the clock divider and multiplexer circuit 305 are supplied as input to an address counter 306. The address counter 306 is used to index the contents of a pattern memory PROM 307, a display selection memory PROM 311 and a duration memory PROM 310. The contents of the memory location of the pattern memory PROM 306 (from 1 to N bits) are loaded via a data bus into a motion register 308 which is analogous to the motion register 218 of FIG. 7. These contents can only be so loaded into the motion register 308 upon receipt of a mode control signal on line 304a from the timing and delay control logic circuit 304. Such a signal cannot be generated by the logic circuit 304 until it receives a corresponding mode control signal from the clock divider latch circuit 309. The generation of this control signal from the latch circuit 309 is controlled by the contents of the memory location which is indexed in the duration memory PROM 310.

The motion register 308 is a recirculating shift register which shifts one bit either to the left or to the right upon receipt of a motion clock pulse from the delay and timing pulse circuit 304. These pulses are supplied each time a .phi. clock pulse is input from the brain wave synchronized variable frequency clock circuit 303 to the timing and control logic circuit 304. The result of this sequence of signals is for a pattern to be selected from the pre-programmed memory contents of the patern memory PROM 307 which is loaded into the motion register 308 and is held there for a time duration specified by the contents of the indexed memory location of the duration memory PROM 310. Motion of the displayed pattern is created by the generation of motion clock pulses from the timing and delay control logic circuit 304 causing the motion register to circulate clockwise or counter-clockwise under the control of some shift direction and detection circuit which is connected via a switch 324 and supplied as input to the delay timing and control logic circuit 304. Different logic circuits may be selected by switch 324 for this purpose.

A second portion of the input brain wave signals on line 301 is supplied to a second .alpha., .beta. or .theta. brain wave filter 320 which is analogous to the filter 302 previously described. Generally the filter 320 would not be chosen to select the same brain wave component as the filter 302. For example, if it is chosen to pass .alpha. brain wave signals through the filter 302 then .theta. or .beta. brain wave signals would be passed through the filter 320 to control the direction of motion of the displays. In any event, the chosen brain wave component signal at the output of the filter 320 is supplied to a direction reversal rate clock 321. This clock provides output signals which control the rate of reversal of the display if so selected by the switch 324.

The output signals from the direction reversal rate clock 321 are supplied via a command clock divider 322 which is analogous to the type previously described with respect to the other figures and a divider switch 323 to the direction reversal selection switch 324.

Alternately, the brain wave input signals present on line 301 may be supplied to an automatic gain control circuit of the type previously described with respect to earlier figures. The output from this automatic gain control circuit 325 is supplied as input to a third .alpha., .beta. or .theta. brain wave filter 326. Brain wave filter 326 may be of the same type as that used for the brain wave filter 302 and 320 and previously described. However, again, if the filter 302 is chosen to select .alpha. brain waves the filter 326 would select .beta. or .theta. brain waves to control the display motion direction as desired. In any event, the output of brain wave filter 326 is supplied to a shift direction and detection circuit 327 which may be of the same type as that described previously with respect to the shift direction circuit 57 of FIG. 3. The output of the shift direction detection circuit 327 is also supplied to the selector switch 324. Thus, the selector switch 324 may be used to choose different types of criteria for switching the direction of motion of a chosen pattern in the motion register 308 according to different logic schemes.

When the duration period supplied from the memory location contents of pre-programmed duration memory PROM 310 expires, the timing and delay control logic circuit 304 resets the latches of latch circuit 309, clears the clock divider counter and multiplexer circuit 304, and conditions the motion register 308 for reloading with the next addressed display pattern contained in the pattern memory PROM 307.

The output of the automatic gain control circuit 325 is also supplied as input to a 1-N frequency channel translator circuit 328 which is used to select colors of display lights. It will be recalled that the output of the automatic gain control circuit contains all of the frequency content information of the input signals. The translator 328 to which this signal is supplied separates the frequency components of the signal input to it and provides a plurality of 1-N signals on output lines to control the predominant color of lights in the displays 316, 317, 318 and 319. Actually while only four such displays are illustrated in FIG. 8, it will be appreciated that as many frequency component signals as channels are provided in the 1-N channel translator 328 may be used as desired.

Referring now to FIG. 8b, one channel of the N channel analog to digital frequency translator 328 is shown in more detail. N such channels are provided in the translator circuit 328. The input signal is coupled to an active frequency filter 329 which comprises a bandpass frequency filter chosen to pass a particular band of frequencies as desired. The output from the active filter circuit 329 is connected to an intergrator circuit 331 via a rectifier and filter circuit 330. The integrator circuit 331 integrates the input signal supplied to it and provides an output signal to a comparator circuit 332 which provides either a zero output level or a desired logic level voltage output signal if its input exceeds a predetermined value. The logic level signal output from the comparator circuit 332 is coupled to a Schmitt trigger circuit 334 via an optoisolator circuit 333 of the type previously described. The Schmitt trigger 334 thus provides an output logic level if the input automatic gain control signal to the active filter 329 has an amplitude exceeding the predetermined value compared against by the comparator circuit 332. The logic level output from the Schmitt trigger circuit 334 for this particular channel of operation is thus coupled to the 1-N optical displays 316, 317, 318 and 319 which may be of the type described with respect to FIGS. 5a and 5b. Thus, the analog to digital frequency translator circuits 328 provide 1 to N digital logic level outputs to control the predominant colors of lights on the displays in accordance with the relative frequency content of the input brain wave signals.

For display purposes, the outputs of the analog to digital frequency translator circuit 328 and the motion register 308 are combined logically by mask circuits 312, 313, 314, and 315 in the manner previously described with respect to the other figures. These mask circuits are of the NAND mask logic type previously described with respect to the other figures. The contents of the addressed memory location in the display selection memory PROM 311 is thus masked against the contents of the motion register in the mask circuits 312, 313, 314 and 315 for this purpose. It will be apparent to those skilled in the art, that if desired, more than one motion register could be used. For example, there could be a separate motion register for each of the displays.

Referring now to FIG. 10 a visual display system having yet a further degree of flexibility for displaying the brain wave pattern of a user is illustrated schematically. The system of FIG. 10 is similar to that of FIG. 8 but has a yet further degree of flexibility available in that, rather than using a sequential address counter (such as address counter 306 of FIG. 8) for handling the pattern selection according to the amplitude component of the .alpha., .beta. or .theta. brain waves of the user, the pattern selection of the system of FIG. 10 is bored on the actual amplitude and/or frequency content of the brain waves input at line 501 of FIG. 10.

A component of the input signal at 501 after passing through a brain wave filter 502 (which is analogous to filter 302 of FIG. 8) is supplied to a sample and hold amplifier 434. The amplifier 434 samples this filtered input signal at a rate controlled by an analog to digital logic timing clock 431 which may comprise, for example, a free running oscillator operating at a frequency selected to provide a pleasing rate of change of display pattern. The sample and hold circuit 434, upon receipt of a clock pulse from clock 431 samples the voltage level amplitude of the output signal from filter 502 and supplies this voltage level as input to a 1-N bit analog to digital converter 432. The same voltage level is held by sample and hold amplifier 434 until receipt of the next clock pulse from the clock 431.

Analog to digital converter 432 digitizes the input voltage level supplied to it from sample and hold amplifier 434 and supplies an N bit binary output signal representative of this level to a 1-N binary latch circuit 433. The rate of operation of analog to digital converter 432 and the binary latch circuit 433 are also controlled by clock signals from the clock 431 so that synchronization of sample and hold amplifier 434, analog to digital converter 432 and latch 433 are assured.

Simultaneously with this operation of converting the amplitude of the output of filter 502 to digital form, the output of filter 502 is used to control the frequency of operation of a brain wave synchronized clock divider and multiplexer 505 (analogous to clock divider and multiplexer 305 of FIG. 8) via brainwave synchronized clock 503, delay timing and control logic circuit 504, and latch 509 which are analogous to their respective counterparts in FIG. 8. The output of the binory latch 433 or the output of a 1-N bit analog to digital frequency translator 428 (analogous to analog to digital frequency translator 328 of FIG. 8) is thus strobed into a 1-N bit address latch 430 at a rate controlled by the clock divider and multiplexer circuit 505. The address (1-N bit binary number) thus supplied, is used to index a pattern memory 506, a display selector memory 511 and a duration memory 510 in a manner analogous to that described with respect to FIG. 8.

The remaining circuit components of FIG. 10 operate in a manner analogous to their counterparts as described with respect to FIG. 8. It should be mentioned in this regard that displays 416, 417, 418 and 419 of FIG. 10 and displays 316, 317, 318 and 319 of FIG. 8 could be CRT or video displays, if desired, as well as the discrete light displays described previously.

Thus, the embodiment of the visual display system of FIG. 10 utilizes either the amplitude or frequency content of the input brainwaves to select the visual display pattern, color, duration of display and shift direction of motion of its visual display. Used as a feedback system with a user observing it, such a system can perform to induce controlled thought patterns to create visual displays as a function of mood or thought activity of the user.

It may thus be seen that by using a visual display system according to FIGS. 8 or 10, that the brain wave content of the subject user may be separated into various frequency components and these components used to choose, in a pre-programmed manner, visual display patterns, the motion of these patterns, the shift of direction of the motion of the patterns, and the predominant color of the displays. Thus, a user equipped with such a system can utilize the system to produce desired patterns by varying his thought process in a manner to produce the desired pattern result. Thus, heightened brain activity or lessened brain activity may be achieved through the use of such a visual display system as a feedback link to the user.

It will be appreciated by those skilled in the art that many changes and modifications could be made to the embodiments shown and discussed without departing from the true spirit and scope of the invention. It is therefore the aim of the appended claims to cover all such changes and modifications as would be apparent to those skilled in the art.