Method for Automatically Equalizing the Delay Characteristics of a Transmission Line

The present invention relates to a method for equalizing the delay characteristics of a circuit, in particular, relates to a method for adjusting the delay equalization characteristics of an equalizer having a plurality of quadratic all pass networks on a frequency axis.

A delay equalizer which has a plurality of quadratic all pass networks on a frequency axis and obtaining the desired delay characteristics from the total of said all pass networks is well known. That is to say, N number of quadratic all pass networks having the delay characteristics .tau..sub.1, .tau..sub.2, --- .tau..sub.n are arranged in the band width, and the total delay characteristics H is obtained from the sum of .tau..sub.1, .tau..sub.2, ---- and .tau..sub.n.

However, said prior art has the disadvantage that the adjustment of each all pass network is very difficult, since said adjustment had to be accomplished manually and the desired characteristics of a particular all pass network depends upon the characteristics of the other all pass networks. Therefore, the total characteristics of the delay equalizer depend upon the experience and the sixth sense of an operator, and further the resultant characteristic is not always the best one.

It is an object, therefore, of the present invention to overcome the disadvantage and limitation of a prior delay equalizer by providing a new and improved method for adjusting an equalizer.

The above and other objects are attained by a method for adjusting an equalizer which comprises the steps of measuring the delay of the circuit to be equalized at the center frequencies of a plurality of quadratic all pass networks, obtaining the delay characteristics of eqch quadratic all pass networks, and obtaining the value of Q of each quadratic all pass networks through the asymptotic formula, ##EQU2## WHERE Q.sub.i.sup.k is the value of Q of the i'th quadratic all pass network after k'th adjustment cycle, and .alpha..sub.i is the step size parameter of i'th quadratic all pass network.

The foregoing and other objects, features, and attendant advantages of the present invention will be appreciated as the same become better understood by means of the following description and the accompanying drawings wherein;

FIG. 1 shows a curve showing the individual characteristics of a plurality of quadratic all pass networks and the total characteristics of the same,

FIG. 2(A) and FIG. 2(B) show embodiments of circuit diagrams of a quadratic all pass network;

FIG. 3 shows the embodiment of the delay equalizer according to the present invention; and

FIG. 4 shows the block-diagram of the equalizer control 4 in FIG. 3.

First, the theoretical principle of the present invention will be explained below.

The basic quadratic all pass network utilized in the present invention must change the resonance characteristics, that is to say, the value of Q of the circuit, by changing a value of a resistance and/or a capacitance included in the circuit of the all pass network. And as long as said condition is satisfied, any configuration of an all pass network is possible. In any configuration the quadratic all pass network function is shown in the formula (1) below. ##EQU3## where

V.sub.1 ; input voltage

V.sub.2 ; output voltage

S; complex frequency

Q; Q of the quadratic all pass network

.omega..sub.o ; center frequency in .omega. of the quadratic all pass network

From the formula (1), the delay characteristic is obtained as shown in the formula (2). ##EQU4##

The formula (2) shows the delay characteristics of each quadratic all pass network .tau..sub.1, .tau..sub.2, ----, .tau..sub.n shown in FIG. 1. According to the present invention, the value of Q of each quadratic all pass network is obtained from the N number of discrete delay information measured in the circuit to be equalized. Now, the formula (2) can be changed as follows by introducing the suffix (i). ##EQU5##

In the formula (3), the center frequency is supposed to be a constant having the sequence number of the frequency axis, since if the center frequency changes, the circuit becomes complicated and many resistances and capacitances must be adjusted.

Although many theories for solving the function Q.sub.i are applicable, the steepest descent method is the most desirable, since the delay characteristics and the differential characteristics of the same are obtained analytically. The steepest descent method is defined in the formula (4). ##EQU6## where .alpha..sub.i is the step size parameter, the suffix k shows the repetition number (number of adjustment), and .epsilon. is the error.

The formula (5) is defined as the evaluation function by introducing the square errors. In the formula (5), the suffix k is omitted for the sake of simplicity. ##EQU7##

In the formula (5), H(Q).vertline..omega.=.omega..sub.j means the sampling of the function HC(Q) at .omega.=.omega..sub.j, and H(Q).vertline..omega.=.omega..sub.j is shown below considering the correlation of the basic circuits. ##EQU8## y.sub.i in the formula (5) is the sampled value of the desired delay characteristics, and y.sub.i is the constant during the repetition cycle after the measurement. The center frequency in radians of the basic circuit is usually the same as the sampled frequency in radians of the delay characteristics, however, it is not necessarily the same. Further, the accuracy of equalization can be improved by setting more sampled points than the number of basic circuits.

The formula (7a) is obtained by differentiating the formula (5) by Q.sub.i. ##EQU9##

The (i, j ) element in the matrix in the formula (7a) is shown in the formula (7b). ##EQU10##

Accordingly, the formulas (7a) and (7b) give the slope of the error .differential..epsilon./.differential.Q.sub.i utilized to solve the formula (4).

Now, the step size parameter .alpha..sub.i will be explained. 1/.omega..sub.oi in the formula (7b) is independent from the direction of the error shown by the change of Q.sub.i. Accordingly, .alpha..sub.i is expressed as follows in order to cancel the same by .alpha..sub.i in the formula (4).

where .alpha. is the constant. It is a matter of course that the value 1/.omega..sub.oi in the formula (7b) and the value .omega..sub.oi in the formula (8) which are cancelled by each other are removed beforehand in the actual calculation.

Further, in the present equalizer, since the center frequency .omega..sub.o of each quadratic all pass network is different from the others, the ratio of the change of phase to the change of the value Q.sub.i is different in each phase shifter. Therefore, in order to obtain the uniform average change ratio of the phase, the change of the value Q.sub.i must have the weight, thus said value .alpha..sub.i has the weight .omega..sub.oi /.omega..sub.ol.

The desired value of Q in each circuit is obtained by adjusting the circuits repetitively until Q.sub.i.sup.(k+1) becomes almost equal to Q.sub.i.sup.k. And by setting each quadratic all pass network according to the value Q thus obtained, the desired delay equalization characteristic is obtained.

Now, the apparatus according to the present invention will be explained with reference to the drawings.

The all pass network utilized in the present invention is shown in FIGS. 2(A) and 2(B). FIG. 2(A) is an embodiment of a quadratic all pass network using an operational amplifier. The transfer function of the circuit in FIG. 2(A) is shown below and the value Q of the circuit can be adjusted by changing either the value of the resistance R.sub.A or R.sub.B. ##EQU11## where, Q = r - 4.rho., .rho. = R.sub.B /R.sub.A, .omega..sub.o = 1/RC, and r is constant.

FIG. 2(B) is another embodiment of a quadratic all pass network using an operational amplifier. The transfer function of the circuit FIG. 2(B) is given by the formula (9).

FIG. 3 is a circuit diagram of the present delay equalizer. According to the present invention, the switches SW1, SW2, SW3 and SW4 are so set that the movable contacts are connected to the fixed contacts (a) at first. The signal generated in the test signal generator 1 is applied to the delay mesuring apparatus 3 through the transmission circuit 2, and the apparatus 3 measures the value of the delay in the transmission circuit 2 at a plurality of frequencies which coincide with the center frequency .omega..sub.oi in each basic all pass network. However, it should be noted that the measured frequency does not need to coincide exactly with the center frequency of each all pass network, as explained before. The measure values are stored in the equalizer control 4, which receives also the initial setting value, the setting value of the equalization width, and .alpha.. Said initial setting value is applied to the equalizer to be adjusted 6 through the gate circuit 5, and then the variable resistors in the equalizer 6 are initially adjusted to said initial setting value. Then, the delay characteristic of the equalizer thus initially adjusted is measured by the test signal generator 7 and the delay measuring apparatus 3. The measured values are stored in the shift-register in the equalizer control 4. Next, the equalizer control 4 provides the information for defining the value Q of each basic all pass network, and said information is applied to the equalizer 6 through the gate circuit 5, and thus the resistors in each basic circuit are adjusted and the first adjustment of Q.sub.i (that is to say, Q.sub.i.sup.(1)) is finished. Next, the test signal generator 7 provides a test signal to the equalizer 6 in order to measure the delay characteristics of the equalizer 6 after the initial adjustment, and the equalizer control 4 receives the revised information concerning Q.sub.i.sup.(2) and adjusts the equalizer 6 again. The adjustment cycle explained above is repeated until the equalization characteristics of the equalizer 6 reaches approximately the inverse characteristics of the transmission line, and the adjustment operation is finished when the error between the actual characteristics of the equalizer and the desired inverse characteristics of the transmission line reaches an allowable small value. Next, the switches SW1, SW2, SW3 and SW4 are switched to the contacts (b), then the equalizer 6 is connected to the transmitter 8, the transmission line 2 and the receiver 9, and the actual signal transmission starts.

FIG. 4 shows the detailed block-diagram of the equalizer control 4 in FIG. 3.

The switch 5 is connected to the contact (c) when the test signal is transmitted from the transmission station through the transmission line 2 (FIG. 2). Accordingly, the measured value concerning the characteristics of the transmission line by said test signal is applied to the shift register 10 and the minimum value detector 11. The output of the shift register 10 provided in sequence is applied to the subtractor 12, which subtracts the output of the minimum value detector 11 from the output of the shift-register 10. Thus the output of the shift-register 10 is normalized. The output of said subtractor 12 is subtracted in another subtractor 13 from a predetermined equalization duration and the output of the subtractor 13 provides the inversed delay characteristics. The output of the subtractor 13 is applied to the memory 16 through the clipper 14 and the auxiliary delay circuit 15, and is stored in the memory 16. The clipper 14 changes the negative outputs of the subtractor 13 to zero, and the auxiliary delay circuit 15 provides a predetermined delay to the output of the clipper 14. It should be appreciated that the value stored in the memory 16 is the equalization characteristic y.sub.i. The auxiliary delay circuit 15 facilitates the rapid convergence of Q.sub.i of each basic circuit by providing a predetermined delay to the inverse characteristic. Said auxiliary delay is usually inversely proportional to the equalization duration.

When all the equalization characteristics y.sub.i are stored in the memory 16, the switch 5 is connected to the contact (d) and the switches 6 and 7 are switched to the contacts (e). When the initial value Q.sub.i.sup.(1) is applied to the input terminal 17 from the outside apparatus, said initial value is applied to the Q-R convertor 18 through the switch SW7 and to the shift register 20 through the switch SW6 to adjust the value of R.sub.A. The output of the Q-R convertor 18 is applied to the equalizer 6 (FIG. 2) through the output terminal 19. When the variable resistors in the equalizer 6 are initially adjusted as explained above by the initial adjustment Q.sub.i.sup.(1), the characteristic of the equalizer is measured and the result of the measurement is applied to the shift register 22 through the input terminal 21 and the switch SW5. Said result applied to the shift register 22 is ##EQU12## explained above. At this point, the switches SW6 and SW7 are connected to the contacts (f). Now, the content of the memory 16 and the content of the shift register 22 are applied to the subtractor 23, the output of which relating to ##EQU13## is applied to one input of the multiplier 24. On the other hand, the output of the shift register 20 having the initial value Q.sub.i.sup.(1) is also applied to the other input of the multiplier 24 through the differential matrix calculator 25, which provides the differential matrix in the formula (7a). The output of the shift register 20 is also applied to the delay circuit 26. The output of the multiplier 24, which is the product of the output of the subtractor 23 and the output of the differential matrix calculator 25, is multiplied by a constant in the multiplier 27, the output of which is ##EQU14## in the formula (4). Since the output of the delay circuit 26 is Q.sub.i.sup.(1) the subtractor 28 provides the right side of the formula (4). The clipper 29 changes the negative output of the subtractor 28 to zero. It should be noted that the output of the clipper 29 is Q.sub.i.sup.(2), and this output is applied to the equalizer 6 in FIG. 3 through the Q-R convertor 18 and the output terminal 19. The output of the clipper 29 is also applied to the shift register 20 for the next repetition cycle.

As explained above, according to the present invention, when the initial value is set, the adjustment of the equalizer is automatically accomplished, and the solution Q.sub.i.sup.(2), Q.sub.i.sup.(3), . . . , Q.sub.i.sup.(k) is obtained sequentially, and finally the goal solution Q.sub.i.sup.(k) is obtained.

The structure of the Q-R convertor 18 in FIG. 4 depends upon the configuration of the basic quadratic all pass network, and it should be appreciated that said structure of the Q-R convertor is usually simple, since the value Q of a quadratic all pass network is obtained by Q=f(R.sub.A) as the function of a variable resistance R.sub.A and is obtained through a simple addition and/or subtraction. For instance, Q=r-4(R.sub.B /R.sub.A) for the circuit of FIG. 2(A).

The test signal generator 7 in FIG. 3 is necessary when the value H(Q).vertline..omega.=.omega..sub.j is obtained through the measurement. However, it should be noted that said test signal generator 7 can be omitted if said value is obtained through the calculation according to the formulas (3) and (6).

As explained above in detail, according to the present invention, the desired value of Q of each quadratic all pass network is automatically obtained, and the equalization characteristic is easily adjusted. Thus, the present invention has the effects that the operation of the adjustment of an equalizer is simplified and the accuracy of the adjustment is improved. Further, the steepest descent method used in the present invention through the analysis of the delay characteristics of a quadratic all pass network and the differential of the same simplifies the structure of the apparatus.

From the foregoing it will now be apparent that a new and improved equalization adjustment has been found. It should be understood of course that the embodiments disclosed are merely illustrative and are not intended to limit the scope of the invention. Reference should be made to the appended claims, therefore rather than the specification as indicating the scope of the invention.