Switch for Fault Tolerant Bubble Domain Memory Systems

FIG. 1 is a diagramatic representation of a switch which specifically includes a conductor arrangement related to separate magnetic bubble domain propagation paths.

FIG. 2 is a schematic representation of a magnetic bubble domain serial memory system which incorporates the subject invention therein.

Referring now to FIG. 1, there is shown a detailed diagram of the switch of the subject invention. The switch which can be termed an antiexchange switch, is utilized with a magnetic bubble domain system. The system comprises a first propagation path 20 which extends from location A to location C. A second propagation path 21 extends from location D to location B. Another propagation path 14 extends from a location adjacent to path 21 to merge 12 wherein paths 14 and 20 are joined. Similarly, path 15 extends from a location adjacent to path 20 to merge 13 wherein paths 15 and 21 are joined. The propagation paths can be provided in virtually any known manner. For example, chevrons, assymetric chevrons, T-bars, gapless devices or the like, can be utilized to form the path elements.

Arrows 22 and 23, respectively, represent transfer devices such as, but not limited to, dollar sign ($) switches or the like which selectively transfer information (i.e. magnetic bubble domains) from path 20 to path 15 (arrow 22) or from path 21 to path 14 (arrow 23). A conductor is provided to control the operation of transfer devices 22 and 23. The conductor includes conductor portions 10 and 11 which can be considered to be portions of the basic conductor. Correction loop C1 is connected between conductors 10 and 11 to provide one conductive path therebetween. In addition, a further, complex loop CS is connected electrically in parallel with correction loop C1. Complex loop CS includes transfer loop T1 which is disposed adjacent to transfer element 22 and transfer loop T2 which is disposed adjacent to transfer element 23. The combination of transfer element 22, transfer loop T1 and the adjacent portions of paths 20 and 15 collectively describe switch S1. Similarly, transfer element 23, transfer loop T2 and the adjacent portions of paths 21 and 14 collectively form switch S2.

It should be emphasized that each of the transfer switches S1 and S2 consists of a one way transfer switch. Together the switches function as an exchange switch pair. In the instant invention, the double switch arrangement causes paths P1 and L1 to be connected in series when the switches are not activated. Conversely, paths P1 and L1 are separated from each other when switches S1 and S2 are both activated.

The switches are arranged to operate at a current level I. That is, when a current I passes through transfer loops T1 and T2, a sufficient magnetic field is generated so that switches S1 and S2 are activated. However, with correction loop C1 connected, as shown, in FIG. 1, the current I applied to conductor 10 is divided through the conductor loops C1 and CS and a current which is smaller than I is applied to loop CS. With correction loop C1 intact, switches S1 and S2 can be activated only if the current in conductor 10 is raised to I.sub.2 = kI, where k is the resistance ratio between the conductor loops CS and C1. The value of k can be designed to be any value greater than 1, dependent upon the sensitivity desired in the circuit. The current I.sub.2 is useful during testing as described hereinafter. In the event that correction is required, also described hereinafter, correction loop C1 can be removed by any method, such as etching, laser scribing or the like. So long as any portion of loop C1 is removed whereby loop C1 is broken, as suggested by dashed lines 30, the electrical short circuiting effect of loop C1 is removed and the current I is supplied via conductor 10 to loop CS and, thus, to transfer switches S1 and S2, respectively.

Inasmuch as current I is defined as being sufficient to cause transfer switches S1 and S2 to be active (when loop C1 is broken) bubbles propagating along path P1 from A are transferred from path 20 to path 15 via transfer element 22 and thence via merge 13 to path 21. Conversely, bubbles propagating along path 21 are transferred via transfer element 23 to path 14 and, thence, via merger 12 to path 20. These transfers occur in response to current I in conductor 10. Thus, loop L1 and path P1 are totally separate. Consequently, information propagates from location A to location B and from location D to location C.

Conversely, if correction loop C1 has not been altered (i.e. indicative of no defect in loop L1) current I in conductor 10 is split between loops C1 and CS. The resultant current (<I) through transfer loops T1 and T2 is insufficient to render switches S1 and S2 active. Consequently, information propagating along path P1 (or path 20) propagates from location A to location C. In addition, information propagating from location D propagates along path 21 to location B. Consequently, path P1 and loop L1 are connected in series.

Referring now to FIG. 2, there is shown an implementation of the subject invention into a memory system. In this system, a plurality of loops L1, L2, . . . LP, LP+1, . . . LN are provided. Each of these loops includes a switch of the type described in FIG. 1. A major propagation path P1 is defined. Signal source 50 provides a current signal I along conductor 10. Annihilator A, generator G and detector D are shown. These elements are typical and the interaction thereof in the system is also typical and well known.

In the event that a system as shown in FIG. 2 is fabricated without any defects, a bubble generated by generator G passes through propagation path P1 and then, through loops L1, L2 and so forth through to loop LN, consecutively, wherein a large-scale series memory is provided. On the other hand, if a defect is noted in any one or more of loops L1 through LN, the defective loop is removed from the system through the simple expedient of removing the appropriate correction loop C1, C2 . . . CN. As noted, above, if correction loop C1 (through CN) is not removed, current I in conductor 10 is split so that the switches S1 and S2 (see FIG. 1) are not active and the storage loop is included in the system. If the correction loop C1 (through CN) is removed, the associated switches S1 and S2 are active and the associated storage loop is removed from the circuit.

Testing for the defective minor loop such as L1, L2, and the like can be effected by applying a current I2 to the system with the appropriate information being propagated therethrough. The test procedure is typical of other testing arrangements.

Thus, there has been shown and described an improved memory system with fault tolerant capability. The full data rate is maintained on the chip even though defective loops are removed. That is, dead space is not inflicted on the information stream. The physical location of the minor loop does not affect the data structure or the data throughput and, therefore, provides more flexibility in the chip design layout. In addition, even though the minor loops are all accessed by switches, most of the switches are short circuited and only those switches corresponding to the defective or redundant loops are active. Therefore the driver requirement in this arrangement is not as critical as in prior major/minor loop chip organizations. In addition, the transfer switch line will, preferably, be pulsed in synchronism with the in-plane rotating field wherein timing control is maintained in a relatively simple manner. The large scale memory systems provided by this invention are highly desirable. Those skilled in the art will conceive of modifications to the specific details shown and described. However, any such modifications which fall within the purview of this description are intended to be included therein. That is, this description is intended to be illustrative only and not to be limitative. The scope of the application is limited only by the claims appended hereto.