Power Transistor Including a Sense Emitter and a Reference Emitter for Enabling Power Dissipation to Be Limited to Less Than a Destructive Level

This application is related to applicant's co-pending application entitled "System for Limiting Power Dissipation in a Power Transistor to Less Than a Destructive Level" filed on Sept. 16, 1977, application Ser. No. 833,736.

The present invention generally pertains to a system for limiting power dissipation in a power transistor to less than a destructive level.

Destructive secondary breakdown in a power transistor occurs when the power being dissipated by the power emitter causes the temperature of the emitter to rise to a destructive level. The destructive power dissipation level in a power transistor is not easily calculated and/or may vary considerably between power transistors even though they have the same nominal power rating. To prevent destruction of power transistors it has been necessary to rate the operation of power transistors considerably below their capabilities.

The present invention provides a power transistor having a structure that enables it to be used in a system for limiting the power dissipation of the power transistor to less than a destructive level. The power transistor of the present invention includes a base; a power emitter in the base; a sense emitter positioned in the base sufficiently close to the power emitter for enabling the temperature of the power emitter to be indicated as a function of the voltage across the junction of the base and the sense emitter; and a reference emitter positioned in a base at a remote position that would not be heated by the heat dissipated by the power emitter for enabling the temperature at the remote position to be indicated as a function of voltage across the junction of such base and the reference emitter. Accordingly, the power dissipation of the power transistor can be limited to less than a destructive level in response to sensing a voltage difference proportional to the temperature gradient between the remote position and the power emitter induced by power dissipated in the power emitter. This voltage difference can be sensed between the sense emitter and the reference emitter. The reference emitter is positioned in either the same base as the power emitter or in a second base of the power transistor.

Additional features of the present invention are discussed in the description of the preferred embodiment.

FIG. 1 is a schematic representation of one preferred embodiment of a power transistor according to the present invention.

FIG. 2 is a schematic representation of an alternative preferred embodiment of a power transistor according to the present invention.

FIG. 3 is a schematic representation of another preferred embodiment of a power transistor according to the present invention.

FIG. 4 is a schematic representation of still another preferred embodiment of a power transistor according to the present invention.

FIG. 5 is a schematic representation of yet another preferred embodiment of a power transistor according to the present invention.

FIG. 6 is a schematic circuit diagram of a system for limiting power dissipation in power transistor of the present invention to less than a destructive level.

FIGS. 1 through 5 inclusive schematically illustrate various embodiments of power transistors in accordance with the present invention. The power transistor of FIG. 1, includes a collector 12, a base 14 in the collector 12 and a power emitter 16 in the base 14. For the sake of clarity of illustration, conductors to collector, base and emitter terminals and the contacts by which such conductors are joined to the collector, base and emitter are not shown in the drawing.

The power transistor of FIG. 1 further includes a sense emitter 18 and a reference emitter 20, both in the base 14. The sense emitter 18 is distributed around the power emitter 16 and is sufficiently close to the power emitter 16 to enable the highest instantaneous temperature at any part of the periphery of the power emitter 16 to be indicated as a function of the voltage across the junction of the base 14 and the sense emitter 18. The reference emitter 20 is positioned in the base 14 at a remote position 23 that would not be heated by the heat dissipated by the power emitter 16 for enabling the temperature at the remote position 23 to be indicated as a function of the voltage across the junction of the base 14 and the reference emitter 20.

The power transistor of FIG. 2 is constructed in the same manner as the power transistor of FIG. 1, except that the reference emitter 20 is in a second base 22 that is separate from the base 14. Both the base 14 and the second base 22 are in the collector 12. The reference emitter 20 is positioned in the second base 22 at a remote position 23 that would not be heated by the heat dissipated by the power emitter 16 for enabling the temperature at the remote position 23 to be indicated as a function of the voltage across the junction of the second base 22 and the reference emitter 20.

The power transistor of FIG. 3 is constructed in the same manner as the power transistor of FIG. 1, except for the provision of a sense emitter 24 instead of the sense emitter 18. The sense emitter 24 is positioned adjacent the power emitter 16. The sense emitter 24 is sufficiently close to the power emitter 16 to enable the temperature of the power emitter 16 to be indicated as a function of the voltage across the junction of the base 14 and the sense emitter 24.

The power transistor of FIG. 4 differs from the power transistor of FIG. 1 in that a plurality of power emitters 26 are contained in the base 14 and a sense emitter 28 is distributed around and between the power emitters 26. The sense emitter 28 is positioned sufficiently close to each of the power emitters 26 to enable the highest instantaneous temperature at any part of the peripheries of the power emitters 26 to be indicated as a function of the voltage across the junction of the base 14 and the sense emitter 28. The power emitters 26 are connected to a common power emitter terminal (not shown).

The transistor of FIG. 5 differs from the power transistor of FIG. 4 in the same manner that FIG. 2 differs from FIG. 1. The reference emitter 20 is in a second base 22, which is separate from the base 14.

A system for limiting power dissipation in a power transistor according to the present invention to less than a destructive level is shown in FIG. 6. This system utilizes a power transistor 30. The power transistor 30 includes a power emitter e.sub.p, a sense emitter e.sub.s and a reference emitter e.sub.r. The power emitter e.sub.p has a large power dissipation; and the sense emitter e.sub.s and the reference emitter e.sub.r both are operated at low power.

By sensing the voltage difference between the sense emitter e.sub.s and the reference emitter e.sub.r, an indication is provided of the temperature gradient between the remote position 23 and the power emitter e.sub.p induced by the power dissipated in the power emitter e.sub.p. The power emitter e.sub.p, the sense emitter e.sub.s and the reference emitter e.sub.r are matched for emitter-base voltage-temperature characteristics as a consequency of being manufactured at the same time. Therefore with equal current densities in the sense emitter e.sub.s and the reference emitter e.sub.r, the voltage difference between the sense emitter e.sub.s and the reference emitter e.sub.r is zero volts when no power is being dissipated in the power emitter e.sub.p. However, once power is dissipated in the power emitter e.sub.p, both the power emitter e.sub.p and the sense emitter e.sub.s are heated and the voltage V.sub.be across the junction of the base and the sense emitter e.sub.s decreases. However the reference emitter e.sub.r is positioned at a remote position that would not be heated by the heat dissipated by the power emitter e.sub.p ; so that the voltage V.sub.be across the junction of the base and the reference emitter e.sub.r remains relatively constant as the power emitter e.sub.p is heated. Thus as the temperature of the power emitter e.sub.p increases due to power dissipation in the power emitter e.sub.p the voltage difference between the sense emitter e.sub.s and the reference emitter e.sub.r also increases. This voltage difference is proportional to the temperature gradient between the power emitter e.sub.p and the remote position 23 induced by the power dissipated in the power emitter e.sub.p.

A differential amplifier 32 has its input terminals respectively coupled to the sense emitter e.sub.s and the reference emitter e.sub.r for sensing the voltage difference between the sense emitter e.sub.s and the reference emitter e.sub.r. The negative input terminal of the differential amplifier 32 is connected to the sense emitter e.sub.s, and the positive input terminal of the differential amplifier 32 is connected through a bias voltage source E to the reference emitter e.sub.r. The output terminal of the operational amplifier 32 is connected through a diode D to the base of the power transistor 30.

Drive current to the base of the power transistor 30 is provided from a current source I. The bias voltage source E has a predetermined voltage corresponding to a predetermined temperature gradient indication level. The bias voltage source E biases the differential amplifier. When the voltage difference between the sense emitter e.sub.s and the reference emitter e.sub.r reaches this predetermined voltage, the output of the differential amplifier 32 becomes negative, thereby reducing the drive current to the base of the power transistor 30 from the current source I. Accordingly the power provided to the power transistor 30 is reduced and the power dissipation in the power transistor is limited from increasing.

Since it is known at what temperature levels power transistors may be destroyed, the predetermined bias voltage of the bias voltage source E is selected to correspond to a temperature gradient indication level that enables the system of FIG. 6 to limit the power dissipation in the power transistor 30 to less than a destructive level.

The system of FIG. 6 is the subject of applicant's co-pending application filed on Sept. 16, 1977, application Ser. No. 833,736, cross-referenced hereinabove.