US 4,132,898 AGrant
Overlapping Boundary Electron Exposure System Method and Apparatus
Issue Date:1979-01-02
•18 Claims
•7 Drawing Sheets
Abstract
An electron beam exposure apparatus and method for use in fabricating semiconductor devices. A chip pattern larger in area than the electron beam scan field is divided into and exposed in a number of smaller parts (called partitions). The work piece on which the chip pattern is to be formed is moved relative to the scan field to enable each partition to be individually scanned at a different work piece position. The scan field, with the work piece positioned to scan one partition, overlaps onto and establishes a boundary region on an adjacent partition. Portions of chip patterns which lie in a boundary region are selectively scanned in connection with one or another of the abutting partitions. Portions of chip patterns falling in the boundary regions are selected for scanning in one or the other of adjacent partitions so as to minimize the number of divisions and so as to avoid dividing the pattern along critical dimensions.
Metadata
Assignee
- Fujitsu Limited
Inventors
- Fred K. Buelow
- John J. Zasio
- Laurence H. Cooke
Application Information
Application Number:US 8474761
Filing Date:1977-11-01
Priority Date:1977-11-01
Art Unit:256
Classifications
IPC:
A61K 2702
Field of Search:
250492 A
Patent Drawings (7 sheets)
Description
CROSS REFERENCE TO RELATED APPLICATIONS
ELECTRON BEAM SYSTEM, Ser. No. 847,485, filed Nov. 11, 1977, invented by Fred K. Buelow and John J. Zasio and assigned to the assignee of the present invention.
BACKGROUND OF THE INVENTION
This invention relates to the fabrication of microminiature devices and, more particularly, to an automated, high-speed electron beam apparatus and method for making such devices.
It has long been known that the high-resolution and excellent depth-of-focus capabilities of an electron beam make it a practical tool for inclusion in an automated system for making microminiature electronic devices. The electron beam is controlled in a highly accurate and high-speed manner to expose an electron-resist-coated material as a step in the fabrication of extremely small and precise low-cost integrated circuits.
Although an electron beam can be deflected and blanked in a high-speed manner, the scan area over which the beam is capable of being accurately deflected is relatively small. A basic problem presented, therefore, is how to utilize an electron beam which has a small-area scan field to rapidly and accurately expose relatively large chip pattern areas.
In addition to the need for exposing large areas, large densities of circuits are desired on semiconductor chips. The trend in the industry has been towards a greater number of circuits per unit of area and towards smaller circuit elements. With this trend, it has become increasingly possible to integrate an entire system or subsystem on one or a relatively few number of semiconductor chips.
In order to accommodate the greater density of circuits and to obtain the accuracy required for smaller circuit elements, electron beam systems are employed to scan chip patterns or portions of chip patterns each covering an area which is equal to or less than the scan field area which can be accurately scanned by the electron beam.
When the chip pattern to be scanned covers an area greater than the area which can be accurately scanned by the electron beam, the chip pattern is divided into partitions where each partition has an area which is small enough to fit within the scan field of the electron beam. The partitions are then scanned one at a time. After scanning each partition, the work piece (wafer or other material to be scanned) is moved so that the electron beam scan field is relocated for scanning the next adjacent partition. In this manner, the entire chip pattern is scanned one partition at a time.
In order that the composite chip pattern be accurately scanned, each partition must be accurately scanned. Furthermore, adjacent partitions must be properly aligned (that is, properly registered) with respect to each other. Failure to have proper registration means that circuit elements crossing the boundry between partitions will be misaligned. This problem of partition alignment is a problem of registering the electron beam scan field on the work piece each time the work piece is moved.
Problems arise in connection with the registration of the scan field particularly when circuit elements having critical dimensions are located at or near the boundary between adjacent partitions. If a circuit element having a critical dimension is located across a partition boundary, portions of the circuit element will normally be scanned at two different times with two different positions of the work piece relative to the electron beam scan field.
If the electron beam scan field position at one location of the work piece is misaligned relative to its position at an adjacent position of the work piece, then an error due to the misalignment will be introduced into the scanning of the circuit element crossing the boundary. If the magnitude of the misalignment is large with respect to critical dimensions of the circuit element being scanned, the circuit element will be significantly malformed.
The problem of how to accurately register and reregister the scan field on a work piece is well known. Many different solutions for this problem have been proposed and have been employed with various degrees of success. Many of these solutions employ alignment marks within each partition for use in connection with registering the scan field when the work piece is moved. While the use of alignment marks in various forms is useful and desirable, there is still a need for an improved method and apparatus for avoiding the problems caused by misalignment of adjacent partitions.
In accordance with the above background of the invention, it is an object of the present invention to provide an improved electron beam apparatus and method for successively scanning smaller partitions to form a larger composite chip pattern.
SUMMARY OF THE INVENTION
The present invention is an electron beam apparatus and method for scanning a chip pattern. The chip pattern is divided into partitions, each smaller than the overall chip pattern. Also, each partition is smaller than the scan field of the electron beams. The partitions are scanned by the electron beam one at a time so that the overall chip pattern is formed as a composite of the individual partitions. A work piece on which the chip pattern is to be scanned is moved to a different position relative to the electron beam scan field each time a different partition is to be scanned.
Since the scan field of the electron beam is larger than each partition, the scan field positioned to scan one partition overlaps onto an adjacent partition. Each partition, therefore, has a boundary region which is overlapped by the scan field at more than one position of the work piece. Any portion of the chip pattern which falls within such a boundary region may be scanned at more than one position of the work piece. Since only one scanning is desired, a selection is made, in accordance with the present invention, as to which position of the work piece such a portion of the chip pattern is scanned. The selection is made so as to minimize the division of circuit elements and so as to avoid division of circuit elements in those regions which have critical dimensions and which would, therefore, cause registration problems.
Accordingly, those portions of a circuit element having critical dimensions tend to be exposed in a single scanning with the work piece at one location. In this manner, such critical dimensions are accurately scanned and are immune to any misalignment of the electron beam scan field when the work piece is moved from one position to an adjacent position.
In accordance with the above summary, the present invention achieves the objective of providing an improved electron beam apparatus and method for scanning an electron beam to expose a chip pattern by means of overlapping boundary scan fields and selective scanning of portions of the chip pattern.
Additional objects and features of the invention will appear from the following description in which the preferred embodiments of the invention have been set forth in detail in conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts an overall electrical schematic block diagram of an electron beam apparatus in accordance with the present invention.
FIG. 2 depicts one of the two table controls which form part of the FIG. 1 apparatus.
FIG. 3 depicts a line generator which is one component within the FIG. 1 apparatus.
FIG. 4 depicts a representation of the electron beam scan field produced by the FIG. 1 apparatus.
FIG. 5 depicts a top view of the table and work piece which are utilized in the FIG. 1 apparatus.
FIG. 6 depicts a representation of the FIG. 4 scan field at a reduced scale.
FIG. 7 depicts a chip area formed by a plurality of adjacent scan fields of the FIG. 4 type at the scale shown in FIG. 6.
FIG. 8 depicts a typical chip area having a chip pattern which has been partitioned in accordance with the present invention.
FIG. 9 depicts an expanded view shown along a line between two of the partitions of FIG. 8.
FIG. 10 depicts a view of a processed first one of the two partitions of FIG. 9.
FIG. 11 depicts a view of a processed second one of the two partitions of FIG. 9.
FIG. 12 depicts a representation of how the chip pattern partitioning is performed.
DETAILED DESCRIPTION
Overview-FIG. 1
In FIG. 1, a wafer or other work piece 2 to be exposed by an electron beam is positioned on the motor-driven table 24. The table 24 is located within the work chamber 80 of an electron beam column 76. The column 76 is a conventional device including an electron source 77, a blanking unit 78, a deflection unit 79, a work chamber 80, and an interferometer unit 81. The column 76 is typically like that manufactured by ETEC Corporation of Hayward, California.
The electron source 77 provides the electrons which are incident upon the work piece 2 on the table 24. Blanking unit 78 permits the electron beam to be focused on the work piece or blanks the electron beam to inhibit electrons in a conventional manner. The blanking unit 78 is selectively controlled to inhibit or pass the electron beam by the beam blanking control line 52 from the line generator 28.
The deflection unit 79 includes both X and Y deflection coils (not shown) for positioning the electron beam in the X and Y axes. The X coil is driven by the output from the X sum circuit 36. Similarly the Y coil is driven by the Y sum circuit 36'.
The sum circuits 36 and 36' provide the X and Y drive signals to the deflection unit by summing a number of input signals. First, the sum circuits 36 and 36' receive the IX and IY commanded position signals as inputs from converters 32 and 32', respectively, which in turn are commanded by the line generator 28 and processor 26. The IX and IY signals specify the location of the electron beam with respect to a unit size in some predetermined coordinate system. In one embodiment, the unit size is 0.5 .times. 10.sup.-6 meter.
The sum circuits 36 and 36' also receive correction signals IDX and IDY, respectively, which correct the position of the electron beam with some correction unit size as a function of the measured position of the movable work piece 2 as measured by an interferometer unit 81. In one embodiment, the size of the correction signal is in units of 0.08 .times. 10.sup.-6 meter. Accordingly, one unit of the IX position command signal (0.5 .times. 10.sup.-6 meter) summed with one unit of the IDX correction signal (0.08 .times. 10.sup.-6 meter) specifies a deflected distance of 0.58 .times. 10.sup.-6 meter. Similarly, ten units of IX (5.0 .times. 10.sup.-6 meter) and 20 units of IDX (1.6 .times. 10.sup.-6 meter) specifies a deflected distance of 6.6 .times. 10.sup.-6 meter.
The sum circuits 36 and 36' also receive rotation signals IRX and IRY, respectively, from units 131 and 131' for rotating the XY electron beam axes relative to the X'Y' axes of table 24. In FIG. 1, the work table 24 is driven in the X-axis direction by the X axis motor 20 and in the Y-axis direction by the Y axis motor 20' to precisely position the work piece 2 relative to the incident electron beam. The actual position of the work piece 2 and the table 24 is measured by the interferometer unit 81. Typically the interferometer unit 81 includes an interferometer for measuring the X axis position which provides an X position output 22. Similarly, the interferometer unit 81 includes a Y axis unit providing a Y position output 22'. One typical interferometer unit is manufactured by Hewlett Packard Corporation and is model number HP5501. Such a unit provides a 24-bit output which is capable of measuring the actual position of the work piece 2 and table 24 to approximately 0.08 .times. 10.sup.-6 meter. The interferometer unit is capable of tracking movements at rates of approximately up to 15 centimeters per second. The X and Y position outputs 22 and 22' from the interferometer unit 81 are connected as inputs to the X and Y axis table controls 10 and 10' respectively. Controls 10 and 10' provide signals to the units 34 and 34' to generate the correction signals IDX and IDY, respectively. In FIG. 1, the control circuitry for controlling the electron beam column 76 includes a computer 4 which commands the operation of the system in the exposure of the work piece 2 by the electron beam. Computer 4 in one typical embodiment is a Hewlett Packard model HP21MX. Computer 4 connects over a conventional digital interface 5 to the data bus 6. The computer 4 is also connected in a conventional way to I/O devices such as a CRT console 69, a magnetic tape unit 70 and a magnetic disc unit 71. The computer 4 controls the remainder of the system.
The computer 4, through the digital interface 5, communicates with a number of addressable units connected to bus 6. Bus 6 is typically a 16-bit bus with appropriate conventional selection means (not shown) for selecting an addressed one of the units connected to bus 6.
In FIG. 1, the units connected to bus 6 include the memory 7, the X gain control 8, the Y gain control 8', the X rotation control 11, the Y rotation control 11', the X table control 10 and the Y table control 10'.
Memory 7 is a random access memory typically storing 2,048 or more 16-bit words. The X and Y gain controls 8 and 8' are typically digital-to-analog converters (DAC). When selected by the digital interface 5, the controls 8 and 8' convert the digital outputs to analog levels on lines 9 and 9', respectively. Lines 9 and 9' each connect as a reference (R) input to the X and Y deflection DAC's 32 and 32'. The DAC's 8 and 8' and the DAC's 11 and 11' are conventional devices of the type which typically receive a 10-bit input to responsively provide one of 1024 levels for the analog signal output. Such devices are conventional and in one typical embodiment are manufactured by Burr Brown with model number 60-10. Since those DAC devices do not have means for storing the digital signals from bus 6, each of the DAC's 8, 8', 11 and 11' are shown in FIG. 1 to include conventional registers 8-1, 8'-1, 11-1, and 11'-1 for storing the digital data, respectively, under command of the interface 5.
When exposing the work piece 2 to form a pattern thereon, it is important that the deflection gain of the electron beam be accurately controlled so that the actual size of the electron beam scan field on the work piece 2 corresponds to the desired size of the electron beam scan field. The gain controls 8 and 8' are utilized for controlling the size of the electron beam scan field. When the beam deflection exceeds or is less than required for the desired scan field size, the deflection gain signals from controls 8 and 8' are controlled to appropriately adjust the respective referenced inputs to the converters 32 and 32'.
The X and Y rotation controls 11 and 11' are digital-to-analog converters (DAC) of the same type as the converters for controls 8 and 8'. The controls 11 and 11' convert digital outputs from the computer 4 into an analog level on lines 13 and 13', respectively. Lines 13 and 13' are each connected to one of the inputs of the multiplying amplifiers 131 and 131', respectively. The other input to amplifier 131 is supplied from the output of the Y converter 32'. Similarly, the other input to the amplifier 131' is supplied from the output of the X converter 32. The amplifiers 131 and 131', respectively, provide output signals which are connected in common with and summed with the outputs of the X and Y deflection converters 32 and 32', respectively, in the sum circuits, 36 and 36', respectively.
In FIG. 1, it is desired that the scanning axes, X and Y, of the electron beam coincide with the axes X' and Y' of the table 24, and with the axes, X" and Y", of the work piece 2. The three sets of axes XY, X'Y' and X"Y" are shown with a common origin in FIG. 1. In order to bring the axes into common alignment, rotation of the electron beam axes XY is useful. The rotation controls 11 and 11' are utilized for adjustably rotating the axes XY of the electron beam relative to the axes X'Y' of the table and the axes X"Y" the work piece 2. In operation, digital signals specifying the degree of rotation are supplied from the computer 4 to the inputs of the rotation controls 11 and 11'. The outputs from control 11 and 11' in turn control the rotation by controlling the electron beam deflection through operation of the sum circuits 36 and 36' and the amplifiers 131 and 131'.
The rotation controls 11 and 11' are also utilized for controlling the perpendicularity of the electron beam scanning in response to the digital outputs from the computer 4. Perpendicularity of the electron beam scanning refers to the X axis movement relative to the Y axis movement.
In FIG. 1, the X and Y table controls 10 and 10' receive data from and connect data to the 16-bit bus 6. Controls 10 and 10' are shown in further detail in FIG. 2. Briefly, the control 10 receives a commanded position from the bus 6. The commanded positon from bus 6 is converted to the drive signal on line 16 for driving the X motor drive 18. The X motor drive 18 in turn drives the X motor 20 to position the X axis of the table 24 within the chamber 80. Similarly, the Y table control 10' via line 16' energizes the Y motor drive 18' which in turn energizes the Y motor 20'. The Y motor 20' drives the table 24 to the desired Y axis position. The motor drive 18 and 18' and the motors 20 and 20' are conventional devices for indexing a motor-driven table. A typical motor drive and motor employed in one preferred embodiment of the invention is manufactured by Torque Systems Inc. having model number RL 3260E. Such a system has a capacity of driving the table 24 at a rate of approximately 5 centimeters per second, and accelerating or decelerating at a rate of 10 meters/sec.sup.2 (approximately 1G).
In addition to commanding the actual position of the table 24, the table control 10 and 10' also compare the commanded position (received over bus 6) with the actual position measured by the interferometer unit 81. The difference between the commanded position and the actual position is utilized to generate a correction signal on the 10-bit buses 14 and 14' for the controls 10 and 10', respectively. The 10-bit correction buses 14 and 14' are connected as inputs to the X and Y position correction DAC's 34 and 34'. The table 24 can be positioned by the motor drives 18 and 18' within an accuracy of about 0.24 micron from the commanded position. In order to provide higher accuracy as is necessary for scanning small areas, the converters 34 and 34' are utilized. The converters 34 and 34' form the analog correction signals IDX and IDY. The correction signals IDX and IDY are summed with the line scan signals IX and IY, respectively, in the sum circuits 36 and 36'. The line scan signals IX and IY are generated by the X and the Y deflection digital-to-analog converters (DAC) 32 and 32', respectively.
The converters 32 and 32' are of the same type as the converter 8 and 8'. Converters 32 and 32' are driven by inputs from the line generator 28 which is in turn driven by the line processor 26.
The line processor 26 is typically a conventional microprocessor such as the Motorola 6800. The line processor 26 accesses data for a line scan from the memory 7. Processor 26 then loads the line generator 28 with data sufficient for one line scan. The line generator 28 then is clocked at a high data rate loading the appropriate values into the converters 32 and 32' to perform a line scan at a high data rate. Converters 32 and 32' generate the line drive signals IX and IY in response to the outputs from line generator 28 as adjusted by the reference levels output from the gain controls 8 and 8'. Any correction factors required for drive signals IX and IY are derived from the converters 34 and 34' and the controls 11 and 11' which are all summed in the sum circuits 36 and 36'. The sum circuits 36 and 36' in turn drive the deflection unit 79 to actually position the electron beam.
The line generator 28 receives data from the line processor 26 via the 16-bit bus 57. Generator 28 in turn generates 10-bit deflection commands on output buses 53 and 53' which are connected to the X converter 32 and to the Y converter 32', respectively. Generator 28 also provides an output signal on line 52 which controls the blanking unit 78.
Line generator 28 provides a zero detect output line 51 which connects to the line processor 26. Zero detect line 51 signals the line processor 26 to indicate when the line generator 28 has completed a line scan. When generator 28 has completed a line scan, processor 26 immediately loads the generator 28 with a new line command and scanning continues in this manner.
The line generator 28 functions to inhibit line scanning whenever a STOP SCAN signal is drived on the lines 12 or 12' from the X and Y table controls 10 and 10'. The STOP SCAN signals signify that the commanded position of the table 24 relative to the actual position of table 24 exceeds a predetermined error (for example, greater than correctable by the 10-bit correction signal). Whenever this predetermined error is exceeded, the STOP SCAN signal functions to inhibit further operation of the line generator until the error is reduced to within the acceptable limits.
Table Control-FIG. 2
In FIG. 2, further details of the table controls 10 and 10' of FIG. 1 are shown. In FIG. 2, only the X table control 10 is actually shown since the Y table control 10' is identical.
In FIG. 2, the 16-bit bus 6 from the digital interface 5 is selectively gated to the commanded position register 42 and the maximum error register 48. The commanded position register 42 is a 24-bit register which receives the full 16-bits of bus 6 as one field and 8 bits of bus 6 as a second field. The lowest-order bit (and each count) in register 42 represents a distance of 0.08 .times. 10.sup.-6 meter. The fields are separately addressed by the computer 4 of FIG. 1 and are separately selected at different times by the digital interface 5 in a conventional manner for computers. At still a different time, a 10-bit field of the 16-bit bus 6 is selected for the maximum error register 48. The lowest-order bit (and each count) in register 48 represents a distance of 0.08 .times. 10.sup.-6 meter.
In FIG. 2, the actual position register 43 is a 24-bit register for receiving the actual position data from the 24-bit bus 38 from the interferometer unit 81 of FIG. 1. The lowest-order bit (and each count) in register 43 represents a distance of 0.08 .times. 10.sup.-6 meter. The 24-bit outputs from the commanded position register 42 and the actual position register 43 are subtracted in a conventional 24-bit subtractor 44. The output from this subtractor is connected on a 24-bit bus to a 24-bit error register 45. The contents of the error register 45 are gated selectively to a number of locations in a number of field sizes. A low-order 16-bit and a high-order 8-bit field connect to the bus 6 for returning data through the digital interface 5 to the computer 4 of FIG. 1. The high-order 12 bits from error register 45 are input to the gate control 41. The low-order 12 bits from the register 45 are input to the error limit register 46. The low-order 10 bits connect to the magnitude comparator 49 and connects an output on bus 14 to a position correction DAC 34 in FIG. 1. The high-order 14 bits from register 45 connect to the control 41'.
Control 41, in one embodiment, is an EXCLUSIVE-OR gate network (not shown) for examining the 12 high-order bits from register 45. For positive errors less than +4095 (2.sup.12 -1), such network detects the all 0's condition of the 12 high-order bits. For positive errors greater than +4095, the network detects a 1 in any of the 12 high-order bit positions. In a similar manner, the network also detects for negative errors greater than or less than -4096 (-2.sup.12).
If control 41 detects an error greater than +4095 (2.sup.12 -1) in register 45, it forces the error limit register 46 to the binary equivalent of +4095 producing the maximum negative velocity of the servo.
If control 41 detects an error less than -4096 (-2.sup.12) in register 45, it forces the error limit register 46 to the binary equivalent -4096 producing the maximum positive velocity of the servo.
If the error is between the above two limits (+4095 and -4096), the error value in register 45 is fed directly to register 46 and then to converter 47 producing a servo motor velocity signal on line 16 proportional to the error value. This proportional velocity signal provides an overdamped drive response to the servo motor system while allowing it to accurately position the table 24 to an accuracy of less than one micron.
The contents of error register 45 and maximum error register 48 are fed to magnitude comparator 49. If the magnitude of the error exceeds the value in register 48, a STOP SCAN signal is provided to the line scan generator 28 of FIG. 1.
The 10 low order bits of register 45 also form the 10-bit bus 14 which forms the position correction signal for the position correction converter 44 of FIG. 1.
By way of summary, the table control of FIG. 2 includes a means for driving the table with a signal having a magnitude proportional to the difference between the commanded position and the actual position of the table, includes means for providing a position correction signal proportional to the difference between the commanded position and actual position of the table and provides a STOP SCAN signal whenever the difference between the commanded position and the actual position exceed a predetermined error.
Line Generator-FIG. 3
In FIG. 3, the line generator 28 of FIG. 1 is shown in greater detail. The line generator functions to provide signals to the deflection unit 79 for commanding the electron beam to scan a line at a time in discrete steps. The X location of the beam is stored in the X beam position up/down counter 60. The Y location of the beam is stored in the Y beam position up/down counter 60'. The number of steps to be scanned (in either the X or Y directions) is stored in counter 58. The lowest-order bit (and each count) in each of the counters 58, 60 and 60' represents a distance of 0.5 .times. 10.sup.-6 meter. Scanning occurs for the number of steps represented by the count in length counter 58. Counter 58 and either the X counter 60 or Y counter 60' are incremented to cause the electron beam to be scanned. The 16-bit bus 57, from the processor 26 of FIG. 1, connects to the 10-bit length counter 58, to a 2-bit register (not shown) in the control unit 59, and to the 10-bit beam position counters 60 and 60'.
The line processor 26 supplies three 16-bit words to the line generator 28 when it receives a zero detection signal on line 51. Control unit 59 in FIG. 3 controls the distribution of the three words in the following manner. Upon receipt of the zero detection signal from detector 50, the control unit 59 is reset to parallel load the three low-order 10 bits of the first, second and third words from bus 57 into the X beam position counter 60, the Y beam position counter 60', and into the length counter 58, respectively, during first, second, and third stages of a load sequence. During the first stage, control unit 59 provides a control signal on line 61 to the X beam position counter 60 to cause counter 60 to parallel store the low-order 10 bits of data from bus 57 (which specifies a coordinate in the X axis of the beam).
After the counter 60 has received the first word, the control unit 59 sequences to the second stage and provides the control signal on line 62 to cause the Y beam position counter 60' to parallel store low-order 10 bits from bus 57 specifying a coordinate in the Y axis of the beam.
After receipt of the second word, the control unit 59 is stepped to the third stage. The control unit 59 provides the control signal on line 63 to cause the counter 58 to parallel store the low-order 10 bits of the third word from bus 57. Control unit 59 also on the third stage stores the two high-order bits of the third word. The two high-order bits, BIT 14 and 15, designate the direction of scan (positive or negative) and the axis of scan (X or Y).
Upon the receipt of the two high-order bits, the control unit 59 is stepped to the operating stage removing the beam blanking signal on line 52 and enabling the clock signal to counter 58. The control unit 59 then steps the counter 58 at the clock rate (for example, 10.sup.7 Hz or greater) until the length counter 58 is counted down to zero.
Meanwhile, the control unit 59 provides the control signals on lines 64 and 65. The control signal on line 64 causes one of the counters 60 and 60' to step up or down in accordance with the BIT 14. The other control signal, on line 65, causes the counter 58 to provide a signal generated at each step thereof to the X or Y beam counter 60 or 60', whichever one corresponds to the scan axis, as determined by the BIT 15. If BIT 15 is a logical 1, then the counter 60 is counted by the signal on line 66 from the counter 58 while counter 60' is not counted. If BIT 15 is a logical 0, the the counter 60' is counted by the signal on line 66' while counter 60 is not counted. The 10-bit outputs on lines 53 and 53' from counters 60 and 60' connect to converters 32 and 32'.
When the length counter 58 is counted down to zero, the zero detector 50 senses a zero, resets the control unit 59 to the beginning of the sequencing stage and signals the processor 26 to send a sequence of three additional words.
If at any time during the scanning mode either of the STOP SCAN lines 12 or 12' signals to stop the scanning, the control unit 59 inhibits clock outputs and generates the BEAM BLANK signal until neither STOP SCAN signal is present.
Field Scan - FIG. 4
In FIG. 4, the scan field 102 produced by the electron beam column 76 of FIG. 1 is shown in greater detail. The scan field 102 covers an area 512 by 512 microns (512 .times. 10.sup.-6 meters square). That area is divided into 1,048,576 addressable locations where each location appears at the intersection of one of 1,024 rows and one of 1,024 columns. The columns are defined by the 10-bit X address and the rows are defined by the 10-bit Y address previously described in connection with the line generator of FIG. 3. The line generator of FIG. 3 causes the electron beam to be deflected so as to be incident at any one of the 1,048,576 locations specified by a row address and a column address.
In a typical embodiment, the electron beam spot size is 0.5 micron in diameter. With this spot size for the electron beam and with the 1,024 addresses per axis, the entire 512 by 512 micron scan field or any part thereof, may be exposed by the electron beam.
In connection with FIG. 4, an example of how the present invention operates to scan a particular part of a circuit is described. In FIG. 4, the scan field 102 includes in the lower left hand corner a printed circuit conductor 103 which terminates in a printed circuit land 104. The conductor 103 is 3 microns wide, has a right angle and terminates in a land 104 which is 5 microns square. Assumming, for purposes of explanation, that the scanning of the conductor 103 and land 104 is to occur in the X direction, then the following addresses are generated by the line generator of FIG. 3.
In the manner previously indicated in conjunction with FIG. 3, the X beam position counter 60 is loaded with a 10-bit binary word which specifies column 5.
Thereafter, the Y beam position counter 60' is loaded with another 10-bit binary word which specifies row 3. The outputs of the counters 60 and 60' are fed to the X deflection DAC 32 and the Y deflection DAC 32', to cause the electron beam to be positioned at the point of column 5 and row 3.
Meanwhile, the length counter 58 is loaded with still another 10-bit word representing the distance to the last location of the conductor 103 in row 3, which is column 20. At the same time, the control unit 59 receives BIT 14 as a logical 1 and BIT 15 as a logical 1, which together, indicate that the scanning is to occur in the positive X direction. After the loading has been completed, the beam blanking signal on line 52 is removed and the X axis address in the X beam position counter 60 is incremented until the length counter 58 reaches a zero count. Incrementing occurs because BIT 14 and BIT 15 are logical 1's. When the count in length counter 58 reaches zero, the beam blank signal is turned on and no further exposure in row 3 will occur. The zero detector 50 causes the control unit 59 to load three new 10-bit numbers for the next scanning line. An identical 10-bit number indicating column 20 is stored in the X beam position counter 60, and the Y beam position counter 60' is loaded with a 10-bit number which indicates row 4. Then, the X and Y DAC's 32 and 32' supply analog signals to position the beam at the column 20 and row 4 location.
A length count of 15 is loaded into counter 58 and the control unit 59 detects BIT 14 as a logical 0 and BIT 15 as a logical 1.
Therefore, the X beam position counter is decremented and the beam is moved in the negative X direction while scanning the row until the length counter reaches a zero count. Scanning in this manner for each row for columns 5 through 20 continues.
After the scanning has been performed for row 8, new numbers specifying column 15 and row 9 are stored respectively into the X beam position counter 60 and the Y beam position counter 60', and then the length counter 58 is loaded with a length count of 6. Scanning with this length count of 6 is carried out for each of the rows 9 through 14, while the initial count in the counter 60 is changed to 15 for rows 9, 11 and 13 and to 20 for rows 10, 12 and 14 and the count in the Y counter 60' is incremented by one for each row from 9 to 14.
Thereafter, the scanning for the land 104 is started by entering the Y address for row 15 into the Y beam position counter 60' and the X address for column 13 into the X beam position counter 60. The length count is 10 and is loaded into the length counter 58. Each of the rows 15 through 24 is scanned with a length of 10 in order to complete scanning of the land 104.
All of the scanning of the conductor 103 and land 104 in FIG. 4 occurs without any requirement that the table 24 of FIG. 1 be moved.
It should be observed that the data rate for scanning the pattern comprising the conductor 103 and the land 104 is determined by the bit rate of data from the counters 58, 60 and 60'. That bit rate is defined by the clock rate at which the counters 58, 60 and 60' are stepped. In the present invention, time is not wasted scanning areas of the scan field 102 which are not to be exposed by the electron beam. While the data bit rate of scanning is the rate of clocking counters 58 and 60, the data rate for loading three words into the line generator 28 is also important in maintaining a high data rate because three words must be accessed for each line to be scanned by the line generator 28. On the other hand, the data rate between the line processor 26 and the computer 4 need only be at a rate great enough to exceed the line rate of scanning. For example, a data rate of 10.sup.6 words per second between computer 4 and processor 6 (on a non-continuous burst mode basis) normally sustains a 10.sup.8 bit per second data rate between line generator 28 and column 76.
Table Position -- FIG. 5
In FIG. 5, the table 24 and work piece 2 of FIG. 1 are shown in greater detail. The work piece 2 is typically a semiconductor wafer of approximately 100 millemeters in diameter. The wafer 2 has a center indicated by the intersection of the X' and Y' axes. The electron beam from electron beam column 76 of FIG. 1 is incident upon the wafer 2 at a location indicated by the intersection of the X and Y axes. The table 24 and wafer 2 are relatively movable with respect to the incident electron beam. Therefore, the X' Y' axes are relatively movable with respect to the XY axes through movement of the table 24. In FIG. 5, the point of incidence (intersection of X and Y) of the electron beam is shown in the lower left quadrant of the X' Y' axes. In FIG. 5, the area of incidence of the electron beam is at one row and one column address within a scan field of the FIG. 4 type. That scan field is in turn within one of many chip areas. The particular chip area 101-1 over which the scan field of the electron beam is incident is determined by the position of the table 24 as defined by axes X' Y'. The chip areas 101 are areas which can be ultimately diced and then packaged to form individual integrated circuits. A chip area can be and typically is larger than the scan field of the electron beam. Therefore, each chip area is divided into partitions which can be individually exposed by the beam scan field. The table 24 and wafer 2 are moved to superimpose the beam scan field over a selected chip area and over a selected partition within a chip area.
In FIG. 5, the electron beam axes X' Y' is located to position the electron beam scan field over a chip area 101-1. The scale of FIG. 5 does not allow the partitions of the chip area 101-1 to be observed.
In one application of the present invention, the beam scan field 102 as shown in FIGS. 4 and 6, is typically 512 by 512 microns and the chip area 105, as shown in FIG. 7, is typically 1350 by 1606 microns. Since the scan field 102 is smaller than the chip area 105, the chip area 105 is divided into twelve partitions 106. Each partition 106 is smaller than the scan field 102. Each partition is positioned, at a different time, to be superimposed by the electron beam scan field so that twelve different positions of the table 24 and wafer 2 are needed to permit one chip area 105 to be fully scanned by the electron beam.
In FIG. 5, the electron beam scan field is positioned over the chip area 101-1. Wafer 2 will accomodate hundreds of other chip areas of the same size, some of which are represented by chip areas 101 in FIG. 5. The table 24 is positionable to locate any chip area 101 (and any partition of a chip area) beneath the electron beam scan field.
Chip Area Formation By Overlapping Scan Fields -- FIGS. 6 & 7
In FIG. 6, a scale representation of the electron scan field 102 like that previously described in FIG. 4 is shown.
In FIG. 7, a chip area 105 is shown having the dimensions of 1,606 microns by 1,350 microns. The chip area 105 is further divided into the partitions 106 and specifically the twelve partitions 106-1, 106-2, . . . , 106-12. The partitions are each smaller than the scan field 102 of FIG. 6. For example, the partitions are 450 microns by 401.5 microns in a typical example. Note that each of the partitions 106 of FIG. 7 can be totally enclosed within the scan field 102 shown to the same scale in FIG. 6.
In FIG. 7, the scan field 102 of FIG. 6 is shown positioned relative to the partition 106-7. When so positioned, the scan field 102 is designated as scan field 102-7. The scan field 102-7 is designated by long broken lines in FIG. 7. Also in FIG. 7, the scan field 102 is shown positioned over the partition 106-8 and the scan field is shown as short broken lines and is designated as scan field 102-8. The boundary line 120 (7/8) between partitions 106-7 and 106-8 is covered both by the scan field 102-7 and the scan field 102-8. There is a region 122 having a dimension B2 which is common to both the scan field 102-7 and the scan field 102-8. In accordance with the present invention, electron beam scanning within the region 122 can be performed either in connection with the scan field 102-7 or in connection with the scan field 102-8. While only the partitions 102-7 and 102-8 have been indicated showing the overlapping scan field relationship, each of the partitions in FIG. 7 and the adjacent partitions on any side similarly have an overlapping boundary relationship relative to the electron beam scan fields.
The purpose of this overlapping boundary relationship is to permit portions of the chip pattern which lie within the overlapping boundary region, such as region 122, to be selectively processed either in one scan field (eg. 102-7) or in the other scan field (102-8). This selective scanning in one or the other of the posssible scan fields avoids the necessity of scanning patterns within the boundary using two different scan fields. It has been found that when patterns having critical dimensions are scanned by two different scan fields, that is, partially in one scan field and partially in another scan field, substantial errors are frequently introduced.
In accordance with the present invention, such errors can be reduced or eliminated by wholly scanning critical dimensions in the boundary region using only one of the two possible scan fields.
In FIG. 7, if the width of the partition, W7, is 401.5 microns and the scan field 102-7 is 512 microns, the portion of the boundary B1 is 55.5 microns and the full boundary region demension B2 is 110.5 microns. In a similar manner, a portion of the boundary region having dimension B3 lies between partitions 106-7 and 106-5 and measures 31 microns. The full boundary between scan field 102-6 (not shown) and the scan field 102-7 is then 62 microns wide.
Chip Pattern -- FIG. 8
In FIG. 8, a chip area 105 is shown including a chip pattern 107. The chip pattern 107 is to be exposed with an electron beam in accordance with the present invention. The pattern includes a number of pads 131 which are identified as P1, P2, . . . , P24. The pads are generally arranged around the perimeter of the chip area 105. The pads 131 are utilized, for example, to form off-chip connections in a final package integrated circuit (not shown). The pads 131 and other areas on the chip area 105 include various lines 132. In FIG. 8, the lines all represent conductors in one layer of a multi-layer semiconductor structure. The present invention, of course, also pertains to other layers in which the chip patterns represent semiconductor regions and other circuit elements well known in the field of integrated circuits.
The chip pattern 107 is layed out for convenience in connection with an X axis and a Y axis which intersect at an origin 130. Each line 132 and each pad 131 in the circuit pattern 107 is initially specified in accordance with its position and size relative to the origin 130. Furthermore, each portion of the chip pattern 107 is formed by one or more different sized shapes. While many different shapes can be employed, the particular example of FIG. 8 employs rectangular shapes. Each rectangular shape, is designated by four numbers which represent its displacement along the X axis from the origin 130, its displacement along the Y axis from the origin 130, its length along the X axis, and its length along the Y axis. These four numbers are designated as four words, namely, WORD 1, WORD 2, WORD 3, and WORD 4, respectively. The words are conveniently stored and processed in the data processing apparatus of FIG. 1.
By way of example, and referring to FIG. 8, the P12 pad 131 is a rectangle which measures 120 microns by 120 microns or 240 by 240 one-half microns. In FIG. 8, the coordinate system is measured in one-half microns (because the electron beam spot diameter is one-half micron wide). Therefore, as indicated in FIG. 8, the dimensions of the P12 pad 131 are 240 by 240 one-half microns.
The displacement of the P12 pad 131 from the origin 130 is 1,280 one-half microns along the X axis and -1,120 one-half microns along the Y axis. Hence the displacement address from origin 130 is designated as [1,280, -1,120]. The displacement address designates the location of the lower left-hand corner of the P12 pad 131. The P12 pad 131 has a length along the X axis of 240 one-half microns and a length along the Y axis of 240 one-half microns.
In accordance with the four word notation, the WORD 1, WORD 2, WORD 3 and WORD 4 designations which specify the rectangular shape for the P12 pad 131 are 1,280, -1,120, 240, 240, respectively.
The P12 pad 131 has a rectangle 133 adjacent to its left-hand edge. The WORD 1, WORD 2, WORD 3 and WORD 4 designations for the rectangle 133 are 1,260, -1,040, 20 and 80.
In a similar manner, the P11 pad 131 has the WORD 1 through WORD 4 designations 1,280, -720, 240, 240, respectively.
In FIG. 8, every portion of the chip pattern 107 is specified in terms of its rectangular dimensions and its offset position from the origin 130. A file listing for the entire chip pattern 107 of FIG. 8 appears as TABLE I at the end of this specification. Referring to TABLE I, the record number (RECORD NO.) column identifies each 4-word record. As previously explained, WORD 1 designates the X axis offset from the origin 130. WORD 2 designates the Y axis offset from the origin 130. WORD 3 designates the length, XL, of the rectangle along the X axis. WORD 4 designates the length, YL, of the rectangle along the Y axis. Certain of the records of TABLE I designate header information to identify TABLE I.
Specifically, referring to record numbers 1 and 2 the four words merely indicate information identifying TABLE I and its use in connection with other integrated circuit layers.
Record number 3 is a header which indicates in WORD 1 and WORD 2 that the size of the chip area is 1,606 microns in the X axis and 1,350 microns in the Y axis. WORD 4 indicates that the remainder of TABLE I is comprised of 681 record numbers, that is, record numbers 4 through 684.
Record number 4 specifies the four words which define the P12 pad 131 as previously described.
Record number 5 specifies rectangle 133 in the manner previously described.
Record number 6 describes the P11 pad 131 in the manner previously described.
Additionally, record numbers 8, 10, 12, . . . , 24, 26, 28, 30, . . . , 48, 50, designate the pads P10, P9, P8, . . . , P2, P1, P24, P23, . . . , P14, P13, respectively. In a similar manner, every other rectangular shape on the chip pattern within chip area 105 is defined by a four word record entry in TABLE I.
By way of further example, still referring to FIG. 8 and TABLE I, record number 331 specifies the land (for a via hole) V2. Record 333 specifies the land V1. Record 374 specifies the land V3 and record 375 specifies the land V4. Record 377 specifies the line L1, record 426 specifies the line L3, record 430 specifies the line L4 and record 441 specifies the line L2. The lines L1 through L4 and the via holes V1 through V4 lie in the general vicinity of a partition line 120(7/8) which has been drawn to partition the chip pattern on the chip area 105 of FIG. 8. It should be noted, however, that the input file of TABLE I has entries with respect to the origin 130 without regard to any partitioning of the chip area 105.
The chip pattern of FIG. 8 is divided into 12 partitions 106-1 through 106-12 in the manner described previously in connection with FIG. 7. Accordingly, the data of the unpartitioned file of TABLE I must be processed to partition the data so that it corresponds with the partitions 106-1 through 106-12 of FIG. 8. Actually, the partitions 106-11 and 106-12 do not contain any of the chip pattern and hence only 10 partitions need be employed to define the chip pattern of the chip area 105 in FIG. 8.
Referring to FIG. 8, the partitioning of the chip pattern 107 requires that portion of the chip pattern in each of the partitions 106 to have its data in TABLE I translated relative to the XY axes having an origin 130 to a new coordinate system having an origin in the lower lefthand corner of the scan field 102 associated with the particular partition 106. Referring to FIG. 7, the origin 130 is shifted to a point 134-7 in connection with the partition 106-7. The point 134-7 is the lower left-hand corner of the scan field 102-7.
Referring to FIG. 8, the partitions 106-1 has a translated coordinate system including the X1 axis and the Y1 axis which intersect at the origin 134-1. The origin 134-1 is 1412 one-half microns shifted down from the X axis and 1716 one-half microns shifted over from the Y axis. The 1412 one-half micron value is determined in the following manner. The shift from the X axis is equal to one-half the height of partition 106-5 (equal to 450 one-half microns), the total height of the partition 106-1 (900 one-half microns) plus the width of the boundary of the partition 106-1 and the scan field 102-1 (62 one-half microns). Similarly the 1,716 number is equal to the width of the partitions 106-1 and 106-2 (each 803 one-half microns) plus the width of the boundary between the scan field 102-1 and the partition 106-1 (110 one-half microns). All of the chip pattern rectangular shapes of FIG. 8 which fall within the partition 106-1 may have their coordinates translated to the new axis by adding 1,716 to the X axis coordinate and by adding 1,412 to the Y axis coordinate. In general, this translation involves searching all of the records in the TABLE I file to ascertain which ones fall within the scan field associated with the partition 106-1 of FIG. 8. Thereafter the X axis and Y axis translation factors are added to form the translated coordinates. Such a translation for all the rectangular shapes and all the partitions of FIG. 8 are shown in TABLE II.
Referring to TABLE II, record numbers 1 and 2 merely specify information identifying the table and its use in forming an integrated circuit. WORD 2 of record number 2 indicates that TABLE II comprises the following 733 record numbers, namely, record numbers 3 through 735.
Record number 3 indicates that the table specifies a chip pattern which measures 1,606 by 1,350 microns.
Record number 4 indicates the number of one-half microns that the table 24 of FIG. 1 must be moved from the origin 130 in order to superimpose the scan field 102 of the electron beam over the partition 106. The table is moved -1,204 one-half microns in the X direction and -900 one-half microns in the Y direction so that the scan field has its translated center at 130-1 and has its lower left-hand corner at point 134-1 as shown in FIG. 8.
Record number 5 of TABLE II indicates that the partition 106-1 has a width in the X direction of 803 one-half microns and in the Y direction of 900 one-half microns. WORD 4 of record number 5 indicates that the partition 106-1 is defined by 8 rectangles. Those 8 rectangles are specified in the following 8 record numbers, namely 6 through 13.
Record number 6 defines the P20 pad 131 with respect to the X1 Y1 coordinate system. Record number 6 indicates that the lower left-hand corner of the P20 pad 131 has a location which is 196 one-half microns along the X axis and 692 one-half microns along the Y1 axis all with respect to the origin 131-1. The WORD 3 and WORD 4 entries of TABLE II are identical to the WORD 3 and WORD 4 entries of TABLE I since no change in the size of the rectangle has been implemented with respect to the translation presently described. Of course, if a change in scale were desired, the WORD 3 and WORD 4 entries could be also translated to changed values.
Record number 6 in TABLE II corresponds to record number 36 in TABLE I. The TABLE II entry of 196 is obtained by adding 1,716 to -1,520. The 692 TABLE II entry is obtained by adding 1,412 to -720 in the manner previously described.
In TABLE II, the records 8 and 10 specify the P19 and P18 pads 131. The records 8 and 10 of TABLE II correspond to the records 38 and 40 of TABLE I.
In TABLE II, record 14 specifies the amount that the table 24 of FIG. 1 must be moved from its position at partition 106-1 in order to position the scan field 102 over the partition 106-2. The move is 803 one-half microns in the positive X direction and no movement in the Y direction.
Record 14 specifies the size of the partition 106-2, namely 803 by 900 one-half microns. WORD 4 specifies the number of record entries and hence the number of rectangular shapes which form the pattern within the partition 106-2. The number of rectangular shapes is 9 and includes records 16 through 24.
In TABLE II, record 25 indicates the 803 one-half microns required to move the scan field from its position at partition 106-2 to superposition it over the partition 106-3. Record 26 indicates the 803 by 900 one-half micron size and that 139 rectangular shapes are employed to define the chip pattern within the partition.
The 139 shapes are defined in the records 27 through 165.
In TABLE II, record 166 specifies an 803 one-half micron move from its position at partition 106-3 to superposition the scan field 102 over the partition 106-4 of FIG. 8.
Record number 167 indicates the partition size and that 112 record numbers are employed to define the chip pattern within the partition 106-4. Those 112 record numbers are 168 through 279.
Record number 280 specifies the zero X axis and 900 Y axis movement of the table 24 of FIG. 1 from its position at partition 106-4 to superimpose the scan field 102 over the partition 106-5 of FIG. 8.
Record number 281 indicates the size of the partition and that six record numbers are employed to define the partition. The record numbers are 282 through 287.
Record number 288 specifies the -2,409 one-half micron X axis move of the table 24 of FIG. 1 from its position at partition 106-5 to superimpose the scan field 102 over the partition 106-6 of FIG. 8.
Record number 289 specifies the size of the partition and that six records comprising record numbers 290 through 295 that define the chip pattern.
Record number 296 specifies the movement of the table 24 from its position at partition 106-6 to superimpose the scan field 102 over the partition 106-7 of FIG. 8. Record number 297 indicates the 109 record numbers running from record number 298 through record number 406 which define the chip pattern within the partition. The L1, L2, 3, V1, V3, and V4 shapes in FIG. 8 are defined in TABLE II by record numbers 367, 402, 393, 342, 364, 365, respectively, and the corresponding record numbers in TABLE I are 377, 441, 426, 333, 374, 375, respectively. These record numbers will be utilized hereinafter in accordance with the double boundary partitioning of the present invention since they define shapes which fall on the partition boundary 120 (7/8) between partition 106-7 and partition 106-8.
In TABLE II, record number 407 specifies the 803 one-half micron move of table 24 from its position at partition 106-7 in order to superimpose the scan field 102 over the partition 106-8 of FIG. 8.
Record number 408 among other things specifies that the chip pattern within the partition 106-8 includes 190 records which run from record number 409 to record number 598.
In connection with partition 106-8, the patterns L2, L3, V1, V3 and V4 do not find a record entry even though part of those patterns appear in partition 106-8. The reason they do not appear in the records for partition 106-8 is because, in accordance with the present invention, the entire designation for those patterns appears in the record for partition 106-7. Note in connection with the record for partition 106-8 that a portion of the pattern L3 is stored in record 592 and the entire pattern for V2 is stored in record 549.
Record number 599 of TABLE II indicates the 803 one-half micron X axis movement of the table 24 required from its position at partition 106-8 to superimpose the scan field 102 over the partition 106-9 of FIG. 8.
Record number 600 indicates that 117 record numbers, which appear as record numbers 601 through 717 are required to designate the chip pattern falling within the partition.
Record number 718 of TABLE II specifies the 803 one-half micron movement required from the position at partition 106-9 to superimpose the scan field 102 over the partition 106-10 of FIG. 8. Record number 719 indicates that 14 records, appearing in record numbers 720 through 724, are required to designate the chip pattern falling within the partition 106-10.
Record number 734 designates a move to return the scan field to the origin 130 and record number 735 indicates the end of the TABLE II listing.
Partition Boundary--FIG. 9
In FIG. 9, an expanded view of the chip pattern in the partitions 106-7 and 106-8 in the vicinity of the partition boundary 120(7/8) is shown. In FIG. 9, the lines which cross the partition boundary 120(7/8) are designated as L1, L2, ..., L8. Similarly, the land patterns which cross the boundary 120(7/8) are designated as V1, V2, ..., V6. If the patterns L1 thorugh L8 and V1 through V6 were scanned directly, then a portion of each would be exposed by an electron beam in connection with the partition 106-7 and also a portion in connection with the partition 106-8. For example, line L1 would be exposed four-fifths in connection with partition 106-7 and one-fifth in connection with partition 106-8. Any error in the movement of the table 24 of FIG. 1 in positioning the scan field 102 in connection with the partition 106-7 relative to the partition 106-8 would tend to alter the dimensions of the line L1. Line L1 is, in the particular example, intended to be 5 microns wide. An unwanted change in the relative position of the scan fields would tend to either divide the line L1 into two lines or to reduce the dimensions of the line. Errors of this type, particularly when the chip pattern being formed are critical dimensions, such as regions of transitors or other semiconductor devices, tend to introduce significant errors. In accordance with the present invention, this problem is avoided at scan boundary regions by selectively including shapes having critical dimensions all within one partition or all within another partition. For example, the line L1 in FIG. 9 is totally exposed in connection with the processing of the partition 106-7 and is not exposed at all in connection with the scanning of the partition 106-8. Further details of the scanning at the partition boundary are described in connection with FIGS. 10 and 11.
Double Boundary Partitioning--FIGS. 10 & 11
In FIG. 10, the portion of the chip pattern 107 scanned within the scan field 102-7 in connection with the partition 106-7 is shown. A detailed listing of the rectangles which comprise the chip pattern of FIG. 10 appears in TABLE II in record numbers 297 through 406. In a similar manner, FIG. 11 depicts that portion of the chip pattern 107 which is scanned within the scan field 102-8 in connection with the partition 106-8. For convenience, the partition line 120(7/8) in FIG. 8 has been separated in FIGS. 10 and 11 and appears therein as lines 120(7) and 120(8), respectively. In the actual scanning, however, the lines 120(7) and 120(8) are superimposed and form only one common boundary line 120(7/8) as shown in FIG. 8.
Referring to the boundary 120(7) in FIG. 10, it can be noted that the patterns V5, V3, L1, V4, L2, V1, L7, and V6 all extend across the boundary 120(7) into the region between the boundary 120(7) and the outer perimeter of the scan field 102-7. Because the area of the scan field 102-7 intentionally is greater than the area of the partition 106-7, the extension into the boundary region of the portions of the pattern along the boundary 120(7) is readily facilitated in accordance with the present invention.
Referring to FIG. 11 by way of contrast, no portion of the chip patterns V5, V3, L1, V4, L2, V1, L7, and V6 appear in FIG. 11 since all portions of those chip patterns are included in FIG. 10.
Chip Pattern Partitioning
The decision of where to position shapes (rectangles) falling on the boundary or in more than one partition area can be made manually by inspection of FIGS. 8 and 9. Since the coordinates of all the rectangles are available in TABLE I, the partitioning can be performed automatically with greater speed using data processing equipment.
One preferred method of partitioning a chip pattern using data processing techniques will now be described.
It is assumed that the TABLE I data is stored in the data processing system and it is identified as the unpartitioned file. A decision is made as to how many partitions into which the pattern represented by the TABLE I file is to be divided. In accordance with the present example, 12 different partitions, of which only 10 contain any information, are to be formed.
The partitions, as can be seen in connection with FIG. 12, are arrayed in rows and columns. The first column, designated as 01, includes the partitions 106-1, 106-6 and 106-7. The second column, designated as 0, includes the partitions 106-2, 106-11 and 106-8. The next column, designated as +1, includes the partitions 106-3, 106-12 and 106-9. The final column, designated as +2, includes the partitions 106-4, 106-5 and 106-10.
In a similar manner, the rows of partitions can be observed with respect to FIG. 12. The row designated as 0 includes the partitions 106-1, 106-2, 106-3 and 106-4. The row designated as +1 includes the partitions 106-6, 106-11, 106-12 and 106-5. The row designated as +2 includes the partitions 106-7, 106-8, 106-9 and 106-10.
In TABLE I, record numbers 1 and 2 are accessed from the unpartitioned file and stored in record number 1 and 2 locations of the partitioned file which is TABLE II. This information merely serves to identify the pattern. The TABLE I information only represents one pattern layer while any given circuit design typically has a number of layers. Each layer, however, is similar to the layer represented in TABLE I and would be processed in the manner now to be described for TABLE I.
Initially, the first shape (the rectangle of record number 4) is accessed from the unpartitioned file. After the first shape is processed, then the second shape (record number 5) is accessed and processed in the manner not to be described until all shapes, 681 in all for TABLE I, have been processed.
Record number 4 as accessed from TABLE I has coordinates established with respect to the origin 130 (see FIG. 8). The first step is to shift the origin to a new origin 130' which is on both an X and Y partition boundary. The shift is carried out by adding -450 one-half microns to the Y coordinate of record number 4. No X axis addition is required since origin 130 is already on an X axis partition boundary.
The next step in the process of dividing the whole pattern of FIG. 8 into twelve partitions is to determine the partitions that the shape currently being processed falls into. The process for each shape first examines the coordinates in the X direction to determine the first and last partition columns which the shape falls into. This determination is carried out initially for the X axis by executing the subroutine of CHART I.
The details of the steps in CHART I will be explained hereinafter in connection with the examples of FIG. 12. Briefly, however, each shape is analyzed in the X direction for determination of whether or not the shape has any portions in each of the columns, starting with the FIRST and going to the LAST column. The partitioning is done by using a four-word quantity defined as the RESIDUAL COLUMN SHAPE. Initially, the RESIDUAL COLUMN SHAPE includes the entire shape as defined by the four words (WORD 1, ..., WORD 4) from the TABLE I record. When the partitioning of the FIRST column occurs, the portion of the shape within the FIRST column (again designated by four words) is placed in a local storage area with a column identification code appended. The portion placed in the local storage area is designated as the COLUMN SHAPE and it is subtracted from the RESIDUAL COLUMN SHAPE. Thereafter, the COLUMN SHAPE for the next column after the FIRST is stored in a local storage area with appropriate column identification, and the COLUMN SHAPE thus stored is subtracted from the RESIDUAL COLUMN SHAPE. Processing continues in this manner for each column until the LAST column is reached. When the LAST column is reached, the balance of the RESIDUAL COLUMN SHAPE is stored in the local storage area with appropriate identification of the LAST column. Under certain conditions, of course, as discussed in connection with CHART I, the FIRST column is equal to the LAST column and the particular shape is entirely within a single column.
After all of the COLUMN SHAPES have been stored in local storage (four words each) with appropriate identification of the column, each COLUMN SHAPE is then further processed along the Y axis to determine the portion, called the ROW/COL SHAPE, of each COLUMN SHAPE which is located in each row.
In scanning in the Y direction, the steps of CHART I are again repeated for each COLUMN SHAPE in local storage. In accordance with that CHART I, the FIRST and LAST rows are determined for a first one of the COLUMN SHAPES. Each stored COLUMN SHAPE initially forms one RESIDUAL ROW/COL SHAPE. This RESIDUAL ROW/COL SHAPE is then processed from the FIRST to the LAST row. As each row is processed, a ROW/COL SHAPE is formed and is subtracted from the RESIDUAL ROW/COL SHAPE. The ROW/COL SHAPE thus formed is stored in local storage with appropriate row identification appended to the column identification. Each ROW/COL SHAPE thus formed has, therefore, an appropriate row and column identification which uniquely defines one of the partitions into which the ROW/COL SHAPE is to be placed.
With the ROW/COL SHAPE thus having a unique one of the partitions identified, it now becomes a task of translating the coordinates for the X and Y origins of that ROW/COL SHAPE to appropriate values associated with an origin of the identical portion. The X and Y coordinates currently stored in WORD 1 and WORD 2 are with respect to the origin 130'. The coordinates for the lower left hand corner of the partition to which the portion of the shape is to be assigned are subtracted from the WORD 1 and WORD 2 values of the ROW/COL SHAPE in local storage. The new WORD 1 and WORD 2 result is a shift of the origin from 130' to the lower left hand corner of the identified partition. Next, the X and Y offset values (OFST in CHART I) are added to the new WORD values. In the present example, the X axis offset added is 111 one-half microns and the Y axis offset added is 31 one-half microns. The result of adding the offset values translates the origin from the lower left hand corner of the identified partition to the lower left hand corner of the scan field associated with that partition.
When all of the rows have been thus processed for a particular COLUMN SHAPE, then the processing is again repeated for the next COLUMN SHAPE in turn storing each new ROW/COL SHAPE with a row and column identification and translated coordinates. Finally, when all of the COLUMN SHAPES have been thus processed, processing for a single one of the TABLE record number shapes is complete and the system is now ready to repeat the process all over again for the next record number shape. In the example of TABLE I, the first shape is record number 4 and is the next shape is record number 5. When the processing for record number 5 is complete, the processing continues for each of the shapes of record numbers 6 through 685 of TABLE I.
After all of the shapes of TABLE I have been processed and stored in a local store with appropriate row and column identifications, the ROW/COL SHAPES are then sorted by partition and listed in the partitioned file which appears as TABLE II.
Further details of CHART I will not be explained. CHART I is essentailly a FORTRAN subroutine which is executed a multiple number of times for each shape. The subroutine automatically allocates portions of shapes to positions including those portions lying in the overlapping boundary regions between adjacent scan areas.
In CHART I, statement S1, the subroutine is named as partition boundary (PBND) and the input values for the variables indicated, FIRST, LAST, OFST, PLEN, ORGN, and LEN are called for. FIRST and LAST are initially 0. OFST is the value of the offset which is equal to the width of the boundary region, B2 in FIG. 7, between the partition boundary line 120 and the scan field perimeter 102. In the particular example of FIG. 8, OFST is equal to 110 one-half microns for X axis scans or 31 one-half microns for Y axis scans. The quantity PLEN is equal to the partition width which, in the example of FIG. 8 is 803 one-half microns for X axis scans or 900 one-half microns for Y axis scans.
The quantity ORGN designates the origin of each particular shape with respect to the axis of scan, either X or Y. The quantity LEN is equal to the length of each particular shape in the direction of scan.
Statement S2 incidates that the values of statement S1 are integers. The quantity OVER designates the length that a shape extends from the partition boundary line in the partition in which the shape terminates. The quantity UNDER designates the length between the beginning of the shape and the first partition boundary line.
Statement S3 through S6 are reserved for a textual comment which help explain CHART I.
In Statement S7, the quantity FIRST is calculated from given values of ORGN and PLEN. Referring to FIG. 12, an example of the S7 calculation is described in connection with the X axis scan of rectangular shape 141. In FIG. 12, the partitions running along the X axis are 106-1, 106-2, 106-3 and 106-4 in connection with the Y coordinate in the vicinity of the shape 141. The partition boundary line 122/3 is the 0 axis. Coordinates to the right of the 0 axis are positive and to the left are negative. Since the coordinate for ORGN will be less than the length of a full partition, PLEN, the ratio ORGN/PLEN is a fraction less than 1. The integer value for FIRST in S7 will therefore be 1. The quantity FIRST is indicated as being at the partition boundary line 120(3/4) in FIG. 12.
In statement S8, calculations are made for values in X of ORGN less than 0. Since ORGN is positive and hence greater than 0 for the shape 141, S8 is not employed. Another example in which the ORGN has a negative X coordinate is the shape 142. For the shape 142, the FIRST value becomes a -1 which is indicated as being at the partition boundary line 120(1/2).
In statement S9, the value of NXT is calculated by summing the ORGN and LEN values. In connection with the shape 141, the NXT value falls within the positive region between 0 and +1.
In statement S10, the value of LAST is calculated for positive values of NXT. As shown in FIG. 12, the value of LAST for the shape of 141 is 1 and hence also falls on the boundary line 120(3/4).
Statement S11 is used for negative values of NXT. None of the examples in FIG. 12 has a negative NXT, however, the calculation is analogous to that of statement S8 for negative values of ORGN.
In statement S12, UNDER is calculated based upon the previous calculations of FIRST and LAST and NXT. The various quantities calculated for UNDER and OVER for the shapes 141 through 145 in FIG. 12 are appropriately labeled.
The manner in which these calculations are employed in order to make a determination to which partition column or columns a particular shape is to be allocated are now described in connection with the statements S18 through S26. The statements S14 through S17 are merely for textual comments describing the program.
In statement S18, if FIRST is equal to LAST, then a decision as to which partition column is to receive the COLUMN SHAPE has been made since the shape fits entirely within the column designated by the quantity FIRST. An example where FIRST equals LAST is shape 141. The value of FIRST is +1 and designates the column containing partition 106-3. The X axis processing of shape 141 is then complete. The COLUMN SHAPE in this example includes the original four words for the shape 141 and has the column +1 identification appended as previously described.
In statement S19, the condition of UNDER being less than OFST is examined. Such a condition occurs, for example, both in connection with the shapes 143 and 144. In those conditions, the value of FIRST is changed to equal FIRST +1. That is, the change is from a -1 to 0 thereby changing the designation from the boundary line 120(7/8) to the boundary line 120(8/9). The effect of this change is to place those portions of the shape to the left of boundary line 120(7/8) [but still within the scan field 10(2-8) within the COLUMN SHAPE for the -1 column which contains the partition 106-8. Thereafter that COLUMN SHAPE is subtracted leaving the RESIDUAL COLUMN shape as everything to the right of boundary 120(8/9)].
In statement S20, an examination is made to determine whether OVER is less than OFST. If that condition exists, the value of LAST is set equal to LAST -1. The condition of S20 is not met in connection with the shape 143 so that LAST remains a +1 indicated at the boundary 120(9/10). The result is that the RESIDUAL COLUMN SHAPE [that is, everything to the right of boundary 120(8/9)] is stored as the COLUMN SHAPE for the +1 column containing partition 106-9. In connection with the shape 144, however, OVER is less than OFST, so that LAST is set equal to LAST -1. In connection with the shape 144, therefore, LAST is changed from +1 to 0, that is, from the boundary line 120(9/10) to the boundary line 120(8/9). The result is that the entire shape 144 is stored as the COLUMN SHAPE for the -1 column containing partition 106-8.
In statement S21, the new values of FIRST and LAST as they may have been changed in S19 and S20 are examined. If FIRST is less than or equal to LAST, then a determination has been made as to the partition allocation. In connection with the shape 144, FIRST, now equal to 0, is equal to LAST now also equal to 0. The 0 value for FIRST therefore designates that the partition 106-8 is the one to receive the entire shape 144.
In statement S22, a comparison of OVER and UNDER is made under the condition that FIRST was greater than LAST in S21. Under the condition that UNDER was greater than OVER, S22 would proceed to S23. No example of such a condition is shown in FIG. 12. In FIG. 12, however, the value of OVER is greater than UNDER in connection with shape 145 so that S22 branches to S25 and LAST is set equal to FIRST. In connection with shape 145, FIRST was already set to +2, in connection with S19. Therefore, LAST becomes set equal to +2 in S25. The meaning is in S25 that the shape 145 can be scanned entirely in one partition. The shape 145 is therefore not divided along the boundary 120(12/5) but is scanned entirely within the partition 106-5. The above method places shape 145 in the partition that shape 145 would be most centrally located within.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that those changes in form and details may be made therein without departing from the spirit and the scope of the invention.
Claims
What is claimed is:
1. The method of scanning a pattern on a work piece where the pattern covers a pattern area and where the pattern area is divided into a plurality of contiguous partitions each having a partition area smaller than said pattern area, the steps comprising, generating for an exposing beam a scan field having a scan area greater than said partition area, relatively moving said scan field and said work piece to successively move said scan field to scan each of said partitions whereby an overlapping boundary region exists between the scan field relative to one of said partitions and the scan field relative to another one of said partitions contiguous to said one of said partitions, selectively controlling the exposing beam in said overlapping boundary region to selectively expose portions of said pattern in said boundary region either in connection with the scan field of said one of said partitions or in connection with the scan field of said another one of said partitions.
2. The method of claim 1 including controlling said exposing beam in said overlapping boundary region to expose portions of said pattern, located in said boundary region and located within said one of said partitions, only in connection with the scan field of said another one of said partitions.
3. The method of claim 1 wherein said pattern is defined by a plurality of abutting shapes having a location and size identified with respect to a common origin for said pattern area, the additional step comprising allocating said shapes among said partitions in accordance with a predetermined algorithm whereby a single exposure of all portions of each shape occurs.
4. The method of claim 3 wherein said algorithm includes the step of allocating shapes contained entirely within said one of said partitions entirely to said one of said partitions.
5. The method of claim 3 wherein said algorithm includes the step of allocating a shape, contained in said one of said partitions and contained only within that portion of said another one of said partitions within said overlapping boundary region, entirely to said one of said partitions.
6. The method of claim 4 wherein said algorithm includes the step of exposing a shape which is contained entirely within said overlapping boundary region entirely within said one or said another one of said partitions having the largest percentage of the area of said shape.
7. The method of claim 3 wherein said algorithm is executed for each shape first in one direction to determine partitioning along one axis and thereafter in an orthogonal direction to determine partitioning along a second axis orthogonal to said first axis.
8. The method of claim 3 wherein said partitions are arrayed in orthogonal rows and columns and wherein said algorithm is executed first with respect to said columns to determine allocation of shapes within each column of said partitions and whereafter said algorithm is executed with respect to rows for each of the shapes in each of said columns whereby the row and column allocation of each shape is determined.
9. The method of claim 8 including the step of sorting the shapes allocated to each partition, exposing each shape allocated to a particular partition, and relatively moving the scan field and the work piece to a next partition, and exposing each shape allocated to said next partition.
10. The method of claim 9 wherein said shapes are rectangles.
11. An apparatus for scanning a pattern on a work piece where the pattern covers a pattern area and where the pattern area is divided into a plurality of contiguous partitions each having a partition area smaller than said pattern area, comprising, means for generating a scan field having a scan area greater than said partition area, means for relatively moving said scan field and said work piece to successively move said scan field to scan each of said partitions whereby an overlapping boundary region exists between the scan field relative to one of said partitions and the scan field relative to another one of said partitions contiguous to said one of said partitions, control means for selectively controlling the exposing beam in said overlapping boundary region to selectively expose portions of said pattern in said boundary region either in connection with the scan field of said one of said partitions or in connection with the scan field of said another one of said partitions.
12. The apparatus of claim 11 wherein said control means includes means for controlling said exposing beam in said overlapping boundary region to expose a portion of said pattern, located in said boundary region and located within said one of said partitions, only in connection with the scan field of said another one of said partitions.
13. The method of scanning a pattern on a resist-coated work piece to form semiconductor circuits where the pattern covers a pattern area and where the pattern area is divided into a plurality of partitions each having a partition area smaller than said pattern area where adjacent partitions abut along a partition boundary, the steps comprising, generating for an exposing beam, a scan field having a scan area greater than said partition area, relatively positioning said scan field and said work piece with some positional error to successively move said scan field to scan each of said partitions whereby an overlapping boundary region exists between the scan field relative to one of said partitions and the scan field relative to another one of said partitions contiguous to said one of said partitions, said overlapping boundary region containing portions of said pattern defining particular dimensions of the semiconductor circuit, said positional error being substantial with respect to said particular dimensions, selectively controlling the exposing beam in said overlapping boundary region to selectively expose portions of said pattern in said boundary region either in connection with the scan field of said one of said partitions or in connection with the scan field of said another one of said partitions whereby said particular dimensions are exposed entirely in said one or in said another one of said partitions so that said positional error does not alter said particular dimensions.
14. An apparatus for scanning a pattern on a resist-coated work piece to form semiconductor circuits where the pattern covers a pattern area and where the pattern area is divided into a plurality of partitions each having a partition area smaller than said pattern area where adjacent partitions abut along a partition boundary, comprising, means for generating for an exposing beam, a scan field having a scan area greater than said partition area, means for relatively positioning said scan field and said work piece with some positional error to successively move said scan field to scan each of said partitions whereby an overlapping boundary region exists between the scan field relative to one of said partitions and the scan field relative to another one of said partitions contiguous to said one of said partitions, said overlapping boundary region containing portions of said pattern defining particular dimensions of the semiconductor circuit, said positional error being substantial with respect to said particular dimensions, means for selectively controlling the exposing beam in said overlapping boundary region to selectively expose portions of said pattern in said boundary region either in connection with the scan field of said one of said partitions or in connection with the scan field of said another one of said partitions whereby said particular dimensions are exposed entirely in said one or in said another one of said partitions so that said positional error does not alter said particular dimensions.
15. An electron beam apparatus for scanning a pattern on a resist-coated work piece to form semiconductor circuits where the pattern covers a pattern area and where the pattern area is divided into a plurality of partitions each having a partition area smaller than said pattern area where adjacent partitions abut along a partition boundary, comprising, an electron beam column apparatus having means for generating an electron beam, blanking means for selectively blanking the electron beam in connection with scanning a pattern, and deflection means for deflecting the electron beam, generator means for providing control signals to said deflection means to scan said electron beam over a scan field having a scan area greater than said partition area, positioning means for positioning said work piece at commanded positions relative to said scan field, control means for successively supplying commanded positions to said positioning means whereby said work piece is positioned relative to said scan field to scan each of said partitions with an overlapping boundary region between the scan field relative to one of said partitions and the scan field relative to another adjacent one of said partitions, said overlapping boundary region containing portions of said pattern defining particular dimensions of a semiconductor circuit, said one of and said adjacent one of said partitions abutting in said boundary region with some positional error, means for measuring the actual position of said electron beam on said work piece, means for forming error signals as a function of the difference between said commanded position and said actual position, means for adding said error signals to said control signals whereby said electron beam is positioned more accurately relative to said work piece, means for selectively controlling said blanking means for selectively blanking the electron beam during the scanning of said overlapping boundary region to selectively expose portions of said pattern in said boundary region either in connection with the scan field of said one of said partitions or in connection with the scan field of said another one of said partitions whereby said particular dimensions are exposed entirely in said one or in said another one of said partitions so that said positional error does not affect said particular dimensions.
16. The apparatus of claim 15 wherein said means for selectively controlling includes memory means for separately storing digital representations of portions of the pattern for each separate partition area and includes means for accessing said digital representations for each separate partition area one at a time for each partition area.
17. The apparatus of claim 16 wherein said generator means includes means for controlling said scanning for positions of said electron beam having corresponding digital representations in said memory means.
18. The apparatus of claim 17 wherein said digital representations include X axis and Y axis representations.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3875416 | 1975-04-01 | Spicer | |
| US3900737 | 1975-08-01 | Collier et al. |