Voltage Clamp Device for Monolithic Circuits

This invention relates to voltage clamping circuits, and more particularly to a circuit and method for providing symmetrical voltage clamping to an input signal to an integrated circuit (IC) without producing undesirable parasitic currents.

In the past, an IC was protected from large positive and negative voltage input signals by connecting the input of the IC in series with a limiting resistor in parallel with a zener diode. The co-inventor of the present invention, William Davis, has described significant problems associated with this technique in an article titled, "Bipolar Design Considerations for the Automotive Environment," IEEE Journal of Solid State Circuits, December, 1973, pp. 419-426. An example of such a problem occurs in response to large positive input signals which can cause significant power dissapation in the zener diode which is undesirous. An even worse condition may occur due to large negative input voltage transients.

Negative voltage transients, applied to any N-epi region with sufficient magnitude to forward bias the N-epi/P-substrate can seriously degrade functional IC performance due to the injection of electrons into the substrate (substrate injection). These minority charge carrier electrons will diffuse throughout the P-substrate region until they recombine or are collected by other reversed biased N-epi regions. As described in the above reference article, undesirous currents are established by the formation of a parasitic lateral NPN transistor which may be defined. Hence, circuit malfunction could result due to the parasitic collection of substrate injected electrons. Standard clamping techniques such as a zener diode clamp or even the conventional forward biased IC diode cannot be used as clamping devices for negative transients since substrate injection will occur as prescribed.

Thus, a need exists for symmetrically clamping the input voltage signal to the IC within a particular magnitude without producing the substrate injection of electrons.

Accordingly, it is an object of the present invention to provide a voltage clamp circuit and method for limiting an alternating input signal applied thereacross to predetermined values to protect monolithic integrated circuits including the clamp circuit without producing detrimental currents.

In accordance with the foregoing there is provided a voltage clamp circuit for use in monolithic currents which symmetrically clamps an applied input signal between particular magnitudes. The voltage clamp circuit comprises a first and a second electron control device having first, second and control electrodes, respectively. The first electrode of the first electron control device is adapted to be connected to an input terminal of the monolithic circuit, the second electrode thereof is coupled to the substrate of the monolithic circuit by the first and second electrodes of the second electron control device. The control electrodes of the first and second electron devices are also interconnected. This structure clamps the magnitude of an applied input voltage to the input terminal between a particular value as well as preventing deleterious effects of substrate injection.

FIG. 1 illustrates the circuit of the present invention in schematic diagram form;

FIG. 2 is a cross section of a monolithic integrated circuit showing the formation of the present invention disposed therein;

FIG. 3A illustrates the circuit of FIG. 1 with a positive voltage input signal applied thereto;

FIG. 3B illustrates the equivalent circuit of the circuit of FIG. 3A;

FIG. 4A illustrates the circuit of FIG. 1 with a negative input voltage applied thereto; and

FIG. 4B illustrates the equivalent circuit of the circuit of FIG. 4A.

Referring to FIGS. 1 and 2, there is shown voltage clamp circuit 10 which is suitable for clamping the magnitude of a voltage applied thereacross, e.g., to approximately .+-.7.8 volts. Voltage clamp circuit 10 is suitable to be fabricated as a part of integrated circuit (IC) 12 (shown in dashed outline) which may include other circuitry disposed therein (not shown) such as amplifiers, oscillators and etc. coupled to terminal 28. Voltage clamp circuit 10 comprises transistors Q1 and Q2 which are fabricated using known monolithic techniques during fabrication of IC-12. Transistors Q1 and Q2 may be bipolar NPN devices.

As illustrated in FIG. 2, IC-12 consists of a P-type substrate 14 into which N-type epi-regions or islands 16 and 18 are fabricated to form the collectors of transistors Q1 and Q2, respectively. Using standard photoetching and diffusion techniques, transistors Q1 and Q2 are completed with base P-type regions 20 and 22 and N+-type regions 24 and 26, respectively. It is to be understood that IC-12 may include other transistors and devices formed in a like manner as transistors Q.sub.1 and Q.sub.2. Again, using standard metallization pattern techniques, the emitter electrode or region 24 is connected to input terminal 28 of the IC. Collector regions 16 and 18 of transistors Q1 and Q2 are interconnected by a metal layer 21 (shown schematically) to each other and to P-type substrate 14 which, in a preferred embodiment, is connected to a ground reference potential. Similarly, emitter region 26 of Q2 is also connected to substrate 14 through a metallization connection illustrated as reference numeral 23. Clamp circuit 10 is completed by interconnecting base electrodes 20 and 22 of the transistors, via lead 25. It is to be understood that voltage clamp circuit 10, by clamping the magnitude of a voltage signal supplied across the IC between terminal 28 and ground reference, limits the maximum possible voltage swing which can be developed across the other circuits comprising IC-12. Thus, protection is provided to the IC from otherwise large voltage input transients which may occur at terminal 30 and be applied to terminal 28 via resistor 32. For instance, as shown outlined in phantom, an alternating voltage signal is supplied to terminal 30 from source generator 33. Source 33 may, for example, be an input signal from an alternator in an automobile ignition system or any other source and IC-12 could be a zero voltage switch which is utilized to determine when the applied signal from source 33 crosses the zero axis.

Referring to the remaining Figures, the operation of voltage clamp circuit 10 can be explained as the input voltage, V.sub.IN, varies from a positive to a negative value. Specifically, referring to FIGS. 3A and 3B there is shown voltage clamp circuit 10 with a positive input voltage applied at terminal 30. As the voltage at terminal 30 exceeds the reverse breakdown voltage of the base-emitter junction of transistor Q1 zenering action is established and a zener current, I.sub.Z, flows out of the base of transistor Q.sub.1. The resultant circuit is shown in FIG. 3B wherein the base-emitter junction of transistor Q1 is shown as zener diode, Z.sub.D. Diode, D.sub.1 is formed by the emitter-base junction of transistor Q2 with diode D.sub.2 being formed by the parallel combination of the collector-base junctions of transistors Q1 and Q2, respectively. Hence, the voltage developed between terminal 28 and ground reference is equal to the zener breakdown voltage of Z.sub.D, which in the preferred embodiment may be 7 volts, plus the base-to-emitter junction voltages of diodes D.sub.1 and D.sub.2 which for silicon is equal to approximately 0.8 volts. Therefore, the magnitude of voltage which can be developed at the input to the IC is limited or clamped to approximately +7.8 volts. Under this condition no N.sub.epi region is forced negative.

For negative voltage clamp conditions, as illustrated in FIGS. 4A and 4B, in response to the applied voltage V.sub.IN reaching a value which causes the voltage applied across voltage clamp circuit 10 to be greater than or equal to the zener breakdown voltage of the emitter-to-base junction of transistor Q2, zener current I.sub.Z flows therethrough to the base of transistor Q1 which acts as a normal active transistor. Hence, the voltage is limited to approximately a -7.8 volts. Notice again no N.sub.epi region is forced negative.

What has been described above, is a novel voltage clamp circuit comprising two interconnected transistor devices for symmetrically clamping the input voltage to an integrated circuit to .+-.7.8 volts approximately. The unique structure prevents the collector-epi regions that normally form the collectors of bipolar transistors of an integrated circuit from being forward biased; substrate injection is therefore prevented. Thus, stray currents which may have a deleterious effect on the function of the system are eliminated. The unique voltage clamp circuit described above does not force any epi-island region to go below ground reference potential and thus prevents substrate injection of electrons.

As an aside, it should be noted that since the base and collectors of transistors Q1 and Q2 are common, they can be built as a single multi-emitter NPN in a single epi-island.