Sawtooth Generator

The invention relates to a circuit for generating a sawtooth voltage across a first capacitor which is periodically charged by a charging current, comprising an amplifying element having an input electrode and a first and a second output electrode, a resistor a connection of which is connected to the first output electrode of the amplifying element and the other connection to the first capacitor one end of which is connected to a first terminal of an power supply source, while the second output electrode of the amplifying element is connected to the second terminal of the power supply source, furthermore comprising a second capacitor which is included between the input electrode of the amplifying element and the junction of the first capacitor and the resistor and a switch which is in parallel with the first capacitor for periodically discharging this capacitor.

Such a sawtooth generator is known from United Kingdom Patent Specification 924,224 and is shown in FIG. 1. Herein Tr represents an npn-transistor whose collector is connected to the positive terminal of the power supply source V.sub.B and the emitter to the resistor R. C.sub.1 and C.sub.2 respectively represent the first and the second capacitor respectively whereas S is the switch. The connection of capacitor C.sub.2 which is not connected to resistor R and to capacitor C.sub.1 as well as the cathode of a diode D are connected to the base of transistor Tr. The anode of diode D is connected to the positive terminal of a d.c. voltage source V. The negative terminal of both sources V.sub.B and V as well as the connection of capacitor C.sub.1 not connected to resistor R and switch S respectively are connected to chassis. Source V is derived from source V.sub.B by means of two resistors R' , R" connected in series between terminals thereof and a decoupling capacitor C.

Capacitor C.sub.1 is periodically charged by the emitter current i.sub.e of transistor Tr and it is discharged by switch S. At the beginning of the charging process, that is to say at the instant at which switch S is opened diode D is rendered non-conducting by feedback through capacitor C.sub.2 which has a large capacitance. Across resistor R there is a voltage which is approximately constant so that current i.sub.e is substantially constant. The voltage v.sub.1 across capacitor C.sub.1 increases from zero linearly versus the time. The portion of current i.sub.e which flows to capacitor C.sub.2 and the base of transistor Tr is neglected. At the end of the charging process, i.e. at the instant at which switch S is closed, voltage V.sub.2 assumes its maximum value V.sub.1. If the charging time is indicated by T and if C.sub.1 also indicates the capacitance of capacitor C.sub.1 then is holds that i.sub.e T = C.sub.1 V.sub.1 wherein i.sub.e = V.sub.2 /R. Herein V.sub.2 is the voltage across capacitor C.sub.2 which is assumed to be constant whereas the base-emitter voltage v.sub.be of transistor Tr has been neglected with respect to V.sub.2.

The foregoing shows that

wherein f = 1/T is the frequency of the signal which operates switch S, the duration of the discharging process being assumed to be very short relative to time T. So in the prior art circuit of FIG. 1 firstly the charging current of the first capacitor and consequently the steepness of the sawtooth is constant and secondly the amplitude of the sawtooth voltage obtained is inversely proportional to the frequency. If, for example, the synchronizing frequency of switch S is twice as high then the amplitude of the sawtooth is twice as low. No requirement is imposed on the value of resistor R.

It is an object of the invention to modify the discussed, simple circuit in such a way that the amplitude of the generated sawtooth voltage remains substantially constant and is especially substantially independent of the frequency while retaining the proper linearity of the original circuit. Such a sawtooth generator is important in the television technology for the field deflection (that is to say into the vertical direction with the frequency 50 or 60 Hz respectively). As the average value of the sawtooth generated hereby is in the synchronized state substantially equal to that in the non-synchronized state, a smaller instability takes place then would otherwise be the case. Such an instability is described in U.S. Pat. 3,988,638 and is caused by variations in the amplitude of the sawtooth if the frequency characteristic of the field output amplifier shows a peak at low frequencies. Without the measures proposed in said Patent the displayed picture oscillates in the vertical direction. If the amplitude is constant then, with a proper dimensioning one charging period of the first capacitor will indeed be shorter during synchronization than the preceding charging period but already the next charging period will be of the normal duration so that voltage V.sub.1 will have the correct value. A very small disturbance is the result thereof.

The circuit according to the invention is characterized in that the input electrode of the amplifying element is connected to a d.c. voltage source whose internal resistance forms with the second capacitor a network the time constant of which is large relative to the charging time of the first capacitor.

The invention will be further explained by way of non-limitative example with reference to the accompanying Figures in which:

FIG. 1 shows the prior art generator discussed above;

FIG. 2 shows a circuit diagram of the generator according to the invention, while

FIG. 3 shows a more complete diagram thereof and

FIG. 4 shows a variant of the circuit of FIG. 3.

In the circuit of FIG. 2, relative to that of FIG. 1 diode D is replaced by a resistor R.sub.2 while emitter resistor R now has the symbol R.sub.1. Resistor R.sub.2 has a high value, in any case much higher than the parallel arrangement of resistors R' and R" which in the prior art circuit of FIG. 1 determine voltage V by means of voltage division and which, on the contrary, have rather low values so that the voltage V and, consequently, voltage V.sub.2 remain constant.

No direct current can flow through capacitor C.sub.2. If the base current of transistor Tr is neglected which means that the current gain of the transistor is assumed to be very high then it can be assumed that substantially no direct current flows through resistor R.sub.2. The average value of the voltage at the base is, consequently, equal to V and the average value of the voltage at the emitter is V-v.sub.be. If the value of resistor R.sub.1 and the capacitance of capacitor C.sub.1 are chosen so that the voltage drop caused by current i.sub.e across resistor R.sub.1 is contrary to FIG. 1 negligibly small relative to voltage V and if the variation of voltage V.sub.be is also assumed to be very small then the average value of the voltage v.sub.1 across capacitor C.sub.1 is constant and approximately equal to V. The maximum value V.sub.1 of voltage v.sub.1 is twice as high, i.e. approximately 2V as the minimum value hereof is zero owing to the operation of switch S so that also V.sub.1 is constant. Because V.sub.1 is approximately equal to 2V, voltage V must be smaller than half V.sub.B. If not, transistor Tr becomes saturated at the end of the charging period. It can be recognized that the charging current of capacitor C.sub.1 is not constant but approximately proportional to the frequency. This is shown in FIG. 2 by means of dashed lines from which it appears clearly that the slope of the sawtooth, which is a measure of said current becomes steeper in proportion as the frequency increases while amplitude V.sub.1 remains unchanged. The above-mentioned condition that voltage drop i.sub.e R.sub.1 is small implies that the time constant R.sub.1 C.sub.1 is small relative to time T.

Expressed more accurately than above the average value of voltage v.sub.1 is equal to V-v.sub.be -i.sub.e R.sub.1, so that V.sub.1 = 2(V-v.sub.be -i.sub.e R.sub.1). If for the voltage drop i.sub.e R.sub.1 across resistor R.sub.1 a value is chosen which is only 1% of voltage V then V.sub.1 =2 (0.99 V-v.sub.be). If now the frequency with which switch S opens and closes is increased by, for example, 10% which means that the number of discharges of capacitor C.sub.1 per unit of time increases by 10% then current i.sub.e and, consequently, voltage drop i.sub.e R.sub.1 also increases by 10%: so i.sub.e R.sub.1 becomes 1.1.times.0.01V = 0.011V. Amplitude V.sub.1 becomes 2(0.989V-v.sub.be). From this it appears that increasing the frequency by 10% only results in a decrease of approximately 1 per thousand in the amplitude of the output voltage.

In actual practice this reduction will be slightly larger because the current gain of transistor Tr is not infinitely large. Consequently, across resistor R.sub.2 there is yet a d.c. voltage which is higher in proportion as the frequency is higher. For this reason transistor Tr may be replaced by a so-called Darlington pair or by an amplifier combination of two transistors Tr.sub.1 and Tr.sub.2, the collector of Tr controlling the base of Tr.sub.2. Herein the current gain factor is a product of the individual factors so that a value of 3000 or more can be achieved. In FIG. 3 transistors Tr.sub.1 and Tr.sub.2 are of the complementary conductivity types. As known, the emitter of transistor Tr.sub.2 herein functions as the collector of the combination. In this manner it is ensured that the amplitude is substantially independent of the frequency which cannot be accomplished by reducing the base current of transistor Tr in FIG. 1, as this current is determined by current i.sub.1 and consequently by V.sub.1 and by f.

Source V can be dispensed with because two resistors R'.sub.2 and R".sub.2 are arranged in series between both the terminals of source V.sub.B. The parallel arrangement hereof has the value R.sub.2 and the junction point hereof is connected to the base of transistor Tr.sub.1. The values of resistors R'.sub.2 and R".sub.2 are chosen so that the average value of the voltage at said junction point is equal to voltage V. As it must be possible for an a.c. voltage to be present at the base of transistor Tr.sub.1 said junction point is not decoupled, this in contradistinction with the circuit of FIG. 1 in which the junction point of resistors R' and R" must indeed be decoupled so that voltage V remains constant, which is also ensured by the fact that both resistors have comparatively low values. It is evident that the network R'.sub.2, R".sub.2 is equivalent to a resistor of high value which would be connected between the base of transistor Tr.sub.1 and the junction point of two resistors of comparatively low values, which junction point would be decoupled.

From the circuit diagram of FIG. 2 it appears that the alternating current which flows through resistor R.sub.2 also flows through capacitor C.sub.2 and produces a parabolic voltage across it. For, this current is, just like the a.c. voltage across resistor R.sub.2, sawtooth shaped. A condition for this is that capacitor C.sub.2 has a capacitance which is not infinitely large. The parabolic voltage is added to the voltage present across capacitor C.sub.2 and that in such a way that the sum in the middle of the cycle is enlarged. As current i.sub.e and, consequently, the slope of voltage v.sub.1 are determined by this sum, it follows that voltage v.sub.1 varies in a steeper manner in the middle of the cycle than at the beginning and the end thereof. So it has the S-shape required for the deflection. It is evident that the proper form is determined by the value of resistor R.sub.2 and, consequently, by that of resistors R'.sub.2 and R".sub.2 in FIG. 3 and by the capacitance of capacitor C.sub.2 : the time constant R.sub.2 C.sub.2 must be large relative to time T.

However, the above-mentioned sawtooth-shaped current which flows through capacitor C.sub.2 produces a parabolic voltage across capacitor C.sub.1 which is unwanted as it is added to voltage v.sub.1, the sum thus obtained having a larger steepness at the beginning of the cycle than after it. The linearity error caused in this manner can be reduced by giving resistor R.sub.2 such a high value that the time constant of the network constituted by R.sub.2 and the series arrangement of capacitors C.sub.1 and C.sub.2 is very large relative to time T. As a consequence the sawtooth-shaped current through resistor R.sub.2 is kept low. In addition the error can be corrected in the manner shown in FIG. 3.

The node of components C.sub.1, C.sub.2, and R.sub.1 is connected to the base of a transistor Tr.sub.3 whose emitter is connected through a resistor R.sub.3 to chassis and the collector through a resistor R.sub.4 to the emitter of a further transistor Tr.sub.4. The collector of transistor Tr.sub.4 is connected to the positive terminal of source V.sub.B while the base thereof is connected to a voltage V' which is lower than voltage V.sub.B. The base of a transistor Tr.sub.5 is connected to the collector of transistor Tr.sub.3 while its collector is connected to the base of that same transistor Tr.sub.3 and its emitter through a resistor R.sub.5 to the source of voltage V'. Resistors R.sub.4 and R.sub.5, transistor Tr.sub.5 and the base-emitter diode of transistor Tr.sub.4 constitute a so-called current mirror, wherein the collector current of transistor Tr.sub.5 is equal to that of transistor Tr.sub.3 if resistors R.sub.4 and R.sub.5 have the same values.

As the sawtooth component of voltage v.sub.1 during the charging period is an increasing function of the time also the emitter current of transistor Tr.sub.3, and consequently, also the collector current of transistor Tr.sub.5 has a rising sawtooth-shaped variation. In contradistinction therewith the variation of the sawtooth-shaped current through capacitor C.sub.2 is falling. FIG. 2 shows that the sawtooth-shaped voltage difference between the base of transistor Tr and the connection of resistor R.sub.2 which is shown on the left in the drawing, is falling. Both the said currents flow through capacitor C.sub.1 and eliminate each other there provided resistors R.sub.2 and R.sub.3 are of the same value. If the value of resistor R.sub.3 is adjustable around the value of resistor R.sub.2 then a parabolic component of one or the other polarity can be added to voltage V.sub.1 so that the linearity of the output signal available across capacitor C.sub.1 is adjustable. It is true that the amplitude of this signal depends on the value of the added parabolic component but in practice this fact causes few difficulties because the required linearity correction is only slight. Because the amplifier which amplifies the output signal of the circuit of FIG. 3 behaves as a high-pass filter overcompensation may be desired. An advantage of the described compensation circuit is that the capacitance of capacitor C.sub.1 now has a non-critical value.

Switch S may be designed as a transistor which is periodically rendered conductive by the synchronizing pulses. It may, however, be desired to make the circuit selfoscillating so that an output signal is available also in the absence of these pulses. Such a modification of the circuit is also shown in FIG. 3.

A resistor R.sub.6 has been included in the collector lead of the combination constituted by transistors Tr.sub.1 and Tr.sub.2. The voltage drop across this resistor is the sum of the d.c. voltage which is proportional to the frequency, and a parabolic voltage whose amplitude, just like that of the voltage with the same shape across capacitor C.sub.2 is inversely proportional to the frequency. FIG. 3 shows the variation of the collector voltage of the combination Tr.sub.1, Tr.sub.2. Herein the discharging time of capacitor C.sub.1 is assumed to be infinitely short so that said variation is then peak-shaped instead of parabolic. As the amplitude of the parabola is small relative to the d.c. voltage and because the frequency variation to be expected is small, namely approximately 10%, between the synchronized and the non-synchronized state in the case of a field oscillator, the difference between the dotted d.c. voltage level and that of the peaks can be neglected and said last level can be chosen for introducing the oscillation.

The collector of the combination Tr.sub.1, Tr.sub.2 is connected to the base of a pnp-transistor Tr.sub.6 whose emitter is connected to the collector of an npn-transistor Tr.sub.7. The base hereof is supplied via a capacitor C.sub.3 with the positive-going synchronizing pulses and is biased by means of a voltage divider R.sub.8, R.sub.9 while the collector of transistor Tr.sub.7 is connected to a resistor R.sub.7 whose other end is connected to source V.sub.B. The collector of transistor Tr.sub.6 is connected to the base of a transistor Tr.sub.8 whose collector is connected to the cathode gate of a thyristor which is formed by two transistors Tr.sub.9 and Tr.sub.10 of complementary conductivity types. This cathode gate is constituted by the interconnected base of transistor Tr.sub.9 and collector of transistor Tr.sub.10. The cathode of the thyristor, i.e. the emitter of transistor Tr.sub.9 as well as the emitter of transistor Tr.sub.8 are connected to chassis, whereas the anode, i.e. the emitter of transistor Tr.sub.10 is connected directly and the anode gate, i.e. the interconnected collector of transistor Tr.sub.9 and base of transistor Tr.sub.10 via a separating resistor R.sub.10 to the node of components R.sub.1, C.sub.1 and C.sub.2.

The base bias voltage of transistor Tr.sub.7 is adjusted by the choice of resistors R.sub.8 and R.sub.9 in such a way that in the absence of synchronizing pulses the collector voltage of transistor Tr.sub.7 has a value at which transistor Tr.sub.6 is conducting if its base voltage is lower than the peaks of the parabola. During the charging period of capacitor C.sub.1 transistor Tr.sub.8 is driven to saturation and thyristor Tr.sub.9, Tr.sub.10 is rendered non-conducting. A resistor R.sub.11 is connected between the collector of transistor Tr.sub.8 and source V.sub.B. Consequently the collector current of transistor Tr.sub.8 flows through resistor R.sub.11.

As soon as, however, the collector voltage of transistor combination Tr.sub.1, Tr.sub.2 assumes its maximum value at the end of the charging period transistor Tr.sub.6 is rendered non-conducting. Transistor Tr.sub.8 is also rendered non-conducting so that the current through resistor R.sub.11 now flows to the cathode gate of thyristor Tr.sub.9, Tr.sub.10. As a result the thyristor is conducting and the discharge of capacitor C.sub.1 is introduced. Through a resistor R.sub.12 the base of switch S is supplied with retrace pulses which are derived from the output amplifier (not shown in the drawing) which pulses are of a longer duration than those required to fully discharge capacitor C.sub.1. This ensures a proper interlacing.

By designing voltage divider R.sub.8, R.sub.9 as a potentiometer or by designing the emitter resistor R.sub.13 of transistor Tr.sub.7 as a variable resistor the cut-off level of transistor Tr.sub.6 and, consequently, the frequency can be adjusted.

If the synchronizing pulses are present at the base of transistor Tr.sub.7 then they are amplified by the transistor. During the occurrence of these pulses the emitter voltage of transistor Tr.sub.6 decreases which introduces the discharge of capacitor C.sub.1 in the manner already described.

The sawtooth voltage generated by the circuit across capacitor C.sub.1 is supplied to the output amplifier mentioned above. A resistor R.sub.14 is included between a point hereof at which, during the trace period of the field deflection a decreasing voltage is present and the emitter of transistor Tr.sub.7. Hereby it is accomplished that the emitter voltage of transistor Tr.sub.7 increases immediately after the occurrence of the synchronizing pulses. The collector voltage then increases also. As a consequence transistor Tr.sub.6 is firmly kept conducting which renders the circuit insensitive to interferences occurring after the retrace period and during the largest portion of the trace period. For, this measure ensures that transistor Tr.sub.6 is only cut-off during the occurrence of the pulses.

If no great store is set by self-oscillating of the circuit, for example because the circuit itself is controlled by an oscillator which supplies a signal also in the absence of synchronizing pulses, then the base and the emitter of transistor Tr.sub.7 can be interconnectred while resistors R.sub.8, R.sub.9 and R.sub.13 are omitted. Through a zener diode Z and resistor R.sub.12 the synchronizing and oscillator signal respectively reach the base of switch S.

In a practical embodiment of the circuit of FIG. 3 the following values were chosen:

R.sub.1 : 390 .OMEGA.

r.sub.2 ': 2.2 m.OMEGA.

r.sub.2 ": 3.3 m.OMEGA.

r.sub.3 : 1.2 m.OMEGA.

r.sub.4 and R.sub.5 : 5.6 k.OMEGA.

R.sub.6 and R.sub.7 : 5.6 k.OMEGA.

R.sub.8 and R.sub.9 : 5.6 k.OMEGA.

R.sub.10 : 18 k.OMEGA.

R.sub.11 : 10 k.OMEGA.

R.sub.12 : 3.3 k.OMEGA.

R.sub.13 : 22 k.OMEGA.

R.sub.14 : 47 k.OMEGA.

V.sub.b : 20 volts

i.sub.e : 0.25 mA

C.sub.1 : 680 nF

C.sub.2 : 330 nF

in view of the large number of components of the circuit discussed and of the output amplifier the whole assembly, capacitors C.sub.1 and C.sub.2 and the high- value resistors excepted, can be advantageously integrated in a semiconductor body. A plurality of temperature stabilizing components are then added in known manner.

If the circuit is designed by means of discrete components then the simplified circuit of FIG. 4 can be used. Capacitor C.sub.2 is not connected to the junction points of components R.sub.1 and C.sub.1 but to the emitter of an emitter follower-transistor Tr.sub.11 whose base is connected to said junction point. In this manner the sawtooth current flowing through a resistor R.sub.2 does not flow through capacitor C.sub.1. By means of a resistor R.sub.15 which is connected to the emitter of transistor Tr.sub.11 and of a resistor R.sub.16 which connects the collector of transistor Tr.sub.1 to resistor R.sub.15 an overcompensating parabolic voltage is added to the generated sawtooth voltage. So the described linearity correction circuit replaces that of FIG. 3. However, undercompensation is not possible herewith.

In the circuit of FIG. 4 the self-oscillation is effected by means of only one transistor Tr.sub.12 of the pnp-type whose emitter is connected to the collector of transistor Tr and the collector to the base of transistor S, while its base is connected by means of a potentiometer R.sub.17 and two resistors R.sub.18 and R.sub.19 to an adjustable voltage. A capacitor C.sub.4 is connected between the collector of transistor S and the base of transistor Tr.sub.12. If the parabolic voltage present at the collector of transistor Tr reaches a value determined by potentiometer R.sub.17 then resistor Tr.sub.12 conducts and, consequently, transistor S also. This introduces the discharging of capacitor C.sub.1. The decrease in voltage V.sub.1 is transferred through capacitor C.sub.4 to the base of transistor Tr.sub.12. This transistor remains conductive, so that capacitor C.sub.1 is fully discharged until capacitor C.sub.4 is charged, which depends on its capacitance and on the resistances in the base lead of transistor Tr.sub.12. This determines the duration of the retrace period. The positive-going synchronizing pulses can be supplied to the collector of transistor Tr or to the base of transistor S, whereas R.sub.17 determines the natural frequency of the oscillator.

In a practical embodiment of the circuit of FIG. 4 the following values were chosen:

R.sub.1 : 2.2 k.OMEGA.

R.sub.2 : 1.2 m.OMEGA.

r.sub.6 : 27 k.OMEGA.

R.sub.17 : 10 k.OMEGA.

R.sub.18 : 15 k.OMEGA.

R.sub.19 : 120 k.OMEGA.

V.sub.b : 25 volts

V : 10.4 volts

C.sub.1 : 220 nF C.sub.2 : 270 nF

C.sub.4 : 5.6 nf

It will be obvious that transistor Tr and combination Tr.sub.1, Tr.sub.2 respectively may be replaced by another amplifier component such as, for example, a field effect transistor or an electron tube.