Electronic Calculator or Microprocessor Having a Hexadecimal/Binary Coded Decimal Arithmetic Unit

Background of the Invention

Brief Description of the Drawings

Detailed Description of Specific Embodiment

Detailed Description of System Logic Diagram

The ROM and Program Counter

The Subroutine Stack

The Branch Logic and Condition Latch

The Test Circuitry

The Instruction Word Decoder Logic

Register Address Buffer

Storage Register Input/Output Circuit

The Operational Register Selector Gates

Arithmetic Unit

Register R5

Scan Generator Counter and Segment/Keyboard Scan

Keyboard Logic

Display Decoder

Output Register

State Time Generator

Register Configuration

Tables

Claims

Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:

U.S. Pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "CALCULATOR SYSTEM HAVING AN EXCHANGE DATA MEMORY REGISTER".

U.S. Pat. No. 3,934,233 issued to Roger J. Fisher and Gerald D. Rogers on Jan. 20, 1976 and entitled "READ-ONLY-MEMORY FOR ELECTRONIC CALCULATOR".

U.S. Pat. No. 3,931,507 issued Jan. 6, 1976 to George L. Brantingham entitled "POWER-UP CLEAR IN AN ELECTRONIC DIGITAL CALCULATOR".

The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.

The present invention relates to a hexadecimal/binary coded decimal format arithmetic unit for a microprocessor and more specifically a hexadecimal/binary coded decimal format arithmetic unit for an electronic calculator. An entire eleccalculator system including the hexadecimal/binary coded decimal arithmetic unit of this invention is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, the arithmetic unit of this invention is not limited to the type calculator system disclosed. Electronic calculators of the prior art have typically been operable in a single mode, such as in binary coded decimal format. While such a single mode arithmetic unit may be well suited for use in performing normal arithmetic functions, it has been found that if the data being applied to the arithmetic unit represents, for instance, either the logical status of operations occurring within the calculator or binary coded decimal (BCD) numerals that having an arithmetic unit which automatically preforms the logical operations in binary coded decimal format complicates the interpretation or decoding of the such logical operations.

It is therefore one object of this invention to provide an arithmetic unit operable in a first mode for performing arithmetic operations in hexadecimal and operable in a second mode for performing arithmetic operations in binary coded decimal format. It is yet another object of this invention to provide a second mode of the arithmetic unit with capability to automatically and selectively preform arithmetic operations on BCD inputs in BCD format and to preform operations on flag bit inputs in hexidecimal, that is, equivalently the binary base.

The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, a hexadecimal/BCD arithmetic unit is provided on a semiconductor chip preferably having an input circuit for receiving numeric data and function commands, an address register responsive to the input circuit, an instruction word memory for storing a number os instruction words and addressable in response to the address stored in the address register and instruction word decoder logic for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto. The arithmetic unit is provided with a binary/hexadecimal adder and a BCD corrector. The BCD corrector is disableable according to instruction words read out of the instruction memory or in accordance with timing signals generated on the chip which are indicative of whether the input to the arithmetic unit represents BCD data or flag bit information.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a pictorial view of a portable, electronic, hand-held calculator of the type which may embody the present invention;

FIG. 2 is a functional schematic diagram of a single chip calculator system of the type which may embody the present invention;

FIG. 3 depicts a functional block diagram of the single chip calculator system embodying the present invention;

FIGS. 4a and 4b depict the timing signals generated by a clock implemented in the calculator system, the timing signals being shown in representative form;

FIGS. 5a and 5b depict a segmented display and a manner in which a calculator system may be interconnected therewith;

FIGS. 6a and 6b depict the format of the data word stored in the operational and storage registers of the calculator system, the MASK codes which are used in the instruction words implemented in the read-only-memory and how these various masks relate to the data words;

FIGS. 7a-7c form a logic diagram of the program counter, the branch logic, the test circuitry, the subroutine stack and the read-only-memory of the calculator system;

FIGS. 8a-8i form a logic diagram of the instruction word decoder logic; the operational registers, the storage registers the register address buffer, and the counter associated with the storage registers;

FIG. 9 is a logic diagram of the operational register selector gates;

FIGS. 10a-10d form a logic diagram of the arithmetic unit and the R5 register;

FIG. 11a-11f form a logic diagram of segment/keyboard scan and scan generator counter, keyboard logic, display decoder,output register and state time generator;

FIGS. 12a-12g depict the format of various instruction words described in Table I;

FIG. 13 is a logic diagram of circuits used to interconnect the test circuitry of FIG. 7 with the K1-K4 keyboard line pins of FIG. 11; and

FIG. 14 depicts alternate embodiments of register architecture for the operational and storage registers of the system.

Referring to FIG. 1, an electronic portable calculator the type which may employ features of this invention is shown in pictorial form. The calculator 1 comprises the keyboard 2 and the display 3. The display 3, in one embodiment, consists of 12 digits or characters, each provided by an array of light-emitting diodes, a vacuum fluorescent tube, liquid crystal devices or other display means. The display is preferably implemented having eight mantissa digits, two exponent digits, and two annotator places for signs, et cetera (one place for the mantissa and one place for the exponent), thereby permitting outputting of data in scientific notation. Ordinarily, the display would be of the seven segment or eight segment variety, with provision for indicating a decimal point for each digit. The keyboard 2 or other such input means preferably includes a set of number keys (0-9), a decimal point key, a plurality of function command keys including, for example, exponential, logarithm and trigonometrical functions. The expoential and logarithmic function command keys include, for example, X.sup.2, the square root of X, the reciprocal of X, e.sup.X, the common log of X, and the natural log of X. The trigonometrical functions include for instance the sine, cosine, tangent and their inverses, the hyperbolic sine, hyperbolic cosine, and hyperbolic tangent of X and inverse hyperbolic functions. Other function command keys include store (STO), and recall (RCL), keys for respectively storing and recalling a number stored in one of the memory or storage registers implemented on the chip. The enter exponent key (EE) allows exponent entry of the number displayed in scientific notation. A plus/minus key is provided for changing the sign of the display number. An exchange key (X:Y) is provided for exchanging operator and operand of an arithmetic function. More conventional function command keys are supplied, including the clear key (C), the clear entry key (CE), and the plug (+), minus (-), multiply (.times.), divide (.div.), and equal (=) keys.

Referring now to FIG. 2 there is shown a functional schematic diagram of the single chip calculator system. A single chip 10 is shown here in a standard 28 pin dual-in-line package; however, it is to be understood that how the chip 10 is shown as being interconnected with a 12-character display 11 utilizing a segment scan technique. Each of the seven segments of the character plus the decimal point for each character position are individually connected in common to the segment scan conductors 14. An individual common lead for each character position is connected by bus 15 to chip 10. The details of segment scanning are explained with reference to FIGS. 3 and 5 and it should be evident to one trained in the art that the number of segments selected and the number of characters selected is a design choice.

Chip 10 is interconnected with an X/Y metrix keyboard 12 utilizing five column conductors 16' and eight row conductors 14', the row conductors 14' being individually connected to the segment scan conductors 14 and the column conductors 16' being individually connected via bus 16 to chip 10. An X/Y matrix keyboard having five column conductors 16' and eight row conductors 14' may accommodate up to 40 switches located at the intersections of the conductors; however, the number of conductors 14' and 16' and consequently the number of switches is a design choice. The chip 10 is further connected to a source of DC electrical power through a common connection (Vss) at pin 1, a Vdd connection at pin 2, and a V.sub.DISP connection at pin 3 for the display. Further, a resistor 13 is connected between pins 28 and 1 as a means of controlling the chip's oscillator frequency. External resistor 13 could of course be implemented on chip 10, however, resistor 13 is preferably implemented off chip 10 in order to be able to "fine tune" the frequency of the clock oscillator implemented on chip 10.

Referring now to FIG. 3 there is shown a functional block diagram of the single chip calculator system of this invention showing various circuits implemented on chip 10. A detailed description of the individual function blocks will be discussed subsequently with regard to FIGS. 7, 8, 9, 10 and 11, with only a general functional description of the basic system here set forth. It is to be understood that on the block diagram of FIG. 3, a connection represented by a single line may represent a plurality of actual hardware interconnections, and for ease and simplicity of illustration, a single line may represent a plurality of different functions. The calculator system of this invention includes on chip 10 a main program read-only-memory (ROM) 30, preferably having two sections which may be referred to as ROM A and ROM B. The reason for denoting that ROM 30 has two sections will be subsequently explained in regard to the instruction words implementable in ROM 30. Main program ROM 30 is responsive to an eleven bit ROM address (A.sub.10 -A.sub.0) stored in program counter 32a and produces, in response thereto, a 13 bit instruction word (I.sub.12 -I.sub.0), which is provided to instruction word decoder logic 31. Instruction word decoder logic 31 interprets the instruction word received from ROM 30 and produces in response thereto a plurality of command signals to the other circuits implemented on chip 10. These command signals direct how data is transferred within chip 10, how the data is manipulated by arithmetic unit 40 and serves several other functions which will be explained with reference to the circuits receiving the command signals.

Program counter circuit 32a includes an add-one circuit and is associated with branch logic 32b. The add-one circuit in program counter 32a increments the ROM address stored in the address register in program counter 32a by adding the number one to the address stored in the address register during each instruction cycle, thereby causing the instruction words stored in ROM 30 to be read out sequentially. At times, however, it is advantageous to be able to execute the same instruction word repetitively and therefore the add-one circuit in program counter 32a is responsive to a HOLD command which disables the add-one circuit allowing the address stored in program counter 32a to remain unchanged. Branch logic 32b is responsive to commands generated by instruction word decoder logic 31 for inserting a new ROM address in program counter 32a, thereby permitting the program stored in ROM 30 to "branch" to a new location in ROM 30 rather than cycling sequentially through the instruction words stored in ROM 30. As will be seen with respect to the discussion of the instruction word set and the details of the branch logic 32b and program counter 32a circuits, a branch instruction received from instruction word decoder logic 31 may be either a conditional or an unconditional branch. If unconditional, the branch automatically occurs. If conditional, however, the branch instruction is executed only if the state of the condition latch 41 matches the state of a selected bit in the conditional branch instruction. If a match does not occur, program counter 32a merely cycles to the next sequential ROM address. Thus, branch logic 32b and program counter 32a circuits are interfaced with condition latch 41.

If a branch is to be accomplished, the program counter must be updated with the new ROM address by branch logic 32b. This new ROM address is typically derived from the branch instruction, but as will be seen from the discussion regarding the instruction word set, the new ROM address may also be derived from an address stored in an auxiliary register called R5 register 34. Since R5 register 34 can be loaded with an address corresponding the depression of a particular switch or key on keyboard matrix 12 (FIG. 2) or with number from an operational register 38 supplied via arithmetic unit 40, the new ROM address can be made dependent on the particular keyboard key depressed or can be an "indirect" address generated in one of the operational registers.

Branch logic and program counter circuit 32 is further interconnected with a subroutine stack 33. Subroutine stack 33 is preferably a three level stack having 11 bits per level which receives an incremented ROM address from program counter 32a in response to an unconditional branch command (CALL) and supplies the most recently received ROM address back to program counter 32a in response to a RETURN command received from instruction word decoder logic 31. The ROM address loaded into subroutine stack 33 in response to an unconditional branch command is the incremented address to which program counter 32a would have otherwise cycled. Therefore, when an unconditional branch instruction is encountered in ROM 30, program counter 32a is caused to branch to the address specified by the unconditional branch command and then increments that address by one each instruction cycle until another branch or a return command is received. When a return command is encountered, the most recently stored address in subroutine stack 33 is loaded back into program counter 32a, thus the addressing of the program stored in ROM 30 "returns" to the instruction address following the last unconditional branch instruction word location. Since subroutine stack 33 is a three level stack, three levels of subroutining are possible. Should a fourth address be loaded into subroutine stack 33, the first stored address is lost and only the second through fourth addresses will remain in subroutines stack 33.

R5 register 34 is an eight bit register which stores the two least signiticant digits generated by arithmetic unit 40 unless keyboard logic 35 in combination with a keyboard scan circuit in the scan generator/counter 36 indicates that one of the calculator keyboard keys has been depressed, in which case, an address associated with the key depressed is loaded into R5 register 34. The keyboard key address loaded into R5 register 34 may then be loaded into program counter 32a upon a "Branch on R5" instruction command, thereby permitting the keyboard to address ROM 30. Alternatively, a "branch on R5" instruction command may be utilized to perform indirect addressing by using the contents of one or two of the operational registers 38, as aforementioned. Since program counter 32a is an 11 bit counter, the three most significant bits (MSB's) are loaded with zeros when the eight bit address from R5 register 34 is loaded into program counter 32a.

Referring briefly to FIG. 6a, the format of the data stored in the various operational and storage registers implemented on chip 10 is depicted along with the effect of the various mask codes used in many instruction words. With respect to the format of the data, it can be seen that there are 16 digits (Do-D15) in a data word; preferably, the three most significant digits (MSD's) provide 12 flag bits and the 13 least significant digits (LSD's) provide 13 digits for numeric data. However, as will be seen, the calculator system disclosed has sufficient flexibility to permit the three MSD's to be used either partially or totally for data storage in addition to the 13 LSD's, if desired during certain operations. Whether the calculator is operating in hexadecimal or binary coded deciman (BCD), four binary bits are required to represent each digit. The data word is serially organized, so each data word comprises 64 (e.g. 16 .times. 4) binary bits.

Referring again to FIG. 3, chip 10 is provided with four operational registers A-D) 38 and 16 data storage registers (X.sub.0 -X.sub.7 and Y.sub.0 -Y.sub.7) 39. The operational registers 38 and the storage registers 39 are each 64 bit shift registers, accommodating the 64 bit format of the data words. The 16 bit data storage registers 39 are separated into X and Y groups, each group comprising eight serially connected registers, thus each group of eight registers may be viewed as a 512 (e.g. 64 .times. 8) bit shift register. Both groups of shift registers are interconnected with storage register input-output (I/0) circuit 42. The first bit clocked out of a storage register 39 is the least significant bit of digit Do.

The operational registers 38 are similarly 64 bit registers, the 38a portion having 60 bits of capacity and the 38b portions having four bits of capacity. The operational registers 38, including the point of junction between 38a and 38b portions, are interconnected with a plurality of register selector gates 43 which control the exchange of data between the operational registers and with arithmetic unit 40. As will be subsequently discussed in greater detail, the separation of operational registers A-D 38 into the aforementioned 60 bit and four bit portions and the connection therebetween with register selector gates 43, facilitates right or left shifting of data, because then it is desirable for the register selector gates 43 to be able to selectively pick off the data word starting with the D15 digit, which is stored in portion 38b or the Do digit, which is stored in portion 38a at the beginning of an instruction cycle (state S0) for instance. Storage register I/0 circuit 42 is interconnected with register A to permit movement of a data word between a selected storage register 39 and operational register A.

A data word may be either outputted from Register A 38 and stored in a selected storage register and stored in Register A. To effect such movement of a data word between Register A and a selected storage register 39, an appropriate instruction word from ROM 30 is received by instruction word decoder logic 31 indicating (1) from which group, X or Y, the particular storage register 39 is to be selected and (2) whether the data word is being moved from Register A to a storage register or from a storage register to Register A. The contents of an address register, register address buffer (RAB) 44, indicates which one of the eight storage registers in the addressed group is being selected.

RAB 44 is a three bit address register which can be loaded either from R5 register (three least significant bits) or from three selected bits of an instruction word as directed by appropriate instruction commands. The data words stored in the eight storage registers 39 in each group normally recirculate, with each 64 bit data word moving to an adjacent storage register location during each instruction cycle. Thus, during one instruction cycle the contents of X.sub.0 shifts to X.sub.1 while the contents of X.sub.1 shifts to X.sub.2 and so forth. This shifting, of course, is responsive to the outputs from clock 45. Storage register I/0 circuit 42 further includes a three bit counter which is likewise responsive to clock generator 45 for indicating which one of the eight data words stored in the addressed group is ready to be read out of X.sub.7 or Y.sub.7. Thus the three bit counter implemented in storage register I/o circuit 42 increments by one each instruction cycle. When a data word is to be read from or into a selected storage register 39, RAB 44 is first loaded with a three bit binary number indicating which one of the eight data word locations in a group is to be addressed. Then an instruction word is decoded by instruction word decoder logic 31 commanding storage register I/0 circuit 42 to select the proper group, X or Y, and to count instruction cycles until the counter contained therein matches the state of RAB 44. Thus it can be seen that it could require up to seven instruction cycles for the selected data word in one of the groups, X or Y, to be shifted into a position preparatory to reading out of or into that group. Thus storage register I/0 circuit 42 generates the HOLD command which inhibits incrementing program counter 32 until the counter in storage register I/0 circuit 42 matches the state of RAB 44 and the desired data is moved between the appropriate group and Register A.

Arithmetic unit 40 is a serially organized arithmetic unit which includes a binary coded decimal (BCD) corrector. The BCD corrector may be disabled by an appropriate instruction command thereby permitting arithmetic unit 40 to operate either in hexadecimal base or in binary coded decimal base, as desired. As aforementioned, the data format preferably includes 12 flag bits. These flag bits are used, for instance, during many problems for keeping tract of the results of certain logical operations. Including the flag bits in the data words stored in the operational registers 38A and 38B and in the storage registers 39 is an important feature of this invention which permits greater programming flexibility in implementing the instruction words into ROM 30 and further simplifies chip 10 in that it eliminates the need for the discrete or dedicated flag registers or latches used in the prior art, and permits the flags to be processed in arithmetic unit 40 rather than in separate flag logic circuitry as done in the prior art. Arithmetic unit 40 is responsive to selected flag bits and selected instruction commands (Table I, Section 7) for setting the condition latch 41. Thus, in accordance with selected instruction words (Table I, Section 7), the 12 flags may be individually set, reset, toggled, or tested. Further, the three MSD's used for flags may be arithmetically operated upon in hexadecimal using appropriate instruction words (see Table I) with appropriate flag masks (see FIG. 6).

The "set flag" instruction (see Table I, Section 7) loads a binary one into the addressed flag bit, while the "reset flag" instruction loads a zero; and "toggle" changes a zero flag to one or a one flag to a zero. The "flag test" instruction causes the condition latch (COND) to be set only if the tested flag has been previously set, e.g., contains a binary one. Thus the flag bits can be advantageously used to determine whether or not a conditional branch instruction will cause a branch to occur.

Register A and Register B are outputted to display decoder 46 in response to a display instruction command. The contents of Register A contains the digits to be displayed by the display 11 (FIG. 2) and Register B is loaded with bits which indicate the position of the decimal point and whether or not a particular digit is to be blanked. By using Register B to store digit blanking and non-blanking codes along with a decimal point and negative sign codes, which codes are loaded into Register B in accordance with instruction words contained in ROM 30, is another important feature of this invention eliminating the need for using discrete leading zero blanking circuitry, as used in the prior art. The display decoder 46 is connected to output register 47 which provides the digit scan lines to the display 11 via lines 15. The scan generator 36, display decoder 46 and output register 47 cooperate to drive the display 11 (FIG. 2) using the segment scan display technique disclosed by U.S. Pat. application Ser. No. 565,489 filed Apr. 7, 1975, now Pat. No. 4,014,012, and assigned to the assignee of this invention.

Referring now to FIGS. 4a and 4b, there is shown, in representative form, the timing signal generated by the clock generators 45 implemented on chip 10. The clock generators 45 may be of conventional design, and are not shown in detail herein. The clock generators sequentially generate .phi.1, P1, .phi.1 and P2 clock pulses, each pulse having a pulse width time of approximately 0.625 microsecond in this embodiment. The precise frequency of the clock generator is typically "fine tuned" using an external resistor 13 (FIG. 2). A full sequence of the four above-identified clock pulses comprise one state time (S0, S1, S2, etc.), each state time having a duration of approximately 2.5 microseconds in this embodiment. One state time represents the time needed for two bits of a data word to be clocked out of a register. Thus, it requires two state times for a four bit hexadecimal or BCD numeral to be inputted into the arithmetic unit 40 from an operational register 28. Since 16 digits in all comprise one data word (as is shown in FIG. 6), 32 state times (So-S31) are required to output all 16 l digits from a register. Thus, 32 state times (So-S31) represent one instruction cycle, as is depicted in FIG. 4b, and an instruction cycle has a duration of approximately 80 microseconds in this embodiment. The state times are generated by state time generator 48.

As will subsequently be discussed, the clock is responsive to a decoded display instruction for slowing the speed of the clock during display operations. During display operation, the period of a state time is 10 microseconds and the period of an instruction cycle is 320 microseconds.

In addition, clock pulses may be provided at every P.sub.1 and P.sub.2 time which are simply labeled P and other clock pulses are provided at every .phi.1 and .phi.2 time, which are simply labled .phi., as is shown in FIG. 4a. Further, clock pulses are provided at selected P or .phi. times in selected state times (for instance S1..phi.2), as is also eximplified in FIG. 4a.

Referring now to FIGS. 5a and 5b, there is shown diagramatically in FIG. 5a the 10 decimal digits, 0-9, displayable by a seven segment character display along with an eighth segment used as a decimal point. With respect to FIG. 5b, the seven character segments are labeled segments A-G and the decimal point segment is labeled P. For each character position there is a common cathode 9 provided for the eight segments, as is shown in FIG. 5b. The eight segments A-G and P for each character position are respectively connected in common by segment conductors S.sub.A -S.sub.G and S.sub.P. Chip 10 uses segment scanning according to the method disclosed by U.S. Pat. No. 4,014,012, which issued Mar. 22, 1977 wherein the segments are scanned sequentially and the digit cathods are selectively energized in conjunction with the scanning of the segment electrodes to form the characters 0-9 and a decimal point. By using the segment scanning method of U.S. Pat. No. 4,014,012, the segment amplifiers generally used heretofore in the prior art are eliminated. Thus, chip 10 may be directly interconnected with display 11.

Referring again to FIG. 3, scan generator counter 36 sequentially energizes the S.sub.A -S.sub.G and S.sub.P conductors (FIG. 5b) via lines 14 and pins SEG A-SEG G and SEG P (FIG. 11). Output register 47 is loaded each time a different segment is scanned with a twelve bit binary code indicating whether the cathodes 9 (FIG. 5b), associated with each of the 12 character positions, should be energized via lines 15 and pins D1-D12 (FIG. 11) permitting the scanned segment in the corresponding character positions to actuate.

Referring again to FIG. 6a, there is shown the format of the data word stored in operational registers 38A and 38B and storage registers 39 (FIG. 3). As aforementioned, each data word comprises 16 digits of serial data, each digit comprising four serial bits. Thus, an entire data word comprises 64 (e.g., 16 .times. 4) bits. The three most significant digits of the data word preferably comprise the 12 flag bits and the 13 remaining digits comprise numerica data, the first 11 digits thereof preferably being the mantissa and the least significant two digits being the exponent.

As aforementioned, associating the 12 flag bits with the 13 digits of numberic data in one data word storage location is an important feature of this invention which eliminates the need for separate flag registers.

In FIG. 6b there is shown the mask codes which are incorporated in many of the instruction words implemented in ROM 30; the set of instruction words storable in ROM 30 and decodable by instruction word decoder logic 31 (FIG. 3) are described in TABLE I. The set of instruction words stored in ROM 30 in this embodiment are listed in TABLE IV. As can be seen from TABLE I, a mask field code (MF) is used in many of the possible instruction words. The mask field denotes to the register selector gates 43 (FIG. 3) which digits of the sixteen digits data words are to be passed to the arithmetic unit 40 (FIG. 3) and which digits are to be recirculated. The mask codes are needed, because it is often desirable to perform some arithmetic or flag logic operation on only the mantissa or only the exponent or both the mantissa and the exponent or on a particular flag bit or perhaps the whole data word. As can be seen from FIG. 6b, there are 12 masks, having codes 0000 through 1011, which are listed and are associated with a rectangle beneath a representation of a 16-digit data word. The digits enclosed by the rectangle associated with a particular mask are permitted (by the mask decoder logic 200 (FIG. 8) in instruction word decoder logic 31 when the associated mask code is received) to pass through arithmetic unit 40 while those digits outside the rectangle are recirculated via gates 316a-d (FIG. 9). As will be seen with respect to the detailed discussion of the mask logic (FIG. 8), the mask codes cause the register selector gates 43 (FIGS. 3 and 9) to operate in timed relation with the data being outputted from an operational register 38 in accordance with the state times indicated by state time generator 48 (FIG. 3). The masks of FIG. 6b operate on complete digits, but certain individual bits may be selected by further mask arrangements as will be explained henceforth.

Referring now to FIG. 12, TABLE I, there are shown the set of possible instruction words stored in ROM 30, decoded by instruction word decoder logic 31 and utilized by the remainder of the system. TABLE I refers to FIG. 12 for drawings representative of the various types of instructions. As can be seen, the instruction word comprises 13 binary bits (I.sub.12 --I.sub.o). A 13 bit instruction word length provides for the possibility of having up to 2.sup.13 or approximately 8,000 different instruction codes; however, it will soon be evident that not all these possible instructions are used. Looking first to the first two instructions, namely the "branch on condition" and the "branch unconditionally" instructions, it will be seen that there is a one in the I.sub.12 position. Since all remaining instructions use a zero in the I.sub.12 position, it will be seen that there are approximately 4,000 variations of the first two instructions. The "branch unconditionally" instruction has a zero in the I.sub.11 position following the one in the I.sub.12 position and an address in the I.sub.10 -I.sub.10 positions. Since the "branch unconditionally" address contains 11 bits and since the program counter 32a contains 11 bits, the "branch unconditionally" instruction can cause the branch anywhere within ROM 30, including branches between ROM A and ROM B. The "branch on condition" instruction, on the other hand, contains only a 10 bit address because the I.sub.10 bit is used as a condition bit. If the state of the condition bit (I.sub.10) matches the state of the condition latch, the branch will occur; if there is no match, the branch instruction is ignored. There being only 10 bits in the address for the "branch on condition" instruction, when the branch is executed only the 10 least significant bits are loaded into the 11 bit address register of program counter 32a. The most significant bit in the program counter remains unchanged. Since a zero in the most significant bit (A.sub.10) in the program counter addresses only those instruction words in the part of ROM 30 denoted as ROM A, and a one in the most significant bit (A.sub.10) in the program counter addresses only those instruction words located in that portion of ROM 30 denoted as ROM B, the "branch on condition" instruction only permits branching within the confines of either ROM A or ROM B. The unconditional branch instruction may be also considered a "CALL" instruction inasmuch as an incremented address (the location following the location of the unconditional branch instruction) is stored in the subroutine stock 33 if the branch is accomplished.

The next listed instruction words in TABLE I, namely "Branch to R5" and "Return" will be discussed subsequently.

Referring to part five of TABLE I, the operations under mask control contain a zero in the I.sub.12 position, the mask field code in the I.sub.11 -I.sub.8 positions, and an operational code in the I.sub.7 -I.sub.0 positions. The operational code is divided into two bits J, three bit K, two bit L, and one bit N fields, as shown in TABLE I. For certain special operations the L and N fields are combined into one three bit field (LN field). TABLE I explains in detail the operations performed in response to particular binary codes entered into the aforementioned J, K, L, and N fields.

Remembering that the mask field, i.e., I.sub.II -I.sub.8 has only 12 possible mask codes (0111-1010, and 1101 and 111 ), while a four bit binary number has 16 possible codes associated therewith, then there are four codes which may be loaded into the mask field position, namely 0110, 1011, 1100 and 1110 , which will not be decoded as a mask operation. Two of these four codes, 1110 and 1100, are decoded by instruction word decoder logic 31. The 1110 code is referred to as the miscellaneous non-mask code; the family of instruction words using the miscellaneous non-mask code are explained in Part six of TABLE I. The miscellaneous non-mask operations have a four bit Q and four bit P fields in addition to the zero and the I.sub.12 position and the 1110 in the I.sub.11 -I.sub.8 positions. In this instruction set, the Q field is ignored by decoder logic 31 unless specifically referred to in this instruction set; the P field is decoded to perform the operations indicated, which are generally operations not making use of the arithmetic unit 40. Thus, there operations relate to transforming data between the storage registers and the operational registers, storing three bit codes in RAB 44 (FIG. 3), storing the contents of R5 register 34 (FIG. 3) in the program counter 32a, or enabling or disabling the BCD corrector in arithmetic unit 40.

The "Return" instruction (Section 4 of TABLE I) and "Branch to R5" location (Section 3 of TABLE I) may be considered as part of the miscellaneous non-mask code since these two instructions also have a 1110 in their I.sub.11 -I.sub.8 positions. The Return instruction causes a branch to the address most recently stored in subroutine stack 33.

Other non-mask operations include the flag operations which are defined by a 1100 in the mask field MF. The flag operations are explained in detail in Part seven of TABLE I. Although generally referred to as a non-mask operation, the flag operations may be thought of as very detailed mask operation in the calculator disclosed, because a specific flag bit in a data word is examined or operated upon rather than merely operating on a particular one or set of digits using the normal mask codes defined in FIG. 6. Flag operations have not heretofore been thought of as being similar to mask operations, since the flags have been typically stored in special registers of latches separate from the numeric data.

The various parts of the system of FIG. 3 will now be described with reference to FIGS. 7, 8, 9, 10, 11 and 13 which depict in detail in logic circuit implemented on chip 10 to form the circuits depicted by the block diagrams of FIG. 3. The following discussion with reference to FIGS. 7-11 will refer to the logic signals available at many points on chip 10. It should be remembered that a logical zero corresponds to a negative voltage, that is, V.sub.dd, while a logical one refers to a zero voltage, that is, V.sub.ss . It should further be remembered that the P-channel MOS transistors depicted in FIGS. 7-11 become conductive when a logical zero, i.e., a negative voltage, is applied at their respective gates. When a logic signal is referred to which is unbarred, i.e., has no bar across the top of it, the logic signal is to be interpreted as "true" logic; that is, a binary one indicates the presence of the signal (Vss) whereas the binary zero indicates a lack of the signal (Vdd). Logic signal names including a bar across the top thereof are in "false" logic; that is, a binary 0 (Vdd voltage) indicates the presence of the signal whereas a binary 1 (Vss voltage) indicates that the signal is not present. FIGS. 7-11 do not depict the clock generators implemented on chip 10, the clocks generating clock pulses .phi..sub.1, P.sub.1, .phi..sub.2, P.sub.2, in accordance with the clocking signals depicted in FIG. 4a. The clock generators are of conventional design and are responsive to decoded display instruction command signal for decreasing the frequency of the clock, as aforementioned.

THE ROM AND PROGRAM COUNTER

Referring now to FIG. 7, there is shown the logic diagram of the program counter 32a, the branch logic 32b, subroutine stack 33, condition latch 41, test logic, and ROM 30 along the interconnecting circuitry. The details of ROM 30 are not shown in detail in FIG. 7, however, ROM 30 is of the virtual ground type disclosed in U.S. Pat. No. 3,934,233 by Roger J. Fisher granted Jan. 20, 1976. Using the virtual ground read-only-memory of U.S. Pat. No. 3,934,233 permits the size of the ROM to be significantly reduced in comparison with the ROM's typically used in the prior art by using one ground or V.sub.ss line for five or more P defusions. Lines A.sub.0 -A.sub.10 supply, in parallel, at time S22..phi.1, the 11 bits address for addressing ROM 30. Address lines A.sub.0 -A.sub.6 address the X address decoder disclosed in U.S. Pat. No. 3,934,233 while address lines A.sub.7 -A.sub.10 address the Y address decoder of U.S. Pat. No. 3,934,233. Lines L.sub.12 - I.sub.0 provide, in parallel, the instruction word corresponding to the address appearing on address line A.sub.0 -A.sub.10. The false logic instruction word is clocked out of ROM 30 at S29..phi.2 by gates 111 and inverted to true logic by inverters 110. Address lines A.sub.10 -A.sub.0 are loaded from program counter 32a at S22..phi.1 by gates 112, unless the power up clear latch 162 has inserted a logical one into complex gate 113, which in turn inhibits conduction by gates 112. The power up clear latch 162 is preferably incorporated in clock 45 and comprises a latch which preferentically enters a first state for generating the logical one to complex gate 113 when power is initially applied to the system. The state of the latch changes when the clocks turn on sufficiently to change a capacitor associated with the reset input to the latch.

Gates 114 unconditionally precharge address lines A.sub.0 -A.sub.10 to Vdd at S21..phi.2 of each instruction cycle and when power up-clear logic finally inserts a zero into complex gate 113, the address previously received by ROM 30 is 00000000000.sub.2. Thus, power up-clear logic effectively forces the ROM to branch to the very first location contained therein. This automatic branch to 000.sub.16 using the ROM precharge gates 114 in combination with gates 113 is an important feature of this invention which permits the operational registers 38 and storage registor 39 along with the remaining logic circuitry to be prepared for numeric operations in accordance with instruction words loaded into ROM 30 beginning at location 000.sub.16 rather than using dedicated circuitry therefore or requiring an address to be jammed into program counter 32a after the state of the PUC signal changes.

Program counter 32a comprises an 11 bit shift register, having 22 inverter stages 115 and gates 116 for precharging the stages, for forming an address register. A serial input to program counter 32a is received on line 117 and a serial output is communicated via line 118 to add-one circuit 119. Gates 143 interconnect the 11 stages of program counter 32a in series. Add-one circuit 119 is a simplified serial add-one circuit comprising a NAND gate 119a, one input of which is connected to line 118 and an output of which is connected to inverter 119b. The output from inverter 119b is communicated to another input of NAND gate 119a, to the gate electrode of transistor 119c and the source electrode of transistor 119d. Line 118 is further connected to the source electrode of transistor 119c and the gate electrode of transistor 119d. The drain electrodes of transistors 119c and 119d are connected together and normally provide the previous 11 bit program counter address incremented by the number one on line 120. The junction between the output of NAND gate 119a and the input of inverter 119b is further interconnected with the HOLD signal generated by gate 500 (FIG. 11) and gate 291 (FIG. 8) to inhibit incrementing the previous program counter address by add-one circuit 119.

The output from add-one circuit 119 normally recirculates via line 120 and gate 121 back to the input of program counter 32a on line 117. Gate 121 is responsive to the output from NAND gate 130 and is normally conductive except when inhibited by a RETURN or KB BRANCH (Branch to R5) commands. Program counter 32a may also be loaded with either 10 or 11 bits of the instruction word appearing at gates 110 via lines 122 and gates 123 and 124. When a conditional branch instruction word is decoded and branch logic 32b determines that the condition has been satisfied, the new branch address is loaded from the I.sub.0 - I.sub.9 bits of the instruction word into the A.sub.0 -A.sub.9 bits of program counter 32a via lines 122 and gates 123. When an unconditional branch instruction word (CALL) is decoded, gate 124 is caused to conduct at the same time as gates 123, thereby inserting 11 bits from the instruction word (I.sub.0 - I.sub.10) into program counter 32a. The 10 or 11 bits from the instruction word are loaded into program counter 32a after the prior ROM address plus one has recirculated serially via lines 117, 120 and gate 121.

THE SUBROUTINE STACK

The subroutine stack 33 is a three-level stack of 11 bit shift registers 33a, 33b, and 33c, each comrpsied of 22 inverter stages 125. Except when subroutine stack 33 is either outputting a return address to program counter 32a or receiving an address from program counter 32a, the 11 bit addresses stored therein are recirculated via gates 126. Gates 126 normally receive a logical zero (i.e., are made conductive) from NAND gate 137, which provides a logical one output only upon receiving either a RETURN signal from NAND gate 135 or a CALL signal from NAND gate 136.

When an unconditional branch instruction is decoded by branch logic 32b, the CALL signal goes to zero permitting the present ROM address plus one to be loaded into subroutine stack register 33a via line 120 and gate 127 from add-one circuit 119. Addresses previously loaded into subroutine stack/registers 33a and 33b are shifted to registers 33b and 33c, respectively, by gates 128. Gates 127 and 128 are responsive to the CALL signal. If an address had previously been loaded into subroutine stack register 33c, it would have been lost upon the execution of another unconditional branch instruction.

Upon the decoding of a "Return" (RTN) instruction by decoder 214 (FIG. 8), the RETURN signal from NAND gate 135 goes to logical zero, thereby causing the output of NAND gate 130 to become a logical one, interrupting the normal insertion of an up-dated address via line 120 when gate 121 becomes nonconductive and forcing the contents of subroutine stack register 33a to be inserted into program counter 32a via gate 129 and line 117. Gates 131 cause the contents of subroutine stack register 33b to be inserted into register 33a and the contents of register 33c to be inserted into register 33b upon the execution of a return instruction. Gates 131 are responsive to the RETURN signal from NAND gate 135.

THE BRANCH LOGIC AND CONDITION LATCH

Branch logic 32b and condition latch 41 cooperate to control gates 123 and 124 in program counter 32a for inserting the address portion of a branch instruction word into program counter 32a. NAND gates 132 form the latch circuit of the condition latch 41 and are responsive to an ADDER COND SET signal from gate 401 (FIG. 10) and a LOAD R5 signal from decoder 508c (FIG. 11) for letting the latch. The latch is reset by either a Return or by such instruction, as is explained subsequently. Complex gates 133 are responsive to COND and COND signals produced by NAND gates 132, a PREG signal from NAND gate 146 and the I.sub.10, I.sub.10, I.sub.11 and I.sub.12 bits which are derived from ROM 30, the I.sub.10 bit via inverter 134. OR gates 133a and 133b both provide a logical one output only when the state of the condition bit matches the state of the I.sub.10 bit. Thus, the output from OR gates 133a and 133b along the I.sub.12 and I.sub.11 bits and the PREG signals are supplied to AND gate 133c which provides a logical one output only when (1) I.sub.11 and I.sub.12 indicates that a conditional branch instruction has been outputted from ROM 30, (2) the state of the I.sub.10 bit and COND match and (3) PREG is a logical one indicating that the PREG test circuitry is not activated. The test circuitry and the PREG and TIRG signals associated therewith are described subsequently.

NAND gate 136 is responsive to the I.sub.12 and the I.sub.11 bits and to PREG thereby providing a CALL signal to NAND gates 137 and 138 and to gates 127 and 128 unless the test circuitry has been activated. NAND gate 135 is responsive to the RTN signal from decoder 214a (FIG. 8) via inverter 159 and to the PREG signal for generating the RETURN signal which is a logical zero if (1) a "return" instruction has been decoded and (2) the PREG test circuitry has not been activated.

NAND gate 138 is responsive to CALL from NAND gate 136 and to TIRG for generating a CALL signal which is normally a logical zero unless (1) an unconditional branch (call) instruction has been decoded or (2) the test circuitry has been activated. NAND gate 139a, which normally receives an S20.P1 clock signal via gate 149 in addition to the CALL signal from NAND gate 138, provides a CALL signal at S20.P1 to complex gates 139b. NAND gate 139a is responsive to an S30.P1 clock signal in gate 150 in lieu of the S20.P1 signal if the test circuitry is activated. Complex gates 139b output the CALL signal at S21..phi.1 to gate 124, unless the test circuitry is activated, in which case the CALL signal is supplied to gate 124 at S31..phi.1. OR gate 133d is responsive to the output from AND gate 133c and to CALL from NAND gate 138, thereby producing a logical one output upon the occurrence of either: (1) a condition/I.sub.10 match on a conditional branch instruction, or (2) the CALL signal (on an unconditional branch instruction or PREG test mode operation). The output of OR gate 133d is supplied to NAND gate 133e along with a normal S20.P1 signal from gate 149 (or S30.P1 during TIRG test operation). NAND gate 133e, in conjunction with gates 140, provide a BRANCH signal at S21..phi.1 (S30.P1 in test mode) to gates 123 for inserting the I.sub.0 -I.sub.9 bits of the instruction word into program counter 32a.

Inverter 142 outputs a RETURN signal from the RTN signal received from decoder 214a (FIG. 8). Gates 141 are responsive to the I.sub.12 branch bit, the RETURN signal from inverter 142 and the S20..phi.1 signal from resetting the condition latch 141 upon the occurrence of either (1) a branch instruction (e.g., I.sub.12 = 1) or (2) upon a "return" instruction.

Considering now the timing of the addressing operations of program counter 32a during normal operations, the address stored in program counter 32a is incremented in add-one circuit 119. The incremented address is circulated back into the program counter 32a during S2-S12..phi.1 when gates 143 in program counter 32a are clocked. Thus, the incremented address in program counter 32a is updated by state time S12 of an instruction cycle and will normally be clocked into ROM 30 at the following S22..phi.1 by gates 112 for reading out the next instruction word. If a conditional BRANCH (and the condition is satisfied) operation is indicated by the present instruction word read from ROM 30 (at the previous S29..phi.2), the present address in program counter 32a is still incremented by add-one circuit 119 during S2-S12, but the address portion of the BRANCH instruction word is jammed into program counter 32a by the action gates 123 and 124 at S21..phi.1, thereby inserting a new address one state time before the new address is to be clocked at S22..phi.1 into ROM 30. This one state time is sufficient to precharge and conditionally discharge the inverters 115 making up the stages of program counter 32a. During a CALL operation, the incremented address is stored in the subroutine register 33a, and a new address from the I.sub.0 -I.sub.10 bit of the CALL instruction word is clocked into program register 32a, a manner similar to the inputting of a BRANCH address.

THE TEST CIRCUITRY

NAND gate 146 is responsive to TEST and K1 signals which are clocked on S31..phi.1 to provide at its output PREG. NAND gate 147 is likewise responsive to TEST and K1 but is clocked at S0..phi.1 to provide TRIG which is inverted to TRIG by inverter 148. PREG is generated when a ROM address is desired to be inputted directly to program counter 32a via keyboard line K1 for test purposes. TIRG is also generated if the instruction word at the aforementioned address is desired to be serially readout of the chip on line K2 during test operations. The output from inverter 148 is supplied to gate 149 which supplies the S20.P1 clock signal to NAND gates 133e and 139a, the S20.P1 clock signal being the clock signal used during non-TIRG test operations. The TIRG signal, besides being applied as an input to NAND gate 138 is also supplied to gate 150 for supplying the S30.P1 clock signal to NAND gates 139a and 133e, the S30.P1 clock signal being provided during TIRG test operations. PREG is inverted by inverter 151 whose output is connected to gate 145, which is in line 117. Gate 145 is conductive, except during test mode operations, normally permitting the incremented address to recirculate on line 117. Thus, gate 145 inhibits the incremented address outputted from add-one circuit 119 from being inserted into program counter 32a during test mode operations. Instead, the address to be inserted on line 117 during test mode operations is received from keyboard line K1 (FIG. 11) via gate 152 which is responsive to PREG. The output from program counter 32a is supplied to keyboard line K2 (FIG. 11) via line 118, inverter 153 and gates 601 and 602 (FIG. 13). K2 receives, as it will be subsequently shown, the I.sub.0 -I.sub.10 bits of the instruction word addressed in ROM 30 during state times S2- S12 of TRIG test mode operations. Accordingly, the output from program counter 32a on line 118 is clocked at S2-S12 to inverter 153 via gate 154. The I.sub.11 and I.sub.12 bits of the instruction word are also outputted to K2, these bits being outputted during S13 and S14 via gates 155 and 156, respectively, which provide the I.sub.11 and I.sub.12 bits to the input of inverter 153.

As will be shown, the aforementioned PREG and TIRG test circuitry permits the instruction words implemented ROM 30 to be read out of the chip on line K2 according to addresses inserted into the chip via line K1 when the calculator has been put into a test mode via input signals which are discussed with reference to FIG. 13. Once in the PREG test mode, an address may be inserted into program counter 32a from K1 via gate 152. This insertion would be timed to be inserted into program counter 32a in the same manner as an updated address from add-one circuit 119. Any branching which might occur at the same time a PREG test operation address is inserted into program counter 32a (according to the previously addressed instruction word) is inhibited by the PREG inputs to AND gate 133c and NAND gate 136. Thus, as the old address is shifting out of the program counter 32a on line 118, an externally supplied address is being inputted from K1 via gate and 152 and line 117 during the same instruction cycle. The incremented address is blocked by the action gate 145. This externally supplied address is then used to address ROM 30 at the following S22..phi.1.

If the chip is also placed into the TIRG test mode (in addition to PREG), the I.sub.0 -I.sub.10 bits of the instruction word are clocked into program counter 32a via gates 124 and 123 at S31..phi.1, it being remembered that the CALL S21.phi.1 and BRANCH S21..phi.1 signals are automatically activated at S31.phi.1 during TIRG test mode operations. The I.sub.0 -I.sub.10 bits instruction word are then shifted out of program counter 32a at (S2-S12), .phi.1 via line 118, gate 154 and inverter 152. At the same time a new address is inputted from K1 via gate 152. Thus, during each instruction cycle, an external source may be used to address ROM 30 and the code contained in ROM 30 at that address is read out via K2, the I.sub.0 -I.sub.10 bits being provided by program counter 32a and the I.sub.11 and I.sub.12 bits being provided by gates 155 and 156. It should be evident that the entire contents of the ROM 30 may be checked in approximately 2,000 instruction cycles whereas if the contents of ROM 30 were to be checked by requiring the calculator to perform all possible instructions, it should be evident that that technique would require significantly more than 2,000 instruction cycles.

Additionally, the state of the condition latch 41 is outputted as COND to keyboard line K3 (FIG. 11) via an inverter 160, responsive to latch 41, and gates 605-608 (FIG. 13). Similarly, HOLD is outputted to keyboard line K3 during test mode operations via gates 605, 607 and 608 (FIG. 13).

Referring now to FIG. 13, there is shown the test logic associated with keyboard lines K1-K4. The K1-K4 pins depicted in FIG. 13 are the same pins as the K1-K4 pins depicted in FIG. 11. The address received on line K1 is directly connected to the input to gate 152 (FIG. 7). The instruction word received from the ROM is outputted via gates 601 and 602 to pad K2. Gates 603 and 604, which are responsive to TEST AND TEST, respectively, isolate the instruction word output from line K2 except during test operations.

Pin K4 is responsive to a Vdd signal for producing the TEST signal. Pin K4 supplies one input to NOR gate 609. The other input to NOR gate 609 is derived from S28..phi.1. The output from NOR gate 609 is supplied through an inverter 610 and gate 611 to NAND gate 612. The other input of NAND 612 is responsive to the power up clear signal, PUC. The output of NAND gate 612 provides the TEST signal and via inverter 613 the TEST signal.

Pin K3 is responsive to the HOLD and COND signals produced by the calculator when in a test mode. Accordingly the HOLD and COND signals are provided via gates 605 and 606, respectively, clocked at state times S3 and S2, respectively, to a gate 604 which is responsive to TEST. The output from gate 607 drives a gate 608 for providing a signal to pin K3 during test operations indicative of HOLD and COND.

THE INSTRUCTION WORD DECODER LOGIC

The instruction word decoder logic 31 is shown in FIG. 8. Referring now to FIG. 8, a decoder 200, which decodes the mask portion of instruction field, receives from inverters 110 (FIG. 7) the mask field (MF) of the instruction word, i.e., bits I.sub.11 -I.sub.8, and their complements I.sub.11 -I.sub.8. Decoder 200 is also responsive to the B-E (and complements B-E) outputs from state time generator 68 (FIG. 11), which provides a binary representation of which one of the 32 state times this system is operating in. Since there are 16 digits in a data word and since the first digit, (DO) starts imputting at S.sub.0, then the second digit begins inputting at S.sub.2 and so on. Decoder 200 decodes the aforementioned bits to produce the masks MANT, LLSD, etc. (FIG. 6b). In addition, decoder 200 decodes the I.sub.12 bit, thereby disabling decoder 200 when I.sub.12 is a logical zero (I.sub.12 is a logical one then), when a conditional or unconditional branch instruction has been outputted from ROM 30 (FIG. 7). Decoder 200 decodes the twelve mask codes which are explained with reference to FIG. 6. Remembering that a mask code indicates which bits of a data word are to be operated on by arithmetic unit 40 and which are to be merely recirculated by register selector gates 43, it is desirable that when a particular mask field has been decoded by decoder 200 that a mask signal be generated during the state times at which the particular digit of a word is to be operated on by arithmetic unit 40 in accordance with the mask codes defined in FIG. 6. Therefore, decoder 200 is responsive not only to the MF field (bits I.sub.11 -I.sub.8 of the instruction word), but also to the binary representation of which one of the 32 state times the system is operating in. Since the digits are outputted only at even state times, as aforementioned, decoder 200 need not be responsive to the least significant bit from state time generator 48 on line A or A.

Decoder 201, which is associated with decoder 200, is responsive to the I.sub.11 -I.sub.8 bits of the instruction word and their complements, I.sub.11 -I.sub.8 and in addition the I.sub.12 bit to disable the decoder 201 when a conditional or unconditional branch instruction has been outputted from ROM 30 (FIG. 7). Decoder 201 decodes the miscellaneous (MISC) and flag operation (FLGOP) codes which also occupy the MF field, as is explained with reference to TABLE I, Sections 6 and 7. As will be seen, the outputs from decoder 201, MISC (via inverter 203) and FLGOP (as well as FLGOP via inverter 211), are applied as inputs into several other decoders for disabling or enabling signals during miscellaneous or flag operations.

Decoder 210 receives bits I.sub.0 -I.sub.3 and their complements I.sub.0 -I.sub.3 of the instruction word and it is enabled only during miscellaneous operations by MISC which is derived from decoder 201 via inverter 203. Decoder 210 decodes the stack instructions (STAY, STAX, STYA, AND STXA) and the address buffer instruction (NAB and RAB), which are explained in TABLE I, Section 6.

Decoders 204 and 205 decode the bit and digit defining bits, respectively, for the flag instructions (see TABLE I, Section 7, B and D fields). Decoder 204 is responsive to the A and A state time from state time generator 48 (FIG. 11), .phi.1 and .phi.2 clock pulses (which are applied to separate loads 204a and 204b associated with decoder 204) and the flag bit defining bits I.sub.2 -I.sub.3 of the B field of the flag instruction (see TABLE I, Section 7). The I.sub.2 -I.sub.3 bits define which bit of four in a digit is selected and decoder 204 provides enabling signal when there is a match between (1) the bit selected and (2) the time at which that bit enters arithmetic unit 40 as denied by the P1 and P2 clocks and by whether the state time is odd or even as defined by state time A. Decoder 205 decodes the digit selected (as defined by bits I.sub.4 -I.sub.5 of the flag instruction, see TABLE I, Section 7) and is responsive to the B-E and B-E outputs from state time generator 48 (FIG. 11) for generating an enabling signal when there is a match between (1) the digit selected and (2) the time at which that digit enters arithmetic unit 40. The output from decoder 204 is nanded in decoder 216 onto line 213 and the output from decoder 205 is nanded in decoder 216 onto line 217. Lines 213 and 217 are applied to NAND gate 207 whose output is connected to input of NOR gate 212. The other input of NOR gate 212 is FLGOP from decoder 201 and thus NOR gate 212 provides a logical one output upon the decoding of flag operation instruction during the time that the bit selected in decoder 204 within the digit selected in decoder 205 is outputted from the operational registers 38 into arithmetic unit 40. The output from the mask field decoder 200 is applied to decoder 202 for performing a NAND operation thereby providing an output on line 218 of a logical zero except when (1) a mask operation has been decoded and (2) the state time counter 48 indicates that the selected bits are to be inputted to arithmetic unit 40. The outputs of NOR gates 212 and 218 are applied to the inputs of NOR gate 219 which outputs a logical one except during either (1) arithmetic mask operations decoded by decoder 200, or (2) flag bit mask operations decoded by decoders 204 and 205. It should be appreciated that the arithmetic masks and flag masks are generated slightly ahead of the time the selected digit or bit is outputted from an operational register to provide sufficient time for the MOS gates to be actuated. The output from NOR gate 219 is outputted through a series of gates 220 providing a signal MSK .phi. which is outputted to the arithmetic unit one .phi. time before the corresponding data is inputted to the adder. The output from NOR gate 219 is also inverted by an inverter 222 to provide a MASK .phi. signal to mask delay generator 225, NAND gate 230, and gate 223, inverter 250 and gate 251.

A mask delay generator 225, whose function is more fully described with respect to the operational register selector gates 43, comprises a series of clocked inverters for providing a delayed mask signal in both true and false logic, the MD .phi./P signal being two state times behind the MASK .phi. signal provided by inverter 222. The MD.phi. signal is one .phi. time earlier than the normal MD .phi./P signal and an MDP signal is provided which provides a P clock during the occurrence of an MD.phi./P signal.

Decoder 215 is responsive to the FLGOP signal and the I.sub.0 -I.sub.5 bits (and their complements) of the instruction word for decoding the STORE signal (see TABLE I, Section 3, the LN field), the SHIFT signal, the IR5 signal and the 2R5 signal (see TABLE I, Section 5, K field). Decoder 206 is responsive to the MISC signal and the I.sub.0 -I.sub.2 bits instruction word for generating the BCDS and BCDR signals, which are indicative of whether the arithmetic unit is to BCD correct (see TABLE I, Section 6). These signals are applied to separate NAND gates 228 and 229 which are arranged as a latch. The output from this latch is the HEX signal which is indicative of whether the adder is to add in hexidecimal or is to BCD correct.

Decoder 208 is generally responsive to selected I.sub.0 -I.sub.4 bits of the instruction word and provides a T/T output and a K .fwdarw. Y output. The T/T signal is generated during flag operations when a flag is to be tested or toggled while the K .fwdarw. Y signal is generated during non flag operations when the number one is desired to be loaded into the least significant masked digit position in the Y input of arithmetic unit 40. The K .fwdarw. Y signal is inverted by inverter 252 and applied to one input of AND gate 251. AND gate 251 is also responsive to the MASK .phi. signal from inverter 222 and to a delayed MASK .phi. signal supplied by inverter 250. Thus, upon occurrence of a K .fwdarw. Y signal and a MASK .phi. signal, AND gate 251 is effective for inserting a one into the least significant bit of the least significant digit immediately following the beginning of the MASK .phi. signal. The T/T signal, as will subsequently be seen, is also used to insert a one into the appropriate bit position in the Y input to arithmetic unit 40; thus the T/T is inverted by inverter 224 and applied as an input to NOR gate 226. The other input to NOR gate 226 is from the output of AND gate 251. NOR gate 226 drives a series of gates 231 which are effective for inserting the aforementioned one into the appropriate bit position in the Y input to the arithmetic unit 40.

Decoder 209 decodes the BRK signal which causes a branch to occur in branch logic 32b, the branch location being defined by the contents of R5 register 34 (FIG. 10). Referring again to FIG. 7, the BKR signal is supplied as an input to NAND gate 130 interrupting the normal address recirculation path via lines 120 and 117 for the updated address. BKR also closes gate 157 for inserting the contents of R5 register 34 via inverter 158 onto line 117 for insertion into program counter 32a via gate 145. Returning to FIG. 8, NAND gate 209a generates the S/RS signal which is generated during flag operations for setting or resetting a flag and the DISP signal which is generated during display operations.

Decoder 214 is responsive to the I.sub.7 -I.sub.0 bits of the instruction word and to FLGOP, FLGOP, and MISC signals for generating the signals used to operate the various register selector gates and register recirculation gates. Decoder section 214a generates the RTN (return) signal which is supplied to inverter 142 and to NAND gate 135 (FIG. 7). Decoder section 214b generates AX-DX signals and section 214c generates AY-DY signals, which are inverted by inverters 221. AX-DX and AY-DY signals are supplied to NAND gates 231a-231d and 232a-232d, respectively, and are indicative of which ones of the operational registers A-D are to be interconnected with the X and Y inputs to the arithmetic unity using the register selector gates 43 (FIG. 9). NAND gates 231a-231d are also responsive to the GMASK signal on line 234 and to the STORE signal generated by decoder 215. NAND gates 232a-232d are also responsive to GMASK signal on line 296. The purpose of the STORE and GMASK signals, in respect to these aforementioned NAND gates, and the timing interactions of these gates with respect to movement data within the various operational registers, between the operational registers and with arithmetic unit via register selector gates 43 will be explained subsequently with reference to FIG. 9. The 214d portion of decoder 214 decodes the I.sub.0 -I.sub.2 bits of the instruction word, those bits corresponding to the L and LN fields in the instruction words control the operations under mask control (Table I, Section 5) for generating the EXCH, .SIGMA..fwdarw.K and .pi..fwdarw.J signals. The .SIGMA..fwdarw.J signal is indicative of a decoded instruction indicating that the results from the arithmetic unit 40 on line .SIGMA.' is to go to the register defined by the J field and similarly the .SIGMA..fwdarw.K signal indicates that the results from the arithmetic unit 40 on line .SIGMA.' is to go the register defined by the K field, or neither field, in which case a binary 10 occurs in the L field, which is simply not decoded by decoder 214 (See Table I, Section 5). Decoder 214e is responsive to the FLGOP and I.sub.1 and I.sub.0 bits of the instruction word for decoding the TGL (TOGGEL) signal which is used invert a selected flag bit.

The EXCH, .SIGMA..fwdarw.K, .SIGMA..fwdarw.J, TGL, STORE, and S/RS signals are supplied to a decoer 227 whose outputs are supplied to decoder 238 along with the AX-DX and AY-DY signals from inverters 221 and the SR' signal from NOR gate 237. The outputs from decoder 238 are applied as inputs to decoder 239 for decoding the recirculation signals RA, RB, RC, and RD and the adder output signals .SIGMA.A, 93 B, 93 C, and 93 D. The RB-4 RD recirculation signals are inverted to true logic by inverters 236. The RB-RD signals are supplied to NOR gates 235b-235d, respectively, along with a RECMASK signal from NAND gate 247 for producing RECB - RECD signals. The recirculation signal RA is supplied to an input of OR gate 244 along with the EXCH' signal derived from decoder 214 via NAND gate 240, which is also responsive to S1. The output of OR gate 244 supplied to a NAND gate 247 via an inverter 248. The output of NAND gate 245 is supplied to NAND gate 246 for producing a RECA signal. NAND gate 246 is also responsive to the LA (Load A) signal from inverter 249 indicating that the contents of one of the storage registers is to be outputted to operational register A.

The .SIGMA.A-.SIGMA.D outputs from decoder 239 are supplied to NAND gates 233a - 233d, respectively, for generating .SIGMA..fwdarw.A-.SIGMA..fwdarw.D signals which are used to control selector gates 43 for determining to which one of the operational registers A-D the result outputted on line .SIGMA.' from arithmetic unit 40 is to be communicated. NAND gates 233a - 233d are also responsive to the MD signal from the output of the mask delay generator on line 253.

The right shift (SR') signal is generated by a NOR gate 237 which is responsive to the SHIFT signal from decoder 215 and to the I.sub.0 bit from the decoded instruction word. The SR' signal, besides being supplied to decoder 238, is also communicated to a NAND gate 230 for supplying an SR signal to register selector gates 43. The SR signal supplied to the register selector gates is under mask control and therefore NAND gate 230 is also responsive to the MASK.phi. signal from the output of inverter 222. The SR' signal is further communicated to inputs or OR gate 253 via an inverter 254. OR gate 253 is responsive to AND gate 223. AND gate 223 is responsive to a logical zero signal supplied at S 31.phi.2, to a logical one signal supplied at A1.phi.2 and to OR gate 294. OR gate 294 is responsive to the output from NOR gate 212 and to the mask signal on line 218. NAND gate 247 is responsive to the output of OR gate 253 and to MD.phi./P via line 253 from the output of the mask delay generator 225 for producing the RECMASK signal, which is provided to inverter 248 and NOR gates 235b - 235d.

OR gate 243 is responsive to the MASK.phi. output of NOR gate 219 and to a SHIFT signal from decoder 214 via inverter 255. The output of OR gate 243 is supplied to AND gate 256 along with MD.phi. from mask delay generator 225. AND gate 257 is responsive to the output from NAND gate 241, to SHIFT from decoder 215 and to MASK.phi. from NOR gate 219. The outputs of AND gates 256 and 257 are supplied to NOR gate 259 which drives gate 295 for generating the GMASK signal on line 296 which supplied as an input to NAND gates 231a - 231d and 232a - 232d.

NAND gate 241 is responsive to the MD.phi./P signal on line 253 and to the EXCH signal from NAND gate 240. OR gate 242 is responsive to the SHIFT signal from decoder 215, the I.sub.0 bit of the instruction word and the MD.phi. signal from mask delay generator 225. The MD.phi. signal is generated one .phi. time before than the normal MD.phi./P signal by mask delay generator 225. The output from OR gate 242 and the output from NAND gate 241 are supplied to a NAND gate 260 for generating an SLRC' signal. The SLRC' signal is inverted by inverter 261 and is clocked through a series of gates 262 along with the SLRC' signal for generating the SLRC and SLRC signals on lines 263 and 264, respectively. The SLRC and SLRC signals cooperate with gates 321a - 321d and 320a - 320d, respectively, in the register selector gates 43 (FIG. 9) and with gates 230 and 336a-d to control right or normal shifting of data as is more fully described hereinafter.

The TGL and EXCH' signals from decoder 214d are supplied to a NAND gate 274 for supplying a TGEXCH signal on line 265 to arithmetic unit 40. The load A (LA) signal supplied to inverter 249 is generated as is now explained. AND gate 266 is responsive to the STXA and STYA signals from decoder 210. A NOR gate 267 is responsive to the output from AND gate 266 and to a COMPARE signal from comparison gates 238 for generating the LA signal.

A NAND gate 234 is responsive to the MD.phi./P signal on line 253 and to the EXCH' signal from inverter 240 for supplying an EXCH signal under mask control to the appropriate register selector gates 43 (FIG. 9). EXCH' from NAND gate 240 is also supplied via an inverter 268 to NAND gate 269. NAND gate 269 is also responsive to the flag set/reset signal S/RS from NAND gate 209a. NAND gate 269 controls a gate 270 which connects the output of the arithmetic unit 40 on line .SIGMA.' with the .SIGMA. bus which is interconnected with various register selector gates 43 (FIG. 9) and to the storage registers 39. The S/RS signal is also supplied to a series of gates 271 for inserting a set or reset flag bit (as defined by I.sub.0) via an inverter 272 to register selector gates via a gate 292 which is responsive to the series of gates 271.

NAND GATE 273 is responsive to the STORE signal generated by decoder 215, the I.sub.0 bit of the instruction word and FLGOP from decoder 201 for generating an ADCON signal for arithmetic unit 40. ADCON is a logical one when the arithmetic unit is to add the data or the X and Y inputs and a logical zero when it is to subtract the data on the Y input from the data on the X input.

REGISTER ADDRESS BUFFER

The RAB 44 is a three bit address register shown in FIG. 8, comprising three pairs of inverters 275, the contents of which are normally recycled at S30 via gates 276. RAB 44 is selectively loadable by the I.sub.4 -I.sub.6 bits of an instruction word via gates 277 which are controlled by a series of gates 279 responsive at S31 to a NAB signal received from decoder 210 via inverter 278. RAB 44 is also selectively loadable from the three least significant bits of the number stored in R5 register 34, via gates 280 which are actuated by a series of gates 281 responsive at S31 to a RAB signal from decoder 210 via inverter 282. The output from the three stages of RAB 44 are applied in parallel to the inputs of comparison gates 283 in storage register input/output circuit 42.

STORAGE REGISTER INPUT/OUTPUT CIRCUIT

Storage register input/output circuit 42, shown in FIG. 8, includes a three stage counter 284, each stage of which comprises two inverters, 284a and 284b. The counter is incremented once each instruction cycle by an S29 signal. The output from the three stage counter is applied on lines R, S, and T to comparison gates 283.

Comparison gates 283 output the COMPARE signal which is normally a logical one, a logical zero being outputted only when the state of the three bit counter 284 matches the state of the three bit number in RAB 44. The output of comparison gates 283 is connected to the inputs of four NOR gates 285a-285d. These four NOR gates are separately connected to the STAY, STYA, STAX and STXA signals, respectively, generated by decoder 210 and to the COMPARE signal from comparison gates 283. Thus, the four NOR gates 285a-d normally provide a logical zero output, except that a selected one of the NOR gates 285a-d will provide a logical one output upon the occurrence of (1) the decoding of a storage register operation by PLS 210 and (2) the COMPARE becoming a logical zero indicating a match between the contents of counter 284 and RAB 44. NOR gate 285a being responsive to the STAY and COMPARE signals, normally causes the data in the Y group of storage registers 39 to recirculate via gate 286a but upon receiving a STAY signal plus a COMPARE signal (e.g., both logical zeros), NOR gate 285a causes (via inverter 288a) gate 287a to become conductive and causes gate 286a to become nonconductive, thereby permitting the selected data word in the Y group storage registers to be read out on open circuited line 289a and to be replaced with data being read out of the 38b portion of operational register A into the selected storage location in the Y group via gate 287a. Similarly, NOR gate 285b normally permits recirculation in the X group of storage registers 39 via gate 286b, but allows a data word to be read out of operational register A into the X group via gate 287b which is controlled by inverter 288b which is in turn responsive to NOR gate 285b. NOR gates 285c and 285d are connected to gates 287c and 287d via inverters 288c and 288d, respectively, for providing a path for a data word to be inserted into operational register A from a selected storage register 39.

The STAY, STAX, STYA and STXA signals are also provided to NAND gate 290 which provides a logical 1 to NAND gate 291 when a storage register instruction has been decoded. NAND gate 291 is also responsive to COMPARE, thereby providing a logical zero HOLD signal whenever a storage register instruction has been decoded and there exists a mismatch between RAB 44 and the counter 284. The eight storage registers in each of the X and Y groups of storage registers 39 are conventional shift registers and therefore are not depicted in detail herein.

THE OPERATIONAL REGISTER SELECTOR GATES

Referring now to FIG. 9, there is shown a schematic diagram depicting the operational register selector gates. As can be seen from FIG. 9, the operational register selector gates preferably comprise a plurality of MOS transfer gates generally controlled by logic gates 230-235, 246 and 262.

As previously discussed, the operational registers A-D are divided each into two portions, a 38A portion and a 38B portion. The 38A portion provides 60 bits of storage for storing 15 four-bit decimal digits. The 38B portions provide four bits of storage for one decimal digit. The stages of operational registers are not shown in detail, although convention 21 stages may be utilized especially if the operational registers are of the architecture depicted in FIG. 13.

At state times S.sub.0, the D.sub.0 -D.sub.14 digits of a data word are stored in the 38A portion of an operational register, while the D.sub.15 digit is stored in the 38B portion of an operational register. A digit of a data word is clocked in two state times, so at state time S.sub.2 the D.sub.15 and D.sub.0 -D.sub.13 digits are stored in the 38A portion while the D.sub.14 digit is stored in the 38B portion when the data is merely recirculating via gates 316a-316d. As can be seen, there are two outputs from each operational register 38 connecting that register with the X input on line 302 or the Y input on line 303 to the arithmetic unit 40. The normal output is on line 301a-301d via gates 320a-320d and another output is on lines 305a-305d via gates 321a-321d. The outputs from gates 320a-320d and 321a-321d are each respectively connected to a common point 306a-306d before being interconnected by gates 310a-310d and 311a-311d with lines 302 and 303. Gates 320a-320d are responsive to the SLRC signal from line 263 (FIG. 8) while gates 221a-221d are responsive to the SLRC signal from line 264 (FIG. 8). The SLRC signal on line 263 is normally a logical 0, but becomes a logical 1 when a left shift command has been decoded by instruction word decoder logic 31 and the mask delay MD is enabled (e.g., a logical 1) or an exchange operation is indicated and MD is enabled. Thus, gates 320a-320d are normally conducting while gate 321a-321d are normally nonconducting except during the aforementioned operations. As can be seen, the normal outputs from the operational registers 38 is by lines 301a-301d to common points 306a-306d.

When a data word is not being outputted from an operation register 38, it is recirculated; and even during many outputting operations the data word also recirculates. The normal recirculation path is through gates 316a-316d for operational registers A-D. Gates 316a-316d are responsive to the RECA-RECD signals generated by NAND gate 246 and NOR gates 235b-235d, respectively (FIG. 8). The recirculation gates 316a-316d connect the output of the 38B portions on line 305a-306d with the inputs to the 38A portions on lines 307a-307d.

When an entire data word is outputted to the arithmetic unit 40, the D.sub.0 digit is outputted from the 38A portion while the D.sub.15 digit is recirculated via gates 316a-316d to the 38A portion and is subsequently outputted therefrom as the last digit of the data word. Since arithmetic unit 40 has a two state time delay, the D.sub.0 digit from the arithmetic unit is inputted to the 38A portion after the D.sub.15 digit has recirculated.

Recalling that during arithmetic operations, shifting operations, and exchange operations either all or a selected portion of the data word stored in an operational register 38 may be operated on according to the indicated operation (the selected portions being operated on is dictated according to the mask field of the decoded instruction word) the operational register selector gates 43 are arranged so as to permit the nonselected portions of the data words to be recirculated while the selected portions are either shifted or read into and out of the arithmetic unit 40 or exchanged as required by the decoded instruction word.

Since the normal output from the operational registers is on lines 301a-301d, the MASK.phi. signal provided by inverter 222 (FIG. 8), occurs as a selected digit or digits to be operated on under a selected mask (FIG. 6) is outputted from the 38A portion. Actually, MASK.phi. is provided one .phi. time early to set up the MOS gates in time. However, because gates 321a-321d control the output from the 38B portion of operational registers A-D during the aforementioned right shift for exchange operations, a digit desired to be unmasked appears at the output of the 38B portion (e.g., the time needed to cycle through the 38B portion) later than it would have been outputted on lines 301a-301d. Thus, mask delay generator 225 (FIG. 8) delays MASK.phi. two state times providing an MD.phi./P signal which is used in controlling gates 246 and 235b-235d by controlling te RECMASK signal applied thereto except during right shift operations.

Considering now right shifting of a data word under mask control, for instance, a right shift operation to be accomplished under the MANT (FIG. 6) mask of a data word in operational register A, the D.sub.15, D.sub.0 and D.sub.1 digits are first recirculated via gate 316a. Then gate 316a is opened and the D.sub.3 digit being outputted from the 38A portion of operational register A is recirculated on line 301a and by gates 230a, 335a, and 336a back to the input of operational register A on line 307a. During this time, the D.sub.2 digit was loaded into the 38B portion and changed to a binary 0000 by gates 308a and 309a and temporarily stored there until it is reinserted into the data word at the most significant digit under mask control at which time gates 335a and 336a are turned off and gate 316a is again turned on. Thus, it can be seen that all the digits within the MANT mask, that is the D.sub.2 -D.sub.12, have been right shifted one digit, the original least significant digit being lost and a 0000 being loaded into the most significant digit. Gates 336a-336d are controlled by the RECMASK signal from NAND gate 230 (FIG. 8) which is responsive to the MASK.phi. and SR' (right shift) signals. As can be seen, the recirculation gates normally operate on a two state time delay mask, but during right shift operations, must operate on a non-delayed mask. Gates 337a-337d are controlled by the respective register selector logic gates 231a-231d (FIG. 8) which are responsive to the GMASK signal on line 234 (a delayed mask in this case), STORE from decoder 215 (FIG. 8). Gates 308a-308d are responsive to the signals from NAND gates 231a-231d while gates 309a-309d are responsive to the SR signal from NAND gate 230 (FIG. 8).

During a left shift of data in operational A under the MANT mask, for instance, the D.sub.15, D.sub.0, and D.sub.1 digits are recirculated by gate 316a. Thus, at the beginning of state time S.sub.6, the D.sub.2 digit is ready to be shifted out of portion 38B of operational register A; at this time the SLRC signal on line 263 (FIG. 8) changes to a binary one at the aforementioned two state times later than the normal MASK.phi. signal, and the output from the 38B portion is then applied by gates 321a and 310a to the X input of arithmetic unit 40. Recirculation gate 316a is likewise opened two state times later than a normal mask (e.g., MD controls the RECMASK signal generated by NAND gate 247). The output on .SIGMA.' line 410 (FIG. 10) from the arithmetic unit 40 is, at the same time, applied by gates 270 (FIG. 8) and 312a to the input of operational register A. Since arithmetic unit 40 has four bits of delay associated therewith and since no data has been inputted to arithmetic unit 40, arithmetic unit 40 subsequently outputs 38a portion of operational register A on line 307a. Since no data is being inputted into the Y input of arithmetic unit 40, arithmetic unit 40 does not alter the data being entered on the X input but merely acts as four bits of delay during a left shift operation. After the most significant digit under mask control is read out of portion 38B, the recirculation mode is re-established by gate 316a and the SLRC signals revert back to a binary zero. Thus, a 0000 is being inserted into the least significant digit under mask control and the most significant digit has been lost, the intervening digits being left shifted one digit.

During the aforementioned left shift operations, it can be seen that gates 310a-310d must be enabled on a mask delayed two state times. However, during normal arithmetic operations when data is being read out on lines 301a-301d, gates 310a-310d and similarly gates 311a-311d (which control inputting of data to the Y input of arithmetic unit 40) must be operable on a normal mask signal or a delayed mask signal, depending on the type of operation being accomplished. Thus, the NAND gates 231a-231d and 232a-232d (FIG. 8) controlling the various selector gates 310a-310d and 311a and 311d are enabled by the GMASK signal on line 234 (FIG. 8) from NAND gates 259 (FIG. 8) on the normal mask for all operations except exchange and left shift when enabled on the delayed mask MD.phi./P. The register selector gates 312a-312d, which control the inputting of data words into the operational registers 38 via .SIGMA. line 304 and gate 270 (FIG. 8) from the output of arithmetic unit 40 online .SIGMA.', are controlled by NAND gates 233a-233d (FIG. 8) which are enabled only on a delayed mask because the result from arithmetic unit 40 on line .SIGMA.' is delayed one digit (two state times) due to two-state time delay of arithmetic unit 40. NAND gates 231a-231d are also inhibited by the STORE signal from decoder 209, so that the register receiving the data word, i.e., the register defined by the J field in the instruction word and decoded by decoders 238 and 239 (FIG. 8), is inhibited from entering the arithmetic unit 40. In addition during a store operation the output from one register is applied to the arithmetic unit 40, the output from the other being inhibited by the STORE signal; thus, the adder does not alter the number being inputted and outputs the data word back to the other register, thereby storing the contents of one register in both registers.

Gates 234 (FIG. 8) and gates 314 and 315 are utilized during an exchange operation. Considering an exchange between register A and register B under mask control, the digits normally recirculate via gates 316a-316d until the delayed mask comes up, at which time gates 321a-d become conductive and recirculation gates 316a and 316b become nonconductive. Gates 321a and 321d are now made conductive because the SLRC signal applied thereto now becomes a logical zero upon the occurrence of an exchange operation and delayed mask signal. The output from register B is then applied by line 305b and gates 321b and 311b to the Y input of the arithmetic unit 40. Gate 338a is controlled by NAND gate 232b by the aforementioned delayed mask GMASK signal on line 234 (FIG. 8). In addition to going to arithmetic unit 40, the contents of operational register B appearing on the Y input to arithmetic unit 40 is communicated back to the A register by gate 315, which is actuated on a delayed mask by NAND gate 234 (FIG. 8). The output from the A register is conveyed by line 305a and gates 321a and 314 to line 304. Line 304 (.SIGMA.) is normally connected to the .SIGMA.' line of arithmetic unit 401 however, during an exchange operation and the aforementioned flag set and reset operations, line 304 is disconnected from the .SIGMA.' line of arithmetic unit 40 by the action of gate 270 (FIG. 8). Line 304 is disconnected from arithmetic unit during an exchange operation, for example, because the data being applied to line 304 from operational register A by gate 314 would otherwise be garbled by the data exiting from arithmetic unit 40. Thus the output from operational register A now on line 346 is conveyed to the input of operational register B via gate 312b. Gate 270 (FIG. 8) is controlled by NAND gate 269 (FIG. 8) which is responsive to the S/RS signal and to EXCH generated by inverter 268 (FIG. 8).

As can be seen, gates 310a-310d control which one of the operational registers A-D is to be applied to the X input of the arithmetic unit 40 on line 302 via common points 360a-306d, respectively, while gates 311a-311d control which one of the operational registers A-D is to be interconnected with the Y input of the arithmetic unit 40 on line 303 via common points 306a-306d, respectively. Similarly, gates 312a-312d permit the interconnection of the output of arithmetic unit 40 on line 304 with any one of the four operational registers A-D. Permitting all the operational registers to be connected to either of the inputs or the output of arithmetic unit 40 is an important feature of the invention permitting greater flexibility in programming the calculator.

It should also be noted that during the aforementioned store and exchange operations that the exchanges and stores may be accomplished under mask control thereby providing more increased flexibility in the programming of the electronic calculator enclosed herein. This novel feature may be advantageously used, for example, when it is desired to use all 16 digits of a data word during an arithmetic operation. Then, for example, the three most significant digits of the data word (which are normally used for flag storage; see FIG. 6a) may be stored in either another operational register 38 or a storage register 39 and the 13 digits of data word normally available for arithmetic storage is expanded to 16 digits for performing arithmetic operations. This is highly advantageous to have more than the usual number of digits of numeric data available during certain calculations to assure that the final result is accurate; that is to say, that to assure that the final result is accurate to 10 decimal places, intermediate answers to 12 or 13 decimal places are occasionally required. The novel selector gate system 43 shown herein permits use of such greater capacity registers during such calculations without the necessity of having such large capacity registers being permanently implemented into the calculator.

ARITHMETIC UNIT

Referring now to FIG. 10 there is shown a schematic diagram depicting the arithmetic unit 40 implemented on chip 10. Arithmetic unit 40 is responsive to the HEX signal from NAND gate 229 (FIG. 8) for indicating whether arithmetic unit 40 is to be operated in binary coded decimal or hexadecimal. The HEX signal is applied to NOR gate 411 along with a logical one from S27 to S1. Thus NOR gate 411 outputs in false logic a HEX signal indicating either that hexidecimal signal BCDR has been decoded in decoder 206 (FIG. 8) or that the data then entering BCD corrector 408 on line 409 then corresponds to flag bits at which time the BCD corrector 408 is automatically disabled from state time S27 through S1. The output from NOR gate 411 is applied to NAND gate 407 for disabling the BCD corrector 408 and NAND gate 406 for disabling illegal BCD code detector.

The adder 405 of arithmetic unit 40 operates on three serial data imputs, 403, 404, and 416. Inputs 403 and 404 correspond to the aforementioned X and Y inputs, which are selectively couplable to the operational registers A-D by the operational registers selector gate 43. The other input, 416, contains a CARRY/BORROW bit from complex gate 417.

ADCON (from NAND gate 273, FIG. 8) provides a SUB signal, via inverter 418 and an ADD signal via another inverter 419. Adder 405 is caused to perform a subtraction function using the two's complement technique. The two's complement is accomplished by inverting each of the bits in the subtrahend and adding a binary one to each digit on line 416 unless a borrow operation was accomplished for the prior digit.

When operating in the addition mode, adder 405 receives the Y input at gate 421 in true logic while gates 422 and 423 receive the Y input in false logic. When the inputs are inverted for two's complement subtraction, however, gate 421 receives the Y input in false logic while gates 422 and 423 receive the Y input in true logic. The conversion between true and false logic and the inversion effected for two's complment subtraction is accomplished by gates 420 and 424 and inverters 425. Gates 420 conduct during two's complement subtraction and are responsive to the ADD signal outputted by inverter 419 while gates 424 are conductive during addition operations and are responsive to the SUB signal outputted by inventer 418.

The output from adder 405 is directed on line 426 to a two stage shift register 415 and thereon by line 409 to one input of BCD corrector 408. A CARRY signal on line 427 from adder 405 is directed to NOR gate 428 and complex gate 402. Complex gate 406 determines whether an illegal BCD digit has been produced during the addition (or two's complement subtraction) of digits being entered adder 405 on lines 403 and 404, and outputs a logical one to NAND gate 428 upon detection of an illegal BCD code (unless disabled by HEX) in register 415. Thus, NOR gate 428 outputs a correct signal which is a logical zero when either a carry signal is on line 427 or the aforementioned illegal BCD code has been detected by complex gate 406. Complex gate 417 is responsive to SUB, ADD, CORRECT, a C/B RESET signal and the C/B RESET signal norred with the carry signal on line 427 by NOR gate 429. The output from complex gate 417 is a logical one if (1) adder 405 is operating in an addition mode, NOR gate 428 indicates that a carry is required and C/B RESET is at zero or (2) adder 405 is operating in a subtraction mode and either a reset or a carry is indicated. During two's complement subtraction a carry indication occurs whenever the subtrahend is smaller than the minuend while a no carry indication indicates that the subtrahend is larger than the minuend, i.e., a borrow must occur and thus a zero is inserted on line 416, thereby not inserting the one normally added to the least significant bit during two's complement subtraction. Thus complex gate 417 produces a logical zero when an add mode and either no carry or a reset is indicated or when in a subtract mode and no reset or no carry are indicated. A reset condition is indicated by a logical one on C/B RESET. C/B RESET is generated by NAND gate 412 which is responsive to SO..phi.1 and to the output of NAND gate 413. NAND gate 413 is responsive to MSK.phi. from inverter 434 and a delayed MSK.phi. supplied by inverter 414.

Complex gates 430 are responsive to CORRECT, ADD, SUB, the carry signal on line 427, and to A and P1 clocks, determining whether or not an illegal BCD code or carry condition was detected by gate 428 for causing BCD corrector 408 to add a decimal six for addition or add a 10 for subtraction. For example, the addition of decimal numbers X=5 and Y=3 in the adder 405 produces binary output 1000 on line 426 which is a valid 8 in BCD. But adding X=5 and Y=7 produces an output 1100, which is invalid in BCD. Adding six (0110) to 1100 in BCD corrector 408 produces an output on line 410 of 0010. The carry is accomplished by the gates 417, 428 and 406 and the 0010 (a decimal 2) outputted from the BCD corrector 408 is of course the correct result. Since the least significant bit of each digit outputted by adder 405 need not be corrected, the least significant bit enters corrector 408 before complex gate 406 tests at .phi.1 of every odd state time for an illegal BCD code.

A binary six or 10 is produced by complex gate 430 depending on whether an addition or subtraction operation is performed. The output complex gate 430 is applied to NAND gate 407 for inserting six or 10, as indicated, so long as gate 407 is not disabled by the HEX indicating that hexadecimal arithmetic is required and so long as that adder 405 is operating in the addition mode and a carry is indicated by NOR gate 428 or that adder 405 is operating in a subtraction mode and line 427 indicates that no carry was accomplished. The aforementioned C/B RESET line 436 forces complex gate 417 to insert a one during subtraction operations in the very first bit operated on by adder 405 and inhibits an insertion of a one in the very first bit during addition operations, thereby inhibiting any inaccuracies occuring due to numbers previously existing in arithmetic unit 40 prior to insertion of desired data.

Complex gate 402 is responsive to SUB, ADD, line 427 and CORRECT thereby producing a one at its output when either (1) gate 428 indicates a carry condition during addition operations or (2) line 427 indicates a borrow condition (no carry) during subtraction operations. The output of complex gate 402 is applied to NAND gate 401, which in turn produces the ADDER CONDITION SET signal to condition latch 41 (FIG. 7).

NAND gate 401 is disabled by C/B STROBE from NOR gate 437 except at the end of a mask operation unless a toggle or exchange operation is indicated in which case NAND gate 401 is disabled by C/B STROBE regardless of the end of a mask operation being encountered. Accordingly, NOR gate 437 is responsive to TGLEXCH from NAND gate 274 (FIG. 8) and to a mask trailing edge circuit 438.

ADDER CONDITION SET is a logical zero when a carry or borrow exists for the first digit after the mask. This indicates an overflow from the mask field for producing an error indication, for instance, or for indicating a desired logical condition, depending on where in a program the overflow occurs. ADDER CONDITION SET therefor also produces a logical zero if a tested flag has been set.

REGISTER R5

R5 Register 34 is depicted at FIG. 10. Register R5 is an eight bit shift register which may be selectively loaded from either the serial output from arithmetic unit 40 on line 410 via gate 467 or may be loaded on lines KR1-3 and KR5-7 via gates 478 from keyboard logic 35 (at which times the MSB of each digit in Register R5 34 is loaded with a zero via gates 479 according to the keyboard code indicated in Table II). Data stored in R5 Register 34 may be selectively loaded into the Y input of arithmetic unit 40 via line 451 and inverter 452, or into program counter 32a (FIG. 7) via inverter 453, line 449 and inverter 158 (FIG. 7) or into RAB 44 via inverter 463. The capability of R5 Register 34 to supply addresses for program counter 32b or RAB 44 is an important feature of this invention providing for indirect addressing of program counter 32b and RAB 44.

R5 Register 34 includes 16 inverters 454 arranged in eight stages of two inverters 454 each. Each pair of inverters 454 comprising a stage are connected via gates 448 and are connectable via recirculation gates 455, for permitting recirculation of the bit stored in each stage of R5 Register 34. Gates 450 connect the stages to permit shifting of data between the stages of R5 Register 34 in a shift register mode. R5 Register 34 normally operates in the shift register mode, receiving and storing the two least significant digits of the adder output under control of the MDP signal received via NAND gates 461 and 465a unless register R5 34 is loaded on lines KR1-KR3 and KR5-KR7 from keyboard logic 35 in response to a "LOAD R5" signal on line 457. R5 Register 34 also operates in a recirculation mode when a "Branch to R5" instruction has been decoded as denoted by BKR from decoder 209 (FIG. 8). Thus, recirculation gates 455 are controlled by a NAND gate 456 which is responsive to NAND gate 465a, BKR and LOAD R5.

The output from register R5 34 is communicated to the Y input of adder 405 via line 451 when inverter 452 is enabled by a NAND gate 458 and gate 459 and to Branch Logic 32b via line 449. As will be seen, NAND gate 458 and gate 459 are controlled in response to the presence of 1R5 or and 2R5 signals from decoder 215 (FIG. 8). The three least significant bits of R5 Register 34 are loadable into RAB 44 in parallel via inverters 463.

The 1R5 and 2R5 signals are applied to input of two NAND gates 460 and 461. NAND gates 461 is also responsive to a FLGOP signal from inverter 462, to the MDP signal provided by mask delay generator 225 (FIG. 8) and a MD signal generated by inverter 463. Thus the output from NAND gate 461 is normally a logical one, however, a logical zero will occur when upon a MDP signal if 1R5, 2R5, and FLGOP are all a logical one, the zero output occuring for only one P time. A logical zero from NAND gate 461 is communicated through complex gates 464 to latch 465 comprising gates 465a and 465b, setting latch 465 so that the output from gate 465a is a logical one and the output from gate 465b is a logical zero. A logical zero from gate 465b enables gate 466, which in turn enables gate 467, permitting R5 Register 34 to function as a shift register and to insert the first eight bits reading out of arithmetic unit 40 on line 402 into R5 Register 34 via gate 467. As will be seen, latch 465 is reset to its normal state with a zero appearing on output of gate 465a and a one appearing on the output of 465b four state times later after R5 Register 34 has been loaded with the two least significant digits outputted on line 402. It should be noted that NAND gate 461 is operated on a delayed mask because the data being outputted on line 431 is two state times behind a normal mask.

NAND gate 468 is responsive to the MSK.phi. signal from gates 220 received via inverter 434, a delayed MSK.phi. signal from inverter 469 and the output from NAND gate 460, thus the output from NAND gate 468 is normally a one, but a zero occurs for one P time upon the occurrence of a MSK.phi. signal and either a 1R5 or 2R5 signal, thus setting latch 465a via gate 464 in much the same manner as NAND gate 461. The latch, now being set, outputs a logical one from gate 465a and a zero at gate 465b, and causes the output from gate 458 to go to a logical zero, NAND gate 458b being responsive to the output from NAND gates 465a and 460. The output from NAND gate 458 enables inverter 452 thereby inserting either four or eight bits of data stored in R5 Register 34 into the Y input of adder 405, the bits being inserted until latch 465 is reset to its normal reset state. Latch 465 remains in a set condition for either two or four state times, depending on whether (1) one digit is to be loaded from R5 Register 34 into the Y input of adder 405 according to a 1R5 signal or (2) two digits from R5 Register 34 is to be loaded into the Y input of adder 405 according to a 2R5 signal.

The resetting of latch 465 back to its normal condition is effected by dual speed shift register 440, which is responsive to the outputs from NAND gates 461 and 468 for resetting latch 465 two or four state times after the conditions occurring at the aforementioned gates set the latch. Two speed shift register 440 normally requires four state times for a bit to cycle therethrough, except when the 1R5 signal is a logical zero indicating that only one four bit digit is to be shifted from R5 Register 34 into the Y input of adder 405, thus requiring that the latch to be reset after two state times.

Dual speed shift register 440 includes a NAND gate 470, a series of six inverters 471-476 and another NAND gate 477. The NAND gate 470, the inverters 471-476 and NAND a gate 477 are coupled in series with clocking gates 470a-476a disposed between adjacent stages. Gate 470a between NAND gate 470 and inverter 471 is clocked at .phi.1 and similarly gate 474a between inverters 474 and 475 is also clocked at .phi.1 while gate 472a between inverters 472 and 473 and gate 476a between inverter 476 and NAND gate 477 is selectively clockable at either .phi.1 or .phi.2. The other clocking gates 471a, 473a and 475a are clocked at P. As can be seen, if gates 472a and 476a are clocked at .phi.2 there is a two state time delay in dual speed shift register 440 whereas if gates 472a and 476a are clocked at .phi.1 there is a four state time delay. Gates 472a and 476a are selectively clocked at .phi.1 and .phi.2 depending upon the state of 1R5, gates 472a and 476a being clocked at .phi.2 when 1R5 is a logical zero and clocked at .phi.1 when 1R5 is a logical one. Thus, clocking gates 472a and 476a are responsive to .phi.2 when supplied via gate 441. Gate 441 is responsive to 1R5 inverter to true logic by inverter 442. Clocking gates 472a and 476a are also responsive to .phi.1 when supplied via gate 443. Gate 443 is controlled by inverter 444 which is responsive to the output of inverter 442.

SCAN GENERATOR COUNTER AND SEGMENT/KEYBOARD SCAN

The keyboard logic 35, display decoder 46, output register 47, state time generator 48, scan generator counter 36A and segment/keyboard scan 36B are depicted in FIG. 11. The scan generator counter 36A comprises a three-bit shift register, each stage which is comprised of inverters 501 and 502, the stages providing outputs U, U, V, V, W, and W. Scan generator counter 36A also includes a series of gates 508 which are responsive to the outputs of the inverters. The output of gates 508 is connected to the input of inverter 501 in the first stage of the counter. Inverters 501 and 502 in each stage are interconnected by gates 539 which are clocked at SO.phi.1 and the stages of the counter are interconnected by gates 540 clocked at S31P1. Thus, the number contained in scan generator counter 36A is updated once each instruction cycle. The number loaded in the counter is dictated by the pattern of feedback logic gates 508, which produces the output shown at reference A on FIG. 11. As can be seen, counter 36A does not "count" sequentially, but during eight instruction cycle provides the three bit binary representations of zero through seven.

Gates 508 comprise an AND gate 508a which is responsive to U and V outputs of counter 36A, an OR gate 508b responsive to the output of AND gate 508a and the W output from counter 36A, an OR gate 508c responsive to the U, V, and W outputs from counter 36A, and a NAND gate 508d which is responsive to the outputs of OR gates 508b and 508c. The state of counter 36A is initialized by a RESET signal on line 505 which inserts a logical one into the 501 gates of each stage of counter 36A. As can be seen from the table at reference A, on FIG. 11, counter 36A "counts" through the eight different possible binary stages producing the following sequence in binary: 7,6,5,2,4,0,1,3. It is only required that the counter count through the possible eight states; there is no requirement that the eight states be in any particular sequence. Counter 36A is a novel feature of this invention which derives such a non-sequential binary output.

Referring now to Table Va, there is listed the states through which counter 36a counts. As can be seen, all the bits are left shifted one bit and a new bit is inserted turning each incrementing cycle, that is, once each instruction cycle. A new bit is generated by feedback logic gates 508 or other such feedback logic means. The pattern of the gates 508 has been described for the three bit counter and may be derived by taking the available signals, i.e., the outpt of each stage and its inverse, and solving Karnaugh equations for inserting a logical one into the least significant bit position of the next number to be generated in response to decoding an octal 6, 0, 1 or 3. Conversely, a zero is inserted into the least significant bit position of the next number to be generated when an octal 7, 5, 2 or 4 is decoded. Thus, the desired non-sequential pattern of states is generated.

Referring now to TABLE Vb, there is listed the states through which a four bit non-sequential counter would count, for example. Using a similar decoding scheme, that is, providing a pattern of gates similar to feedback logic gates 508 or other such feedback logic means, the outputs of the four stages and their inverses are used to provide a logical one in the least significant bit position of the next number to be generated in response to decoding a hexadecimal 0, 1, 3, 7, 14, 13, 12 or 2. The precise pattern of such gates is not shown in detail herein; however, the pattern may be derived by solving the Karnaugh equations for the aforementioned logical conditions of the feedback logic. It should be evident, moreover, that the non-sequential counter scheme here disclosed is usable with counters having more than four stages.

The segment/keyboard scan 36B is provided by an eight stage shift counter which is arranged as a ring counter for shifting a logical zero to a different stage during each instruction cycle. Each of these stages comprises a pair of inverters, 509 and 510, except for the first stage which comprises a NAND gate 509a and an inverter 510. The first stage drives the D segments of the display. The NAND gate 509a is responsive to the output of inverter 510 in the last stage and to circuit ground clocked at S31.phi.1. The eight stages in segment/keyboard scan 36B are interconnected by gates 514 which are clocked at S 30P1. Segment/keyboard scan 36B is further interconnected with the RESET signal on line 505 for inserting a logical one into all stages of the counter, gates 511 being used for inserting the one's into the 509 inverters. Gate 511a l inserts a zero into the 510 inverter of the first stage, which is equivalent to inserting a one into NAND gate 509a. The 509a NAND gate is responsive to gate 512 for inserting a zero into the first stage of segment/keyboard scan during the subsequent instruction cycle. The outputs from inverters 510 in each of the stages are connected to an output driver 513 whose output is connected to the pins labeled SEG A-SEG G and SEG P. Thus, one of the segment pins (SEG A-SEG G or SEG P) is enabled during each instruction cycle following the first instruction cycle. The segment drivers also serve as the strobing lines for strobing the keyboard as shown in FIG. 2.

The RESET signal is generated as is now explained. DISP, from decoder 209 (FIG. 8), is provided to a latch circuit comprised of inverters 503 and 504. The output of inverter 503, DISP, is supplied the input of an edge detecting circuit comprising an inverter 506 and a NAND gate 507. The edge detecting circuit senses a decoded display instruction for outputting RESET on line 505 to segment/keyboard scan 36B and scan generator counter 36A. OR gate 515 is responsive to the DISP and REL HOLD signals. NAND gate 500 is responsive to the HOLD signal from NAND gate 219 (FIG. 8) and the output of OR gate 515. The output from NAND gate 500, HOLD, is supplied to the add-one circuit 119 in program counter 32A (FIG. 7). Gates 500 and 515 cooperate with add-one circuit 119 and program counter 32A to stop incrementing the number stored in program counter 32A when either the HOLD signal is generated by NAND gate 291 in response to a non-match between the contents of counter 284 and RAB 44 or upon the decoding of a display instruction until REL HOLD is generated. REL HOLD is generated by PLA 527 indicating that scan generator/counter 36A has cycled through the eight possible states thereof.

KEYBOARD LOGIC

Keyboard logic 35 comprises a decoder 517 which is driven by inverters 518 which are in turn connected by via buffers 516 to chip 10 pins (K1-K5) and conductors 16' (FIG. 2) of X/Y matrix keyboard 12. Inverters 518 normally provide a logical one output to decoder 517 thus the outputs of the decoder 517 are normally at a logical zero. However, when a key is depressed while keyboard row conductors 14 are being scanned by the outputs occurring on SEG A-SEG P, a logical zero is outputed by one of the inverters 518 thus causing a binary representation of the particular one of five keyboard lines (K1-K5) to appear on the three output lines KR5-KR7 from decoder 517. At the same time the KEY DN (key down) signal from decoder from 517 becomes a logical one, indicating that a key has been depressed. Thus, when the KR1-KR3 inputs to R5 Register 34 are loaded from the U-W outputs scan generator counter 36a, the KR5-KR7 inputs of R5 Register 34 are derived from the output of decoder 517, thereby producing a unique binary input on lines KR1-KR3 and KR5-KR7 for each key position of the X/Y matrix keyboard 12. The inputs to R5 Register 34 caused by keyboard logic 35 are listed in Table II. The KR1-KR3 and KR5-KR7 inputs to R5 Register 34 are inputted at S30P1 after a key is depressed while the calculator is in a display mode. NAND gate 519 is responsive to DISP, KRY DN and a S30.phi.1 clock; the output from NAND gate 519 is gated out at S30P1 via gate 520 providing the LOAD R5 signal to line 457 (FIG. 10) in R5 Register 34, thereby effecting the loading of R5 Register 34 with a number from lines KR1-KR3 and KR5-KR7 indicative of a particular key depressed during a display operation. DISPLAY DECODER

Display decoder 46 receives a data representing numberals to be displayed from operational register A on line 549 and inverts the same by inverter 550. The data from operational register A is of course, in serial format and the least significant bit (in both true and false logic) is first loaded into the two input lines of programmable logic array (PLA) 521 at time P1 of an even state time (E.P1) via gates 522, the next least significant bit being loaded into two other inputs to PLA 521 via gates 523 at P2 of the same state time, the next bit being communicated at P1 of the next following odd state time (O.P1) to two more inputs to PLA 512 via gates 524 and the most significant bit of a digit being inputted into one input of PLA 512 at the next followng P2.

Display decoder 46 is also responsive to the data from operational register B, which indicates where the decimal point is to be displayed among the numerals, whether minus signs are to be provided and which digits are to be blanked according to the codes listed in Table III, which are decoded by inverters 525, 547 and 548 and NOR gate 526 in combination with PLA's 521 and 527. As is shown in Table III, the least significant bit, which is a minus sign indicator, is clocked to inverter 525 via gate 528 at P1 of an even state time (E.P1). The output from inverter 525 is the false logic minus sign which is clocked at O.P2 and E..phi.1 to PLA 521 and 527. A logical one in the second least significant bit of a digit from operational register B indicates that a decimal point is provided in that digit; this bit is clocked E.P2 via gate 529 and inverters 547 and 548 to PLA 527. A zero in the most significant bit of digit indicates that the digit is to be displayed (i.e. not blanked). This bit is communicated to NOR gate 526, which also receives a DISP signal from decoder 209 (FIG. 8); this bit is clocked at P2 of odd state times, providing an ENABLE signal in true logic to PLA 527. Of course, if ENABLE is a logical zero, the associated digit position is blanked (with the exception of the decimal point segment). The outputs from PLA 521 are outputted during O.P2 and E..phi.1; that is, after four bits of a serial data digit have been decoded in PLA 521, it is then clocked out to PLA 527. PLA 527 is also responsive to the U-W signals (indicating which segment is being scanned) provided by scan generator counter 36a and their inverses. Thus PLA 527 and 521 determine whether a logical one or a logical zero should be loaded into output register 47 for each digit received from operational registers A and B during the scan of a particular segment of the display. A logical one from PLA 527 loaded into a stage of output register 47 indicates that the particular character segment scanned by segment/keyboard scan 36b in the character position in the display corresponding to that stage of output register 47 should be actuated; a zero, on the other hand, indicates that the segment being scanned should not be actuated for the digit position corresponding to that stage. Decoder 529 "NANDS" the outputs of PLA 547 to provide 12 serial bits of data to a 12 bit shift register in output register 47.

Display decoder 46, being response to the contents of operation register A for the numeric information and the contents of register B for the display information, is a novel feature of this invention which reduces the amount of dedicated circuitry required for digit blanking, minus sign indication and decimal place indication. The disclosed system permits the contents of register B to be built up according to codes stored in the read-only-memory for providing the display information, thereby permitting greater flexibility in the numbers displayed. This simplifies, for example, the display of two separate numbers at the same time, one being on the right hand of the display, and the other being on the left hand side of the display and simplifies placing the negative sign adjacent to negative numbers displayed, as opposed to being on the left hand of the display as typically done in prior art display systems.

PLA 527 is also responsive to a decimal point blanking signal provided by an inverter 551 clocked at O.P2. Inverter 551 is responsive to the DISP signal from decoder 209 (FIG. 8). The ENABLE signal from NOR gate 526 is effective for disabling segments A-G of the display characters for blanking purposes. The decimal point blanking signal from inverter 551 is applied to a programmable gate 536 in decoder 527 for blanking the decimal point segment of the display. If programmable gate 536 is not programmed, then the decimal point segment in the display will actuate even when the calculator is in a nondisplaying (e.g., calculating) mode. This novel feature of the invention permits the decimal point segments of the display to appear to the operator of the electronic calculator to randomly light during calculations. This is particularly useful during long calculations, which require a second or more to accomplish, so as that the operator knows that some function is being performed and so to make the calculation time appear shorter. If the calculator is not implemented with long calculational programs, then gate 536 may be programmed to eliminate actuating the decimal point segments during calculations.

OUTPUT REGISTER

Output register 47 comprises a 12 stage shift register, each state comprising a pair of inverters 530 and 531. Output register 47 is loaded once each instruction cycle from PLA 527 via decoder 529. During the first instruction cycle of a display cycle, the HOLD signal from NAND gate 500 inhibits incrementing of the program counter 32a, the D segments in the display are decoded by display decoder 46 and output register 47 is loaded with the codes for strobing the D segments of the display. Since the contents of output register 47 is not provided to the display until the following instruction cycle, keyboard/segment scan 36b is arranged to start scanning during the instruction cycle following the decoding of a display instruction. First the D segments are energized in appropriate digit positions for one instruction cycle, followed by the A segments during the next instruction cycle, followed by the B segments and so forth as the logical zero steps through keyboard/segment scan 36b.

The calculator clock (FIG. 3) is responsive to the decoding of a display instruction by decoder 209 (FIG. 8) for slowing down the clock during display operations. The clock must be slowed down during display operations if a VLED display is used because, given the time required to turn on a VLED, and the normal clock frequency of the calculator disclosed herein, the duty cycle of the display would be approximately 65%; however, with the normal clock frequency reduced by one-fourth, the duty cycle improves to approximately 95%. Even at this reduced speed the segments are scanned at a rate faster than that which the human eye may discern and therefore the segments appear to be constantly actuated. To make the display constantly actuated, a display instruction word is typically followed by a conditional branch instruction word to branch back to the address of the display instruction until the condition latch 41 has been set by a LOAD R5 signal indicating that the operator is inserting new data. Moreover, in the embodiment depicted herein, preferably two display destructions are used as a pair (as denoted by reference A in FIG. 11) because the keyboard line KS7 is not strobbed until the first display cycle has been accomplished; recalling that the keyboard is responsive to an input only during a display cycle instruction as provided by NAND gate 519, the keyboard would not be sensitive to keys on the KS7 line unless two display instructions followed each other. Alternatively, of course, a trailing edge circuit could be built into the DISP signal applied to NAND gate 519 for delaying that signal one instruction.

Each of the inverters 531 in output register 47 is connected either to an inverter 533 or a NAND gate 534 or 535 via a gate 532 clocked at S30.phi.2. Inverters 533 and NAND gates 534 and 535 are precharged to V.sub.ss at S30P1. The stage of output register 47 corresponding to the least significant digit (D1) is connected by a NAND gate 535 to a depletion mode device 537 for supplying a V.sub.DISP voltage to the pin of chip 10 (D1/SEG P) which is connected to the common electrode of the display device in the least significant character position. NAND gate 535 is also interconnected with the output of the inverter 510 in the stage of segment/keyboard scan 36b corresponding to segment P. Further, the driver 513 corresponding to segment P is connected at its output to the depletion load device 537 corresponding to the least significant digit position of output register 47. This permits a reduction in the number of pins used on chip 10; however, then decimal point segment (segment P) may not be actuated in the least significant digit position. The interconnection between inverter 510 and NAND gate 535 assures that the current is not sourced and sinked at the same time at the D1/SEG P pin.

Similarly, the stage corresponding most significant digit (D12) in output register 47 is also interconnected via NAND gate 534 to its depletion load device 537, thereby permitting the connection of the D12 and segment D outputs to a common pin. Thus, NAND gate 534 is also responsive to an output from inverter 510 in the segment D stage of segment/keyboard scan 36b. The remaining digit positions in output register 47, D2-D11 are interconnected with the appropriate pins on chip 10 via inverters 533 and gates 532 interconnecting the outputs from inverters 531 with depletion load devices 537. Thus, for the D1 least significant character position all segments in the display except the P segment are energizable, for the D2-011 character positions all segments are energizable and for the D12 character position all segments except the D segment are energizable.

The outputs from NAND gates 534 and 535 and the output from inverters 533 are each provided to gates 538 in addition to gates 537. Gates 538 selectively interconnect the 12 display output pins (D1/SEG P-D12/SEG D) with feedback circuit 541. Feedback circuit 541 is connected with driver 513 in keyboard/segment scan 36B for maintaining a constant voltage across an actuated VLED.

STATE TIME GENERATOR

State time generator 48 is responsive to the calculator clocks .phi.1, P1, .phi.2 for providing a binary representation of which one of the 32 state times of the calculator is on lines A-E in true logic and lines A-E in false logic. While state time generator 48 is shown here with five stages for counting 32 possible states, it soon will be seen that state time generator 40A is expandable and reduceable to count through 2N possible states where N is equal the number of stages in the state time generator.

The first stage of state time generator 48 comprises two inverters 542a and 543a which are arranged in series with gate 544a, which is clocked at time .phi.1, forming a latch. The 543a gate provides the true logic A output and the output of the 542a gate provides the false logic A output. The output of gate 544a is connected by gate 545a to an inverter 551a. The output of inverter 551a is used to (1) provide a CARRY indication to the other stages of the state time generator 48 indicating a CARRY condition and (2) is clocked by gate 552a at time P2 back to the input of inverter 543a for changing the state of the latch. The aforementioned gates and inverters having an "a" subscript comprise the stage in state time generator 48 corresponding to the lease significant bit. The stages in state time generator 48 corresponding to the more significant bits are identical to the aforementioned stage except that (1) the subscripts for the gate and inverter numbers are changed to correspond to the more significant bit outputs and (2) the output from inverter 551 is clocked to the input of inverter 543 at time P2 only if a CARRY signal, i.e., a logical one, occurs at the output of inverter (s) 551 in all the preceeding less significant bit stages. Thus, gate 552b is responsive to not only the P2 clock signal but also the output of inverter 551a which is supplied by an inverter 553a to a gate 554a. Similarly, gate 552c, in a third stage of state time generator 48, is responsive not only to the P2 clock signal, but also the outputs of inverters 551a and 551b via NAND gate 553b and gate 554b.

State time generator 48 operates as is now described. Assuming that state time generator 48 is at time 00011, then inverters 543a, 551a, 543b, 551b, 542c, 542d, and 542e, are all outputting a logical one while inverters 542a, 542b, 543c, 551c, 543d, 551d, 543e, and 551e are all outputtting a logical zero. At time P2, however inverter 551a inserts a logical one into inverter 543a, thus changing the output from 543a to a logical zero; inverter 551b, likewise inserts a logical one into inverter 543b because inverter 553a is outputting a logical zero, thereby causing gate 554a to conduct the P2 timing signal. Also, at the same time P2, inverter 551c inserts a logical zero into inverter 543c because the outputs from inverters 551a and 551b are both a logical one and the output from NAND gate 553b is a logical zero, thereby permitting gate 552c to conduct at time P2. Thus the C output becomes a logical one while the B and A outputs become logical zeros. The D and E outputs remain unchanged because NAND gate 553c and 553d both provide a logical one output, there being at least one logical zero input thereto, thus gate 554c and 554d will not conduct the P2 clock unless through to gates 552d and 552e.

As can be seen, state time generator 48 is easily expandable by providing additional stages of the type shown and described by conditionally clocking the P2 pulses to the 552 gates, condition being tested by a NAND gate 553 which is responsive to the outputs from inverters 551 in each of the less significant bit stages.

The outputs from the stages of the state time generator on lines A-E and A-E provided to a decoder 555 for providing outputs corresponding to the particular state times required by the logic circuitry shown in FIG. 6-11. While state time generator decoder 555 is not shown with the gates being programmed, the gates would be programmed to provide indications of, for instance, the S.sub.0, S.sub.30, and S.sub.31 state times required by the logic circuitry depicted in the FIGS. 7-11.

REGISTER CONFIGURATION

As has been previously discussed, the operational registers 38 and the storage registers 39 are generally comprised of long shift registers, the stages of which are of known design. It should be evident, however, that given the 0.625 microsecond basic clock frequency, that the shift registers of the operational registers 38 or storage registers 39 must be able to accommodate at a high bit rate and further must be able to clock one bit from one stage to a following stage in two clock cycles. While it is presently known how to implement a shift register being able to accommodate such clock rates on such a low number of clock cycles (for instance, R5 Register 34 is of such a design), the design of the stages in the operational registers 38 and storage 39 can be simplified if the bit rate were halved and there were four clock cycles to transfer a bit between adjacent stages. Referring now to FIG. 14, there is shown at 14a and 14c the operational and storage registers arranged as 60 and 512 bit shift register respectively. However, utilizing the register architecture depicted in FIGS. 14b and 14d permits four clock cycles to be used for transferring a bit between adjacent stages in a shift register at one half the speed of the registers depicted in FIGS. 14a and 14c. The pairs of 30 bit and 256 bit shift registers of FIGS. 14b and 14d which have common outputs and inputs, are clocked on different phases of the same clock, i.e., one register of a pair may be clocked on a P1 clock while the other is clocked on a P2 clock conversely, one register of a pair may be clocked on a .phi.1 clock while the other is clocked on a .phi.2 clock. In any event, the outputs and inputs of a register pair tied in common with the intervening stages being of conventional design. Moreover, the data stream at the inputs and outputs of the register pairs of FIG. 14b and 14d are equivalent to that of FIG. 14a and 14d respectively. These pairs of registers is an important feature of this invention permitting the use of ordinary shift register stages in a shift register having a high bit rate and a low number of clock cycles to transfer a bit between stages thereof.

Having described the invention in connection with certain specific embodiments thereof, further modification may now suggest itself to those skilled in the art. It is to be understood that this invention is not limited to the specific embodiments disclosed, except as set forth in the appended claims.

INSTRUCTIONS:

1. branch on condition -- See FIG. 12(a). Program counter branches to location defined by A field (10 bits) only if C bit is the same state as is COND in the condition latch.

2. Branch Unconditionally (CALL) -- See FIG. 12(b). Program counter branches to location defined by A field (11 bits). Incremented address being branched from is stored in subroutine stack.

3. Branch to R5 -- See FIG. 12(c). Program counter branches to location defined by contents of R5 Register. Field Q is ignored.

4. Return -- See FIG. 12(d). Program counter branches to location defined by the last address to be stored in subroutine stack. Field Q is ignored.

5. Operations under Mask Control -- See FIG. 12(e)

6. Non-Mask Operations (misc). -- See FIG. 12(f). Unless otherwise specified, instruction is not dependent on content of Q.

7. Non-Mask Operations (Flag Operations) -- See FIG. 12(g)

The Flag Operation -- Toogle, set, reset and test -- are performed by arithmetic unit on flag address in register J, digit D and bit B. Flag test sets the condition latch if the flag is set; otherwise the condition latch is not affected. Toogle flag changes 1 to 0 and 0 to 1.