Positioning System and Method Particularly Useful for Magnetic Disk Drives

The present invention relates to a system for accurately positioning a device with respect to a reference on a body. The invention is particularly useful in a system for positioning a transducer (e.g., magnetic head) with respect to a record medium (e.g., multi-track disk), and is therefore described below with respect to such a positioning system.

The invention has particular application for use in low-cost drive systems for flexible (or "floppy") disks wherein the present state of the art permits only relatively low track densities, in the order of 48-64 tracks per inch (TPI), because of the substantial dimensional changes under varying temperature and humidity conditions. Obviously, the more accurately a head can be positioned, the higher the permissible track density before intolerable errors appear because of misposition. A number of solutions have been proposed to permit an increase in the track density to that approaching the rigid disk drives, which is in the order of 100-200 TPI and sometimes higher. One proposed solution is to provide specially pre-encoded tracks on one surface which tracks contain servo data enabling the head positioning servo to home in on the centre of the track, thereby positioning the transducer head accurately over the centre of the data track encoded on another surface. However, this solution is too unwieldly and too costly to implement on low cost flexible disk drives. Other proposed systems are approximate in that they compensate for changes in the dimensions of the drive rather than in the disks themselves.

An object of the present invention is to provide a positioning system and method which can be implemented at relatively low cost for accurately positioning a device with respect to a body despite temperature and humidity variations, which system and method are particularly useful for disk drives to enable higher track densities to be obtained.

According to one aspect of the present invention, there is provided a system for accurately positioning a device with respect to a reference on a body in accordance with a command position signal, despite temperature and humidity variations, comprising: measuring means for measuring the actual dimensional deviation of said body from its true dimension over a predetermined distance therealong and for producing a cumulative offset signal indicative of the cumulative deviation over said predetermined distance; computing means effective, upon the reception of a command position signal specifying a commanded displacement of said device, for producing a corrected position signal specifying said commanded displacement corrected by the deviation of said cumulative offset signal pro-rated over the distance of said commanded displacement; and positioning means for positioning said device in accordance with said corrected position signal.

According to a more specific aspect of the invention, the computing means comprises means for computing from said cumulative offset signal a gradient offset signal corresponding to the linear variation of said cumulative offset signal over said predetermined distance, and for utilising said gradient offset signal in producing said corrected position signal.

In the preferred embodiments of the invention described below, the measuring means periodically measures the actual dimensional deviation of the body from its true dimension over a predetermined distance thereof defined by two fixed reference points on the body, stores a value corresponding to said measurement, and utilises said latter value for producing the corrected position signal upon the reception of the command position signal.

The invention also provides a method for accurately positioning a device with respect to a reference on a body in accordance with a command position signal, despite temperature and humidity variations, comprising the steps: measuring the actual dimensional deviation of said body from its true dimension over a predetermined distance therealong and producing a cumulative offset signal indicative of the deviation over said predetermined distance; upon the reception of a command position signal specifying a commanded displacement of the device, producing a corrected position signal specifying said commanded displacement corrected by said cumulative offset signal pro-rated over the distance of said commanded displacement; and positioning said device in accordance with said corrected position signal.

The invention is particularly useful, and is therefore described below, in a system wherein the device to be positioned is a magnetic head, and the body with respect to which it is positioned is a multi-track record disk.

The invention may be implemented by conventional logic circuitry, but is preferably implemented by a microprocessor. Examples of both implementations are described below.

Further features and advantages of the invention will be apparent from the description below of two preferred embodiments thereof illustrated in the accompanying drawings, wherein:

FIG. 1 is a functional block diagram illustrating the generalized concept of a magnetic head positioning system constructed in accordance with the present invention;

FIG. 2 is a diagram helpful in understanding the invention;

FIG. 3 is a functional block diagram illustrating a conventional logic circuitry implementation of the invention;

FIG. 4 is a diagram of a States Machine used in the system of FIG. 3;

FIG. 5 is a States Diagram of the Machine of FIG. 4;

FIG. 6 is a block diagram illustrating a microprocessor implementation of the invention;

FIG. 7 is a flow diagram illustrating the operation of the microprocessor in the system of FIG. 6;

FIG. 8 is a block diagram illustrating the organisation of a microprocessor that may be used in the system of FIG. 6;

FIG. 9 is a block diagram illustrating the functional components of the microprocessor of FIG. 8; and

FIG. 10 is a flow diagram similar to that of FIG. 7 but illustrating another mode of operation of the microprocessor.

It has been found that the dimensional deviation of a record disk because of temperature and humidity changes is substantially linear with increasing radius. The presently used .cent.floppy disks" (which are plastic disks of 73/4 inches diameter coated with magnetic oxide) exhibit an expansion increasing linearly with increasing radius over the disk surface at the rate of .apprxeq.17.mu.in./in./.degree. C. Expansion is typically 0.005 inches maximum on the inside track and 0.015 inches maximum on the outside track over the permitted operating temperature and humidity range for the medium. Thus, by periodically measuring the total dimensional deviation of the record disk from its true dimension over a predetermined distance, the measured deviation may be interpolated or pro-rated for any specific portion of the distance and may be used for accurately positioning the head to a specified location despite the dimensional deviation of the disk because of temperature and humidity conditions.

FIG. 1 illustrates in generalized form a magnetic head positioning system constructed in accordance with the invention, wherein the magnetic disk is provided with two "servo" tracks for use as references for measuring the actual dimensional deviation of the disk from its true dimension. Thus, FIG. 1 illustrates the magnetic disk 2 as including an inner servo track X.sub.0 specifying track "0," and an outer servo track X.sub.1 specifying track "256." Providing two such tracks enables an accurate offset gradient to be computed for any particular disk and also simplifies the computation to produce the corrected position signal, as will be described more particularly below.

The magnetic head 4 is carried by a carriage 6 driven by a motor 8 controlled by a positioning system 10 to bring the head to a track address as specified in the address portion of a Position Command signal received from a host system 12 via a processor 14. To correct for dimensional deviations in the record disk because of temperature and humidity variations, a Calibration Command signal is periodically outputted from the processor 14 to the positioner system 10 which causes same to drive the head 4 first to the inner servo track X.sub.0 while an offset measuring system 16 measures the deviation (Y.sub.0) of the record disk from its true dimension at that track (FIG. 2), and then to the outer servo track X.sub.1 while the offset measuring system 16 measures the deviation (Y.sub.1) of the record disk from its true dimension at that track. The values Y.sub.0 and Y.sub.1 are fed to the processor 14 which produces a cumulative offset signal corresponding to the measured deviation (Y.sub.1 -Y.sub.0) over the distance between the servo tracks X.sub.1 and X.sub.0. The gradient offset (Y.sub.1 -Y.sub.0)/(X.sub.1 -X.sub.0), i.e., the linear variation of the cumulative offset over the distance between the servo tracks, may then be computed, stored and utilized to correct the positioner system for temperature and humidity variations. Thus, whenever a Position Command signal is received specifying a track address, the required offset Y, pro-rated for the distance specified by the Position Command signal and to be added to the Position Command signal, is computed as follows:

where N is the track address specified by the Position Command signal.

FIGS. 3-5 illustrate a conventional logic circuit implementation of the head positioning system, and FIGS. 6-10 illustrate a microprocessor implementation of such a system.

Shown in FIG. 3 is a drive, generally designated 22, including a hub 24 for receiving a multi-track record disk 26 such as a flexible (or "floppy") disk mentioned earlier which is subject to dimensional variations because of temperature and humidity changes. A magnetic head 28 is movable to any selected track on the record disk by means of a carriage 30 driven by a servo motor 32 fed by a servo amplifier 34. The track address is specified in the address lines 36 upon the issuance of a Position Command (SEEK) from the host system 38.

To enable an accurate offset gradient to be computed for any particular disk under the prevailing temperature and humidity conditions, the disk 26 is provided with the two servo tracks mentioned above, namely inner track X.sub.0 specifying track "0," and outer track X.sub.1 specifying track "256."

A calibration sequence is periodically (e.g. every 5 minutes) initiated during idle time of the system, i.e. when the disk is not in the process of reading, writing or seeking a track. The "reading or writing" status is flagged by a low output on POSSET (position settled) line from a comparator C.sub.1 which line goes high when no output is produced by amplifier 34; and the "seeking" status is flagged by a high output on SEEK line from the host system to a flip-flop FF which produces a high signal on its output BUSY line. During this calibration sequence, a control sequencer 40 (FIG. 4) produces a high signal on line Z.sub.0 enabling an analogue switch AS0 to output zero volts to servo amplifier 34 which controls motor 32 to bring the head 28 to the inner servo track X.sub.0 (track "0"). When the head has settled in position, the offset (Y.sub.0) at track X.sub.0 is read via an amplifier 42 and an offset measuring system 44 of known type producing an analog output corresponding to the deviation or offset of the head position from the true centre of the servo track. This analog offset is converted into digital form by an analog-to-digital converter (ADC) 46 which loads a latch 48 with the measured offset. Latch 48 is enabled to receive this measurement by a high signal on line "A," which signal also resets an up-counter 50.

The control sequencer 40 then drives line Z.sub.0 low, and line Z.sub.1 high, enabling analog switch AS1 to apply "plus" volts to amplifier 34 to cause motor 32 to drive the magnetic head 28 to track X.sub.1 (track 256). When the head has settled in position, the offset at this track is measured by amplifier 42 and the offset measuring system 44, and is loaded, via ADC 46, into down-counter 52. The latter is enabled by a high signal applied from control sequencer 40 on line "B," which also applies a low signal on line "A" to disable latch 48.

It will be seen that, at this instant, the measured offset (Y.sub.0) with respect to the inner track X.sub.0 is stored in latch 48, and the measured offset (Y.sub.1) with respect to the outer track X.sub.1 is stored in down-counter 52.

The contents of latch 48 are then subtracted from the contents of the down-counter 52 by means of a circuit which includes an AND-gate G1 enabled by a signal on line "C" from control sequencer 40 to pass clock pulses to increment up-counter 50 and to decrement down-counter 52 until the value in the up-counter equals that of latch 48 as detected by comparator C2. Equality is detected by a high signal on line "D," at which time the contents of the down-counter 52 equals the cumulative offset (Y.sub.1 -Y.sub.0) measured between tracks X.sub.0 and X.sub.1. This cumulative offset may then be divided by "256" (i.e., the number of tracks between track X.sub.0 and X.sub.1) to compute the gradient offset corresponding to the linear variation of the cumulative offset over the distance between tracks X.sub.0 and X.sub.1 ; and whenever it is desired to pro-rate or interpolate the cumulative offset over the distance of a commanded displacement (i.e., a specified track address), it would only be necessary to multiply the gradient offset by the specified track address.

The arrangement illustrated in FIG. 3 uses an 8-bit multiplier 54 for effecting the latter multiplication.

Multiplying two 8-bit numbers produces a 16-bit product, which may be conveniently divided by "256" by merely dropping the eight least significant bits. Accordingly, by merely dropping the eight least significant bits in the output of multiplier 54, and using only the eight most significant bits, a division by "256" is effected to convert the cumulative offset measured between tracks X.sub.0 and X.sub.1 to the gradient offset.

It will thus be seen that the output from the 8-bit multiplier 54, produced by multiplying the measured cumulative offset (Y.sub.1 -Y.sub.0) between tracks X.sub.0 and X.sub.1, and the specified track address (N), and dividing same by "256" (the distance X.sub.1 -X.sub.0), effected by dropping the eight least significant bit of the product, constitutes the measured offset pro-rated over the distance of the specified address.

The specified address (N) on input line 36 from the host system 38 is fed via a latch 56 to the multiplier 54, and its output, representing the offset pro-rated with respect to the specified address, is fed to a digital-to-analog-converter (DAC) 58. The specified address (N) is also fed via latch 56 to a second digital-to-analogue converter (DAC) 60. The outputs of the two DAC's 58, 60 are summed in the servo amplifier 34 and are used to position the magnetic head 28 at the precise location specified by address N as corrected by the measured offset pro-rated for that specified address.

FIG. 5 is a States Diagram more particularly illustrating the operation of the circuit of FIG. 3 as controlled by the States Machine of FIG. 4. The State Machine of FIG. 4 includes a Control Sequencer 40 having three "status" inputs, namely: "BUSY" status, specifying whether the magnetic head is in the process of seeking a track by virtue of a SEEK signal from the host system; a "POSSET" status, specifying whether the magnetic head has settled in position after having been driven to a specified track; and "D" status from comparator C.sub.2, specifying that equality has been detected between the contents of latch 48 and up-counter 50 as described above. Control sequencer 40 has five outputs, namely: Z.sub.0, commanding the head to move to track X.sub.0 ; Z.sub.1, commanding the head to move to track X.sub.1 ; "A," enabling latch 48 and resetting up-counter 50; "B," enabling down-counter 52; and "C," enabling the clock pulses to pass through gate G1 to up-counter 50 and down-counter 52. A timer 62 periodically initiates a calibration sequence, for example every five minutes or any other suitable time interval.

When a calibration sequence is initiated by timer 62, the system moves through the following states:

State S.sub.0 is the idle state, at which time all the outputs from the control sequencer 40 are reset.

The system moves to State S.sub.1 whenever an output signal is received from timer 62, provided the host system 38 is not in a "BUSY" status, i.e., the head is not reading, writing or seeking a track. In State S.sub.1, the sequence controller sets Z.sub.0, which causes the servo amplifier 34 to drive motor 32 to bring the head 28 to the inner servo track X.sub.0, the other outputs of the sequencer being reset.

When the head has settled in position, as determined by a POSSET status, the system moves to State S.sub.2. In this state, the control sequencer 40 resets Z.sub.0 and sets "A" for a short time (e.g. 1.mu.S), which resets up-counter 50 and enables latch 48 to receive the offset measured at track X.sub.0 from the offset measuring circuit 44 and ADC 46. At the end of this short interval, "A" is reset, whereupon the system moves to State S.sub.3.

In State S.sub.3, the control sequencer 40 sets Z.sub.1 and resets its remaining outputs, whereupon the magnetic head is driven to track X.sub.1. When the head settles in this position (POSSET status), the system moves to State S.sub.4, whereupon "B" is set for a short interval (e.g. 1.mu.s) which enables the down-counter 52 to receive the measured offset with respect to track X.sub.1. After this short interval, "B" is reset and the system moves to State S.sub.5, whereupon "C" is set, enabling gate G1 to pass the clock pulses to increment the up-counter 50 and to decrement the down-counter 52 until the contents of the up-counter equals that of latch 48. This is detected by comparator C2, which outputs a "D" signal, indicating, equality to the control sequencer 40, moving the system to the original idle State S.sub.0.

It will thus be seen that during this sequence, the system has measured the total offset (Y.sub.1 -Y.sub.0) between tracks X.sub.0 and X.sub.1 and has stored this value in down-counter 52.

As described earlier, when an address (N) is specified on input bus 36 from the host system 38, this address is fed via latch 56 to DAC 60 and, in addition, to the eight-bit multiplier 54. The latter multiplies the address (N) by the stored measured offset (Y.sub.1 -Y.sub.0) and at the same time divides this value (by dropping the eight least significant bits from the product) by the number of tracks ("256") between the servo tracks X.sub.0 and X.sub.1. This produces a value corresponding to the gradient offset multiplied by the number of tracks specified in the address to produce an output corresponding to the measured offset pro-rated over the number of tracks specified in the address on input bus 38. This pro-rated offset is fed to digital-to-analogue converter DAC 58 and is summed in servo amplifier 34 with the value corresponding to the specified address from DAC 60. The output of the servo amplifier 34, used to control servo motor 32 to drive the magnetic head 28 to the specified address, will now accurately position the head to the specified address as corrected by the measured deviation of the disk from its true dimensions caused by temperature and humidity conditions.

FIG. 6 is a diagram illustrating a microprocessor implementation of the above-described system.

The system illustrated in FIG. 6 includes a disk drive unit, generally designated 122, having a central hub 124 for the disk 126 provided with the two servo tracks X.sub.0, X.sub.1 as described above. The magnetic head 128 is carried by a carriage 130 driven by a motor 132 fed from a servo control system 134 via an amplifier 136. Information may be read out of the record tracks via a read amplifier 138 or into the record tracks via a write amplifier 140 into or from a host system 142 via an interface 144. A microprocessor MP periodically sends the magnetic head first to track X.sub.0 where the offset at that track is measured by an offset measuring circuit 146 via read amplifier 138, and then to track X.sub.1 where the offset at that track is measured. The measured offsets are converted to digital form via an ADC 148 before being inputted into the microprocessor MP.

The microprocessor MP stores the measured cumulative offset (Y.sub.1 -Y.sub.0) or the offset gradient computed by dividing the measured cumulative offset by the distance between the servo tracks X.sub.0 and X.sub.1, i.e. (Y.sub.1 -Y.sub.0) (X.sub.1 -X.sub.0). When a SEEK command is received from the host system 142 via interface 144, specifying a particular address (N) for the magnetic head, the microprocessor computes the correct position in order to compensate for humidity and temperature variations, and outputs this information to DAC 150. The original address (N) from the host system 142 is outputted to DAC 152, and is summed with the output of DAC 150 in the servo control system 134 where it is fed, via amplifier 136, to the drive motor 132 to drive the magnetic head 128 to the specified address.

FIG. 7 is a state flow chart illustrating the sequential operation of the system programmed as described above. Thus, in the initialized State S.sub.A, the microprocessor registers are reset. The system advances to State S.sub.B upon receiving an input SEEK command from the host system 142 specifying a track address (N), during which state the system signals its BUSY status disabling it from entering the Calibration Sequence described above where it measures and computes the cumulative offset Y.sub.1 31 Y.sub.0 between servo tracks X.sub.1 and X.sub.0. In State S.sub.C the system compares the desired (specified) address N with the actual address (i.e., where the head is at that instant). If the desired address is below the actual address, the actual address is decremented by "1" (State S.sub.D) and returned to State S.sub.C ; and if it is above, the actual address is incremented by "1" (State S.sub.E) and returned to State S.sub.C. When equality is detected, the system moves to State S.sub.F, where the measured offsets Y.sub.1 and Y.sub.0 at the servo tracks X.sub.1 and X.sub.0 are inputted into the registers of the microprocessor, it being recalled that these offsets are periodically being computed during the idle time of the system. The system then moves to State S.sub.G where the gradient offset (O.sub.G) is computed by dividing the cumulative offset (Y.sub.1 -Y.sub.0) by the number of tracks (256) between the servo tracks X.sub.1 and X.sub.0. The system then moves to State S.sub.H where the gradient offset (O.sub.G) is multiplied by the specified track address (N) to produce the pro-rated offset for that track address outputted (via DAC 150, FIG. 6) to the servo control circuit 134 during the next State S.sub.1. When the head has settled in position (State S.sub.J), the system returns to its START condition, and it awaits the reception of the next SEEK command from the host system, the system periodically entering the Calibration Sequence during idle periods to continuously up-date the offset values Y.sub.0 and Y.sub.1.

FIGS. 8 and 9 illustrate the organisation and the functional details, respectively, of a commercially available microprocessor that may be used in the microprocessor implementation of the system of FIGS. 6 and 7. Further details of the microprocessor are designed in United Kingdom Patent No. 1,429,379 of July 24, 1973, corresponding to U.S. Pat. No. 3,878,514 of Apr. 15, 1975.

The illustrated microprocessor is a single chip one implemented in P-channel MOS technology in a 16-pin DIP package with a 9-.mu.s. instruction rate and having a TTL compatible interface. As shown in FIG. 8, it has two basic interface signal terminals for external data, namely, a bit-serial-by-byte input terminal DATAIN, and a bit-serial-by-byte output terminal DATAOUT. Information is normally shifted into the microprocessor from an external shift register. The microprocessor can select one of four such input registers in one instruction; conversely, it can load one of five output registers in another instruction. Consequently, the microprocessor can manipulate any one of nine registers, where each register can be of any length.

The microprocessor consists of five functional parts, namely:

The machine, although serially implemented, appears to the programmer as an 8-bit parallel machine for all data functions.

Logic Unit LU consists of three 8-bit registers (A1, A2, A3), an 8-bit B-register, a serial adder SA, and selectors. The registers are recirculating static shift registers so that information can be transferred into the adder without changing the contents of the registers. The inputs to the adder on the X-select are any of the A-registers or zero, and on the Y-select are the B-register or its complement, the alternate microprogram count register (AMPCR), or zero. The output from the adder can be gated into A1, A2, A3, B, AMPCR and external registers (via the DATAOUT line). The adder itself is capable of eight operations (X+Y, X+Y+1, XOR, EQV, AND, OR, NAND, NOR). The adder also feeds four conditions to the condition register, "least bit true" (LST), "most bit true" (MST), "overflow" (AOV) and "all bits true" (ABT). These conditions are set when the associated bit is true, and reset, when false. These Logic Unit conditions do not change until the next logic unit operation and are testable using the condition test instruction.

Memory Control Unit MCU consists primarily of two 8-bit registers: the Microprogram Count Register MPCR and the Alternate Microprogram Count Register AMPCR. The MPCR is an 8-bit counter that can be incremented by one or two. The AMPCR stores jump addresses for changing the sequence of instructions. The MPCR selects the next instruction (successor) from the microprogram memory.

The Microprogram Memory PMP may contain up to 256 words, each 12 bits in length. The memory contains only executable instructions and cannot be changed under program control. The 12-bit instructions are decoded into one of three types: literal, conditional, and logical. Eight of these 12 bits can be transferred directly into the AMPCR, B-register, or the external device (DEV) control register.

The Control Unit CU provides eight testable conditions, condition selection logic, successor determination, instruction decoding logic, and timing for the processor. The eight conditions which may be tested are: AOV, MST, LST, ABT (mentioned above), plus three local conditions set or reset by the program, LC1, LC2, LC3; plus an external asynchronous condition EXT. The successor selection is either: MPCR+1; MPCR+2; AMPCR; or MPCR+1 (which also goes to AMPCR). These successors are called STEP, SKIP, JUMP and SAVE, respectively. The microprocessor uses an external clock input (CI) for internal timing. During each instruction, nine clocks are used, one for setup and eight for data. After the last data clock, the microprocessor checks for the Memory Cycle Continue (MCC) level before starting the next instruction. In continuous operation, this signal is true. The control unit also provides two outgoing timing signals: Clock Out (CO) carries the eight data shift pulses for external register clocking; and Last Pulse (LP) which indicates the end of each instruction and the start of the next operation.

The 16-pin external interface accommodates four types of signals: 1) Data, 2) Control, 3) Timing, and 4) Power (+5 volts, -12 volts, ground).

The DATAIN is the main input for data into the microprocessor. The data is controlled by the BEX command in the logic unit instruction, which enables the serial gating of information into the B-register.

The EXT input condition level is controlled externally and tested by the condition test instruction. It can be used for example to: (1) receive input data, (2) indicate an interrupt is present in an external interrupt register, or (3) have externally selected meaning for various external devices.

The DATAOUT line is the data output interface from the microprocessor. The information is always sent out in 8-bit bursts and can be synchronously gated into an external shift register using the CO clock pulses.

The four External Control signals from the microprocessor control the gating of information into and out of the microprocessor and also indicate how information is to be used by the interface. Two lines, A and B, when decoded, designate the type of operation taking place internal and external to the microprocessor. The combinations are as follows: BEX (A=1, B=0) indicates a Logic Unit Instruction (see Table 2 below) is in progress with one of four BEX destinations and the external data is gated into the B-register; OUT (A=0, B=1) indicates the Logic Unit Instruction is in progress with one of the four OUT destinations selected; DEV (A=1, B=1) indicates an external Literal Instruction (see Table 1 below) is in progress internally and an 8-bit literal from MPM is being transferred out of the microprocessor on the DATAOUT line to the external DEVICE control register; and (A=0, B=0) is the default code for all other internal instructions other than the three specified above (i.e., BEX, OUT, and DEV).

The other two pins of the four external control lines are bits 9 and 10, respectively, of the microprogram instruction. These lines come out ungated and can be combined with the decoded BEX and OUT to determine which of the four external registers was internally selected.

The MPCR Clear signal clears the MPCR register such that the next instruction to be executed will be location zero.

The FORCED STEP signal is used for chip test only where the contents of the Microprogram Memory (MPM) is dumped to the external interface.

The Memory Cycle Continue (MCC) level initiates the start of an instruction by enabling the internal timing generator. This timing generator creates internal shift pulses from the clock input. This level can be used to slow the execution of an MPM instruction to any frequency including single step.

Input clock pulses (CI) feed the timing generator controlling bit frequency; the pulses produced from the timing generator are used to gate and control all the internal and external shift registers. The Clock Output (CO) shift pulses from the timing generator are used to synchronize the external registers. The last pulse (LP) indicates that eight data shaft pulses have occurred. Therefore the external registers are (1) loaded, or (2) information has been accepted by the microprocessor.

There are four Literal type instructions each utilizing an 8-bit constant from Micro Program Memory: Literal to B, Literal to AMPCR, GOTO (i.e. literal to MPCR) and Literal to External Device (DEV) register. Examples of these assembly instructions are as follows: 25 = :B, table = :AMPCR, GOTO loop, xmit = :DEV. Note the names (table, loop, xmit) would be defined as an 8-bit value by the programmer to the assembler.

The Condition Test instruction checks one of eight specified conditions (i.e. four logic, three local flags, one external) and executes the indicated true or false successor depending on the outcome of the test. The successors are STEP, SKIP, JUMP and SAVE. If one wishes to have an unconditional successor, both fields should have the same successor. Example: JUMP is the equivalent to IFAOVJUMPELSEJUMP. If the tested condition is true, one of the three local conditions can be optionally set. Local conditions are reset on testing.

As described previously, the adder is capable of eight operations from which over 20 basic operations are available with appropriate X and Y register selects. The destination is determined by the designated instruction field. The Y select and operations are combined so not all combinations are available. Note AMPCR (indicated by Z in the Y select field) will be zero unless the AMPCR is selected as a destination. The destination field has four major groups: four Internal registers; four Output registers; simultaneous loading the B-register from external (BEX) together with the adder loading the selected internal register; and single bit right shift of the selected internal registers with adder filling the most bit.

Timing: The fetch of the next instruction and the execution of the present instruction are overlapped. This fetch-execute cycle requires 9 clocks pulses; therefore, with a 1-MHz clock, 9 microseconds is the instruction execution time.

The following Tables 1, 2 and 3 illustrate Literal Instructions, Logic Test Instructions, and Condition Test Instructions, respectively.

The microprocessor illustrated in FIGS. 8 and 9 is programmed to perform the above-described functions in the magnetic head positioner system illustrated in FIGS. 6 and 7. Tables 4 and 5 below illustrate a program that may be used. The Addresses and the Instruction Labels are in the Hexadecimal notation, and Table 6 below illustrates how this notation may be converted to the binary notation.

Following are additional comments which will be helpful in understanding the operation of the microprocessor of FIGS. 8 and 9 in accordance with the program of Table 4.

It will be seen that Instruction 1 (Address "00") can be converted (by reference to Table 5 above) from the hexadecimal notation "000" to the binary notation: 0000 0000 0000. The two rightmost (least significant) bits (00) specify a Literal Instruction, JUMP to AMPCR (Table 1); the next two bits are not used; and the remaining 8 bits specify that all 0's are to be loaded into the AMPCR. This instruction thus clears the AMPCR.

Instruction 2 (address "01") can be converted from the hexadecimal notation "0L9" to the binary notation: 0000 1100 1001. The two rightmost bits (01) specify a Logic Unit Instruction (Table 2); the next four bits (0010) specify Destination Select A2; the next four bits (0011) specify Operation Z; and the two leftmost bits (00) specify Select "0." This instruction thus calls for the clearing of register A2.

Instruction 3 (address "02") can be converted from the hexadecimal notation "8M1" to the binary notation: 1000 1101 0001. The two rightmost bits (01) specify a Logic Unit Instruction (Table 2) as the preceding instruction; the next four bits (0100) specify Destination Select OUT O; the next four bits specify the Operation is Z; the two leftmost bits (10) specify Select A2. This instruction thus calls for sending the contents of register A2 (which is 0 to OUT O, which in effect means to clear the OUT O register.

Instruction 4 (address "03") may be converted from the hexadecimal notation to the binary notation: 1111 1111 1111. The three rightmosst bits (111) specify a Condition Test Instruction (Table 3); and the next four bits (1111) specify a SAVE SAVE Instruction. Thus, this instruction says SAVE the contents of the next address in AMPCR (i.e., save address "04" in AMPRC). This is the JUMP Address; return to this address for every JUMP instruction until another SAVE SAVE Instruction.

Instruction 5 (address "04") may be converted from the hexadecimal notation 0N1 to: 0000 1110 0001. The two rightmost bits (01) specify a Logic Unit Instruction (Table 2); the next four bits (1000) specify a Destination Select B, BEX; the next four bits (0011) specify operation Z; and the two leftmost bits (00) specify Select O. This instruction thus says clear register B and take DATA IN into B; BEX means external to "B;" i.e. put the SEEK Command into B.

The program of Table 4 comprises 40 further instructions in addition to the five explained above, or a total of 45 instructions. It will be seen that, by reference to Tables 1-3, these 40 additional instructions call for the following:

Instuction 6 (address "05") is a Dummy Instruction; pass B through the adder to set up the condition flag in the adder.

Instruction 7 (address "06"): if LST is true, then STEP; else JUMP (i.e. back to AMPCR of instruction at address "03.") Actually, Instructions 6 and 7 form a fast idle loop to interrogate whether the SEEK Command is received.

Instruction 8 (address "07"): when LST is true (i.e. SEEK Command is received), then clear DEV register (the output status register); "0" means "busy" (STATUS = busy).

Instruction 9 (address "08"): clear register A1 and take DATA IN (desired address) into B. Instruction 10 (address "09"): send contents of B to register A1.

Instruction 11 (address "OJ"): send contents of register A1 to register B (register A1 is a store).

Instruction 12 (address "OK"): compare A2 (current address) with B (desired address) and store in A3.

Instruction 13 (address "OL"): see whether equality is present; if "yes," go to instruction 14; if "no," go to instruction 15.

Instruction 14 (address "OM"): if equality, go to CALC (branch instruction 25).

Instructions 15-28 (addresses "ON"-"IK"): in effect say increment by "1" or decrement by "1" depending on whether desired (BEXO) greater or less than actual (A2) until equality obtained.

Instruction 29 (address "IL"): CALC loading offset 1 into BEX2 (B1 register).

Instruction 30 (address "IM"): output actual address to OUTPUT O.

Instruction 31 (address "IN"): transfer contents of B offset to A1.

Instruction 32 (address "1"): load the B-register with number "248;" this is part of a multiplier routine.

Instruction 33 (address "20"): transfer "248" to A3, and BEX3 into B; A3 is set up to indicate the number of shifts.

Instruction 34 (address "21"): input offsets of tracks T256-T0 (X.sub.1 -X.sub.0 in FIG. 6).

Instruction 35 (address "22"): clear A1; i.e. offset 1-offset 2.

Instructions 36-42 (addresses "23"-"29") constitute a multiplying sequence for multiplying A2 (track address) by B (T.sub.256 -T.sub.0 offset), and dividing by "256," this being done by dropping the eight least significant bits and retaining the 8 most significant bits as described above.

Instruction 43 (address "2J"): put answer to OUT 1; i.e. output the offset.

Instruction 44 (address "2K"): clear the busy status (DEV register made all 1's which means "not busy").

Instruction 45 (address "2L"): go to START; i.e. loop for the next SEEK command.

FIG. 10 is a state flow chart similar to that of FIG. 7 but illustrating a variation in the operation of the microprocessor. In the variation of FIG. 10, the states S.sub.F ' and S.sub.G ', corresponding to states S.sub.F and S.sub.G in FIG. 7, are removed from the main stream of calculations and are repositioned in an idle loop. Thus, the measured offsets Y.sub.1 and Y.sub.0 are inputted periodically (e.g. every 5 minutes) as defined by an idle timer S.sub.K '. The computation of O.sub.G is also performed during the idle loop as shown by box S.sub.G ' being in the idle loop. The remaining states in the flow chart of FIG. 10 correspond to those in FIG. 7 and carry the corresponding reference characters but include a "prime" mark. The main advantage in the operation illustrated in FIG. 10 is that it substantially decreases the access time over the operation illustrated in FIG. 7.

Whereas the above described embodiments measure the actual dimensional deviation or offset over a predetermined distance measured between the two servo tracks X.sub.0 and X.sub.1, the offset could be measured with respect to only one servo track (X.sub.1) and a stored constant used in place of the other servo track (X.sub.0).

Many other variations, applications, and implementations of the invention will be apparent to those skilled in the art.