Apparatus for Displaying Numerical Value Information in Alternative Forms

1. Field of the Invention

The present invention relates to an apparatus for displaying numerical value information. More specifically, the present invention relates to such an apparatus for displaying multi-digit numerical value information by either or both of first and second different kinds of groups of numeral characters.

2. Description of the Prior Art

Numerical value information is typically processed today in electronic data processing machines, from which the resultant numerical value information is then taken for some desired subsequent purpose. The resultant numerical value information is sometimes converted ultimately to a visual indication for observation by an operator. Devices for such visual indication may be of various types, such as flourescent segment arranged indicating tubes, Nixie type discharge tubes, cathode ray tubes, and the like. For the purpose of indication of multi-digit numerical value information each digit having a value of one of a set of numerals, a display having a predetermined plurality of digit display positions is provided. Typically, such a set of numerals is comprised of the numerals zero through nine.

For the purpose of display of numerical value information, a display has been most widely used which is capable of displaying the numeral characters of Arabic numerals. However, in some countries the numeral characters of Arabic numerals are not so familiar to the nations and are often hardly understood. Recently small sized electronic numerical data processing machines such as portable type or desk top type electronic calculators have been manufactured and widely used, which are typically provided with a display capable of displaying Arabic numerals. Such calculators, however, are inconvenient for those in the Arabian language countries where the Arabian language numerals have been more often used. Hence, it is desired that electronic numerical data processing machines are provided wherein a display capable of selectively displaying numerical value information by either or both of first and second different kinds of groups of numeral characters, such as Arabic numerals and Arabian language numerals. The present invention achieves that purpose.

Briefly stated, the present invention comprises an apparatus for displaying numerical value information, comprising: display means capable of displaying multi-digit numerical value information by first and second different kinds of groups of numeral characters, each digit of said multi-digit numerical value information having a value of one of a set of numerals: means for providing a signal representing multi-digit numerical value information, said multi-digit numerical value information comprising a plurality of digit numeral signals, each of said numeral signals representing, in a coded fashion of a plurality of bits, a value of the numeral to be displayed in the corresponding digit display position in said display means; converting means for converting said digit numeral signal in the respective digit of said coded multi-digit numerical value information signal into first and second kinds of character signals for representing said coded multi-digit numerical value information by said first and second kinds of groups of numeral characters; and means responsive to said first and second kinds of character signals for driving said display means for selectively displaying said coded multi-digit numerical value information by either or both of said first and second kinds of groups of numeral characters, respectively.

According to the present invention, the resultant numerical value information as processed by electronic numerical data processing machines, such as electronic calculators, is selectively displayed by either or both of first and second different kinds of groups of numeral characters, such as Arabic numerals and Arabian language numerals. Preferably, selecting means is provided for selecting display of the numerical value information by either or both of said first and second different kinds of groups of numeral characters.

In a preferred embodiment, said coded multi-digit numerical value information signal is first converted into a set of individual signals each uniquely identifying the numeral in the respective digit in said coded multi-digit numerical value information, and said individual numeral identifying signal is then converted into said first and second different kinds of character signals for representing said coded multi-digit numerical value information by said first and second different kinds of groups of numeral characters.

Therefore, a principal object of the present invention is to provide an apparatus for displaying numerical value information wherein said numerical value information is displayed by first and second different kinds of groups of numeral characters.

Another object of the present invention is to provide an improved apparatus for displaying numerical value information wherein said numerical value information is selectively displayed by either or both of first and second different kinds of groups of numeral characters.

A further object of the present invention is to provide an improved apparatus for displaying numerical value information, which comprises a simplified structure for converting said numerical value information into two sets of numeral character signals for displaying said numerical value information by first and second different kinds of groups of numeral characters.

These objects and other objects, features and advantages of the present invention will be better understood when taken in conjunction with the accompanying drawings.

FIG. 1 is a perspective view of a desk top electronic calculator of an embodiment of the present invention;

FIG. 2 is a table showing a relation between a group of numeral characters of Arabic numerals and a group of numeral characters of Arabian language numerals;

FIG. 3 is a view of a numeral display unit in the respective digit display position in the display DIS1 in the FIG. 1 embodiment, said unit having a plurality of segments arranged in a minus-in-square shape or 8 shape for displaying selectively one of a group of numeral characters of Arabic numerals through selective light emission therefrom;

FIG. 4 is a view of a numeral display unit in the respective digit display position in the display DIS2 in the FIG. 1 embodiment, said unit having a plurality of segments arranged as shown for displaying selectively one of a group of numeral characters of Arabian language numerals through selective light emission therefrom;

FIG. 5 is a block diagram of a desk top electronic calculator employing the present invention to be embodied in the FIG. 1 calculator;

FIG. 6 is a schematic diagram of the first display DIS1 in the FIG. 5 embodiment, to which a schematic diagram of the second display DIS2 is similar;

FIG. 7 shows waveforms of various clock and timing signals to be used in the FIG. 5 embodiment;

FIG. 8 is a schematic diagram of the first signal converting circuit 2 in the FIG. 5 embodiment;

FIGS. 9 and 10 show a connection of the row and column signal lines by means of MOS transistors in the FIG. 8 circuit;

FIG. 11 is a schematic diagram of the second signal converting circuit 3 in the FIG. 5 embodiment;

FIG. 12 is a block diagram of a desk top electronic calculator of another embodiment of the present invention to be embodied in the FIG. 1 calculator;

FIG. 13 is a schematic diagram of the third signal converting circuits 3' in the FIG. 12 embodiment;

FIG. 14 is a perspective view of a desk top electronic calculator of another embodiment of the present invention;

FIG. 15 is a view of the display unit in the respective digit display positions in the display DIS3 in the FIG. 14 embodiment, said unit having a plurality of segments arranged as shown for selectively displaying one of the numerals by either the Arabic numeral characters or the Arabian language numeral characters in the common digit display position;

FIG. 16 is a block diagram of the FIG. 14 calculator which employs a further embodiment of the display of the present invention to be embodied in the FIG. 14 calculator;

FIG. 17 is a schematic diagram of the signal converting circuits 3" in the FIG. 16 embodiment; and

FIG. 18 shows a connection between the row and column signal lines by means of MOS transistors in the FIG. 17 circuit.

FIG. 1 is a perspective view of a desk top electronic calculator of an embodiment of the present invention. The calculator shown comprises a first and second displays DIS1 and DIS2, respectively, arranged in parallel in the upper region on the top surface of the calculator. The calculator also comprises a switch EXS for selectively switching the two parallel-arranged displays DIS1 and DIS2. The switch EXS is adapted to be switchable to three positions P1, P2 and P3, such that the first display DIS1 is enabled when the switch EXS is turned to the first position P1, the first and second displays DIS1 and DIS2 are enabled when the switch EXS is turned to the second position P2 and the second display DIS3 is enabled when the switch EXS is turned to the third position P3. The calculator shown further comprises a power switch BS and a group of key switches, generally denoted as KSW, provided on the top surface of the calculator. The first and second displays DIS1 and DIS2 each comprises a plurality of display tubes positioned in the respective digit display positions, thereby to display multi-digit numerical value information. Each of the displays DIS1 and DIS2 is adapted to be capable of displaying multi-digit numerical value information by a predetermined kind of group of numeral characters which kind of group is different from each other. In the embodiment shown, the first display DIS1 is adapted to display the numerical value information by a group of numeral characters representing Arabic numerals most generally used, while the second display DIS2 is adapted to display numerical value information by a group of numeral characters representing the numerals of the Arabian language (referred to as "Arabian language numerals" hereinafter).

FIG. 2 is a table showing a relation between a group of numeral characters of Arabic numerals and a group of numeral characters of Arabian language numerals. As seen from the table, the numeral characters of the Arabian language numerals each have a character configuration shown in the lower row corresponding to the Arabic numerals 1 through 10 shown in the upper row of the table. Each digit display tube of the first display DIS1 comprises a numeral display unit having a plurality of segments arranged typically in a minus-in-square shape or 8 shape, as shown in FIG. 3, in order to selectively display one numeral character out of a group of numeral characters of Arabic numerals through selective light emission from the segments. Such a numeral display unit typically comprises seven segments a through g and a decimal point segment l. On the other hand, each digit display tube of the second display DIS2 comprises a numeral display unit having another plurality of segments arranged in the pattern as shown in FIG. 4 in order to selectively display one numeral character out of a group of the numeral characters of the Arabian lanugage numerals through selective light emission from the segments. The Arabian language numeral display unit as shown in FIG. 4 typically comprises eleven segments a' through k' and a decimal point segment l'. These segments may be made of a liquid crystal area, an array of light emitting diodes, a flourescent area or the like, which are individually connected to a driver so as to be enabled to emit light, whereby selective light emission from these segments forms one numeral character out of the respective group of the numerals. In order to display the value of numeral one, for example, by the corresponding Arabic numeral, the segments b and c in FIG. 3 are enabled to emit light. On the other hand, in order to display the value of the same numeral one by the corresponding Arabian language numeral, the segments e' and i' in FIG. 4 are enabled to emit light. Similarly, in order to display the value of the numeral two, the segments a, b, g, e and d in FIG. 3 are enabled to emit light, thereby to form the configuration of the corresponding Arabic numeral, and the segments c', e', and i' in FIG. 4 are enabled to emit light, thereby to form a configuration of the corresponding Arabian language numeral.

Table 1 shows a relation between a group of numeral characters of the Arabic numerals and the segments, as shown in FIG. 3, to be enabled to form a configuration of the corresponding Arabic numerals.

Table 2 shows a relation between the group of numeral characters of the Arabian language numerals and the segments, as shown in FIG. 4, to be enabled to form a configuration of the corresponding Arabian language numerals.

fig. 5 is a block diagram of the desk top electronic calculator shown in FIG. 1, which also comprises a block diagram of the display apparatus of one embodiment of the present invention. An input signal as entered by means of an input device such as a key board 7 comprising a set of key switches KSW is encoded by means of a key encoder 8. Assuming that the input signal is a signal representative of multi-digit numerical value information, such a numerical value information signal is loaded in a display register 10 through a gate G1 operable as a function of a gate signal g1. Assuming that the input signal is a signal representative of function as entered by means of a function key, such a function signal is transferred to a control circuit CC, which is responsive to the function signal to provide a control signal to an arithmetic unit 50 for the purpose of controlling the operation. Operation in the electronic calculator is effected through cooperation of the display register 10 and arithmetic unit 50 and the result of operation is loaded in the display register 10 through gate G2 operable as a function of a gate signal g2. The control circuit CC also serves to generate the said gate signals g1 and g2. The arithmetic unit 50 comprises an operation register or accumulator 5 and an operation circuit 6 which is responsive to a proper function signal to effect operation with respect to the contents in the display register 10 and the contents in the operation register 5, whereupon the result of the operation is again transferred to the operation register 5, i.e. the operation register 5 is up-dated to store the result of operation.

In recent electronic numerical data processing machines, such as desk top electronic calculators, for example, electronic circuits employing two-phase logic circuits operable as a function of two trains of clock pulses cp1 and cp2 out of phase with each other are utilized. In such electronic circuits, various timing signals, such as bit, digit and word timing signals, are generated based upon such clock pulses for the purpose of operation of various electronic circuits in a synchronized relation. FIG. 7 shows waveforms of these signals. Referring to FIG. 5, the above described two trains of clock pulses cp1 and cp2 out of phase with each other are generated by a clock and timing generator 30. Further, four bit timing signals t1, t2, t3 and t4 are generated by the generator 30 based on the said two trains of clock pulses cp1 and cp2. In the embodiment shown, a further train of clock pulses cp4 is also generated by the generator 30 as a logical product of the clock pulse cp1 and the bit timing signal t4. According to the embodiment, the digit timing signals T1, T2, T3 . . . T8 are further generated by the digit timing signal generator 4 coupled to the generator 30 based on the said bit timing signals t1, t2, t3 and t4, in the manner well known to those skilled in the art.

In the embodiment shown, the display register 10 comprises eight digit positions, each being constituted by four bit positions. It is pointed out that in FIG. 5 only the least significant digit position 10A in the register 10 is shown being constituted of four-bit structure, while other digit positions are shown by omitting illustration of such four-bit structure therein. The first to fourth bit positions of each digit position are weighted of "1", "2", "4" and "8", respectively, as well known to those skilled in the art. The coded multi-digit numerical value information signal stored in the display register 10 is circulated through the said arithmetic unit 50 and the gate G2 as a function of the clock pulse cp4 and only one digit component of the numerical value information signal in the register 10 is read out by the retaining circuit 1 and is retained therein for a time period of one digit as a function of the clock pulse cp4. The output from the retaining circuit 1 is fed as a function of a clock pulse cp4 to a first signal converting circuit 2, which is responsive to the four-bit coded signal from the retaining circuit 1 to convert the said four-bit coded signal into a set of individual signals each uniquely representative of a value of one of the numerals zero through nine, i.e. a set of numeral representing signals, and is responsive to the said individual numeral representing signals as thus decoded to encode them into a first group of segment selecting signals. More detailed structure of the first signal converting circuit 2 will be described subsequently with reference to FIG. 8. The segment selecting signals from the first signal converting circuit 2 are applied individually to segment drivers SD1 through SD8 for driving commonly the corresponding segments of each digit position of the first display DIS1, and also to a second signal converting circuit 3, which serves to decode the first set of segment selecting signals from the first signal converting circuit 2 into a set of individual signals each uniquely representing a value of one of the numerals zero through nine and further to encode the said decoded individual numeral representing signals into a second set of segment selecting signals. More detailed structure of the second signal converting circuit 3 will be described subsequently with reference to FIG. 11. The second set of segment selecting signals from the second signal converting circuit 3 are individually applied to segment drivers SD1' through SD12' for driving commonly the corresponding segments of each digit position of the second display DIS2.

The displays DIS1 and DIS2 each comprises display tubes (not shown in FIG. 5 for simplicity of illustration) as shown in FIGS. 3 and 4, respectively, in each of eight digit display positions, and each also comprise eight digit drivers D1 through D8 for the respective eight digit display tubes in the eight digit display positions. The corresponding segment electrodes of the respective digit display tubes are commonly connected (not shown in FIG. 5), and the said segment drivers SD1 through SD8 and SD'1 through SD'12 for driving the respective commonly connected segment electrodes are provided in the respective displays DIS1 and DIS2. The said digit drivers D1 through D8 are connected individually to receive the corresponding digit timing signals T1 through T8, respectively, provided in the digit timing sequence fromm the digit timing signal generator 4. For example, consider a case where a numeral is to be displayed in the first digit of the display DIS1. The coded numerical value information component of the corresponding digit of the numerical value information signal is read out from the said display register 10 at the digit timing one digit time before the digit time T1, i.e. at the digit timing of T8, and is retained in the retaining circuit 1 for a time period of one digit time, with the result that the retaining circuit 1 provides the numerical value information signal component corresponding to the said first digit position at the digit timing T1. The said numerical value information signal component is converted by means of the first signal converting circuit 2 into a set of segment selecting signals which are applied to the respective segment drivers SD1 through SD8 in the display DIS1. As a result, only the segment drivers out of the drivers SD1 through SD8 necessary for display of the numeral of the said numerical value information signal component are brought in an active state only during the digit time T1. At that time, only the digit driver D1 is supplied with the digit timing signal T1. As a result, the relevant segments of only the first digit display tubes are caused to emit light, thereby to display the said numeral of the said numerical value information signal component. During the following digit time T2, the first digit display tube is disabled, while only the second digit display tube is enabled as a function of digit timing signal, and thus the enabled condition of the digit display tubes proceeds in turn toward the more significant digit display positions, while the respective numerals of the corresponding numerical value information signal components are displayed in the respective digit positions. Since these operations are repeated in a high speed, display of multi-digit numerical information can be observed from the respective displays DIS1 and DIS2. The first and second displays DIS1 and DIS2 are of substantially the same circuit configuration, except for the difference in the shape and number of the segments between the displays DIS1 and DIS2. A typical example of such a circuit configuration will be explanined subsequently with reference to FIG. 6.

The said switch EXS is interconnected between the first and second displays DIS1 and DIS2. The switch EXS may be a sliding switch which comprises a sliding member SL and contacts P1a, P1b, P2a, P2b, P3a, P3b. The sliding member SL is connected to the -V voltage source which is a power supply of the displays, as to be described subsequently with reference to FIG. 6. The contacts P1a and P2a are commonly connected to the terminal of the -V voltage source of the first display DIS1. Similarly, the contacts P2b and P3b are commonly connected to the terminal of the -V voltage source of the second display DIS2. The turning of the switch EXS to the first position P1 causes the sliding member SL to contact the contacts P1a and P1b, the turning of the switch EXS to the second position P2 causes the sliding member SL to contact the contacts P2a and P2b, and the turning of the switch EXS to the third position P3 causes the sliding member SL to contact the contacts P3a and P3b, whereby selective energization of the displays DIS1 and/or DIS2 is achieved, as previously described with reference to FIG. 1.

FIG. 6 shows a schematic diagram of the first display DIS1, to which a schematic diagram of the second display DIS2 is similar, as previously pointed out. The digit timing signals generated in a digit timing sequence from the digit timing signal generator are applied, after being inverted, to bases of transistors TR1 through TR8, respectively, which serve as digit drivers D1 through D8 in FIG. 5. The segment drivers SD1 through SD8 comprising the transistors TR11 through TR18 are connected to drive or enable eight segments a through l, respectively, arranged in the said minus-in-square shape or the 8 shape and provided in each of flourescent-segment arranged tubes DT1 through DT8 of the respective digit positions. The transistors TR11 through TR18 each have the bases connected to receive the segment selecting signals Sl, Sg, Sf, . . . Sb, Sa, respectively, so as to control conduction of the respective transistors. More specifically, the flourescent-segment arranged tubes DT1 through DT8 each comprise eight segment electrodes coated with a flourescent material and a common electrode provided in operative association with these segment electrodes, while the corresponding segment electrodes throughout different tubes are commonly connected. It is appreciated by those skilled in the art from the foregoing description that the display tubes in FIG. 6 are driven on the so called dynamic basis as a function of the digit timing signals generated in the digit timing sequence.

FIG. 8 is a schematic diagram of the first signal converting circuit 2 in FIG. 5. Referring to FIG. 8, the coded output signal of four bits weighted of "1", "2", "4", "8", obtained from the retaining circuit 1 in FIG. 5, is applied in parallel to column signal lines 217, 215, 213 and 211, respectively, and further through inverters 44, 43, 42 and 41, respectively, to column signal lines 218, 216, 214 and 212, respectively. Row signal lines 0, 1, 2, . . . 9 are connected by means of MOS transistors d to predetermined ones of the column signals lines 211 through 218. Connection of the row and column signal lines by means of MOS transistors d is shown in more detail in FIG. 9. As seen in FIG. 9, the row signal lines 0 through 9 are all connected to a voltage source of the low level through a resistor R. The MOS transistor d has the gate connected to one of the column signal lines 211 through 219, the drain connected to one of the row signal lines 0 through 9, and the source grounded. The source as grounded is in the high level with respect to the low level voltage source. It is assumed in the present specification that the MOS transistors d are of a type which becomes conductive when the low level input is applied to the gate electrode thereof. In addition, MOS transistors d' are connected between the column signal line 219 and all of the row signal lines 0 through 9. The column signal line 219 is supplied with the high level potential, only when the segment selecting signals Sa through Sl are to be withdrawn. Further, MOS transistors d1 are connected between the row signal lines 0 through 9 and predetermined ones out of the column signal lines 220 through 227, as shown. Connection between the row signal lines 0 through 9 and the column signal lines 220 through 226 by means of MOS transistors d1 is shown in FIG. 10. As seen in FIG. 10, one end of each of the column signal lines 220 through 227 is connected by a respective resistor R' to a voltage source of the low level and each MOS transistor d1 has the gate connected to one of the row signal lines 0 through 9, the drain connected to one of the input lines 220 through 226, and the source grounded or connected to the high level voltage source. The MOS transistors d1 are also of a type which becomes conductive when the low level input is applied to the gate electrode thereof. The other ends of the column signal lines 220 through 227 are each connected via inverting amplifiers 46 through 53, respectively, as necessary, to the first display DIS1 and the second signal converting circuit 3. For the purpose of display of the decimal point, the output signal from the said column signal line 219 and the decimal point indicating signal DP are applied to an AND gate 28, and the output from the AND gate 28 is, via the inverting amplifier 53, withdrawn as the output Sl.

For simplicity of the explanation, operation of the FIG. 8 circuit will be first described. For the purpose of describing the operation, let it be assumed that the coded output signal from the retaining circuit 1 is "0001" representing the value of the numeral one. In brief, the first signal converting circuit shown in FIG. 8 serves to convert the output signal from the retaining circuit 1 representing in a coded manner, one-digit numerical value information into a set of segment selecting signals Sa, Sb, . . . Sg, Sl for selecting required segments in the display tubes in the first display DIS1 so as to form a configuration of required numeral characters by selective light emission from the segments. Thus, it is appreciated that if and when the coded numerical value information signal is "0001", the high level output should be withdrawn from the output terminals Sb and Sc to cause light emission from the segments b and c in FIG. 3. Such an operation of the circuit will be described in more detail in the following. In response to the said coded numerical value information signal "0001", the high level is applied to the column signal line 217, while the low level is applied to the other column signal lines 215, 213 and 211, and accordingly the column signal line 218 is supplied with the low level, while the column signal lines 216, 214 and 212 are supplied with the high level. All the intersections between the column signal lines 212, 214, 216 and 217 and the row signal line 1 as supplied with the high level have been provided with MOS transistors d. Therefore, all these MOS transistors d do not become conductive, because of the high level in the gate electrode thereof. No MOS transistors are connected between the row signal line 1 and the column signal lines other than the column signal lines 212, 214, 216 and 217. Normally, column signal line 219 is in the high level. As a result, all the MOS transistors d and d' connected to the row signal line 1 do not become conductive, and accordingly, the row signal line 1 is forced to the low level as a function of the low level voltage source, as shown in FIG. 9. Therefore, the MOS transistors d1 at the intersections between the row signal line 1 and the column signal lines 221 and 222 become conductive, as seen from FIG. 10, thereby to provide the high level outputs, which are inverted by inverting amplifiers 47 and 48, respectively, to provide the outputs Sb and Sc, respectively. As a result, the segments b and c in FIG. 3 are enabled to emit light, thereby to display the configuration of the Arabic numeral character of the numeral one.

It is pointed out that although in the foregoing description the display segments were shown and depicted as embodied in the flourescent segment arranged display tubes, any other types of segments, such as liquid crystal segments, may be used for the purpose of the present invention and, if and when the liquid crystal segments are used, these segments can be driven by the outputs direct from the column signal lines 221 and 222, without inversion, i.e. the outputs Sb and Sc, in case of the above described example. It is also printed out that this fact is applicable to any other embodiments of the present invention to be described subsequently.

In summary, the first signal converting circuit 2 first serves to convert the coded numerical value information signal applied through the column signal lines into a set of individual numeral representing signals each uniquely representing one of the numerals by means of a matrix implemented by the row signal lines 0 through 9 and column signal lines 211 through 219, thereby to provide the said individual numeral representing signals at the respective row signal lines, and further serves to convert the said individual numeral representing signals as withdrawn through the row signal lines 0 through 9 into a set of segment selecting signals for selecting required segments arranged in the minus-in-square shape in each of the display tubes of the first display DIS1 by means of a matrix implemented by the row signal lines 0 through 9 and the column signal lines 220 through 226.

In the foregoing description, the embodiment of the present invention was described as employing in the displays the well-known segment arranged display tubes. Alternatively, however, well known gas discharge tubes such as Nixie tubes may be used each of which has 10 display electrodes shaped in different Arabic numeral characters zero through nine or Arabian language numeral characters zero through nine and has a common electrode associated with the said ten electrodes for the purpose of digit driving. In such an embodiment, the above described row signal lines zero through nine each individually uniquely identifying the value of numerals 0 through 9 of the matrix implemented by the row signal lines 0 through 9 and the column signal lines 211 through 219 may be used to drive the said ten character shaped electrodes, of both the displays DIS1 and DIS2, while the matrix implemented by the row signal lines 0 through 9 and the column signal lines 220 through 226 as well as the second signal converting circuit 3 may be dispensed with. In such embodiment, the said individual numeral identifying signals obtainable from the row signal lines 0 through 9 are commonly applied to the corresponding character shaped electrodes, respectively, in the manner similar to that of the segment arranged display tubes.

FIG. 11 is a schematic diagram of the second signal converting circuit 3 shown in FIG. 5. The principle of operation of the second signal converting circuit 3 is substantially the same as that of the above described first signal converting circuit 2. Referring to FIG. 11, only the signals Sa, Sb, Se, Sf and Sg, as not inverted, out of the said segment selecting signals Sa through Sg obtainable from the first signal converting circuit 2 are applied to the column signal lines 111, 113, 115, 117 and 119, respectively, and further through inverters 11, 12, 13, 14 and 15, respectively, to the column signal lines 112, 114, 116, 118 and 120, respectively. It is appreciated that these column signal lines 111 through 120, as combined with the row signal lines 0 through 9, constitute another matrix. The predetermined intersections between these row signal lines and the column signal lines are provided with MOS transistors d, as shown in FIG. 11. Connection of these MOS transistors d is the same as shown in FIG. 9. MOS transitors d' are connected between the column signal line 121 and all of the row signal lines 0 through 9. The connection of these MOS transistors d' is also the same as shown in FIG. 9. The column signal line 121 should be forced to the high level potential, if and when the second display DIS2 is to be enabled to display the numerical value information. The row signal lines 0 through 9, combined with the column signal lines 122 through 132, constitute a further matrix. Predetermined intersections between the row signal lines and the column signal lines are provided with MOS transistors d1. The connection of these MOS transistors d 1 is the same as shown in FIG. 10. The other ends of the column signal lines 122 through 132 are each connected through inverting amplifiers 16 through 26, respectively, as necessary, to the second display DIS2. The output from the said column signal line 121 is applied to one input to an AND gate 28'. The other input to the AND gate 28' is connected to receive a signal DP for displaying the period mark (.). The output from the AND gate 28' is withdrawn through an inverting amplifier 27.

Now operation will be described with reference to FIG. 11. Assuming that the coded numerical value information signal obtainable from the retaining circuit 1 is "0001" representative of the value of the numeral one, then, as seen from the previous description with reference to FIG. 8, only the outputs at the output terminals Sb and Sc from the first signal converting circuit 2 become the high level, while the other outputs are all the low level. Therefore, the outputs Sa and Sg applied to the column signal lines 111 and 119 in FIG. 11 become the low level, and thus the outputs from the inverters 11 and 15 become the high level. It is pointed out that the outputs Sa and Sg to be applied to the column signal lines 111 and 119 both become the low level, only if and when the coded numerical value information signal is "0001", i.e. the value of the numerical character to be displayed is the numeral one. Thus, only if and when the numeral character to be displayed is the numeral one, the outputs from the inverters 11 and 15 both become the high level, when the MOS transistors d' at both intersections between the row signal line 1 and the column signal lines 112 and 120 do not become conductive, because the gate input thereto is the high level. Since no MOS transistors are connected between the row signal lines 1 and the column signal lines other than the column signal lines 112 and 120, and the column signal line 121 has been brought to the high level only if and when display should be effected by the first and second displays DIS1 and DIS2, none of the MOS transistors d and d' connected to the row signal line 1 becomes conductive and accordingly the row signal line 1 is forced to the low level potential as a function of the low level voltage source, as shown in FIG. 9. As a result, the MOS transistors d1 connected between the row signal line 1 and the column signal lines 126 and 130 become conductive, because of the low level of the gate input thereto, and accordingly the column signal line 126 and 130 are forced to the high level, which means the high level at the outputs Se' and Si'. These outputs Se' and Si' are invert-amplified by means of inverting amplifiers 20 and 24, thereby to provide the outputs Se' and Si', respectively. Meanwhile, the row signal line 1 is connected by means of the MOS transistors d1 to only the column signal line 126 and 130 out of the column signal lines 122 through 132, and no MOS transistors are connected from the row signal line 1 to the other output lines.

Since the coded numerical value information was assumed to be "0001", the row signal lines other than the row signal line 1 out of these row signal lines 0 through 9 become the high level, in view of the fact that at least one of the said predetermined MOS transistors d becomes conductive. Accordingly, the column signal lines 122 through 125, 127 through 129 and 132 which are not connected to the row signal line 1 by the MOS transistors d1 are all the low level. As a result, the segments other than the segments e' and i' in FIG. 4 are not driven and thus do not emit light. When the period mark is to be displayed, the input DP to the AND gate 28' is brought to the high level, whereby the outputs S'e from an inverting amplifier 27 is brought to the low level, thereby to enable the segment to emit light.

FIG. 12 is a block diagram of a desk top electronic calculator of another embodiment to be embodied in the FIG. 1 calculator, which includes a block diagram of a display as modified in comparison to with that of the FIG. 8 embodiment. Thus, illustration of FIG. 12 is similar to that of FIG. 8. Therefore, the same reference characters are used to designate the same portions as those in FIG. 8. In the following, only different portions in the FIG. 12 embodiment will be described, while description of the same portions will be omitted. In the FIG. 12 embodiment, the coded numerical value information signal from the retaining circuit 1 is applied to a first signal converting circuit 2 and a third signal converting circuit 3'. The first signal converting circuit 2 is responsive to the said coded numerical value information signal to convert it to a first set of segment selective signals for allowing for selective light emission from the segments to selectively constitute a configuration of the numerical characters of the Arabic numerals, which segment selecting signals are applied to the first display DIS1. Quite similarly, the third signal converting circuit 3' is also responsive to the said coded numerical value information signal to convert it into a second set of segment selecting signals to selectively enable the segments to emit light so as to constitute a configuration of the numeral characters of the Arabian language numerals, which segment selecting signals are applied to the second display DIS2. The third signal converting circuit 3' will be described subsequently with reference to FIG. 13. In the present embodiment, a switch 37 is interconnected between the first and the third signal converting circuit in the same manner as the switch EXS in FIG. 11. The switch 37 is turned to the right side P1 as viewed in the figure when the display DIS1 is to be enabled, turned to the left side P3 as viewed in the figure when the display DIS2 is to be enabled, and placed in the neutral position P2 when both of the displays DIS1 and DIS2 are to be enabled simultaneously.

Referring to FIG. 13, the coded numeral value information signal consituted of the four-bit structure obtainable from the retaining circuit 1 in FIG. 12 is applied to the respective column signal lines 211', 213', 215' and 217', respectively, and further through inverters 41', 42', 43' and 44' to the respective column signal lines 212', 214', 216' and 218', respectively. The row signal lines 0' through 9' are connected to the row level voltage source through resistors, as similar to the row signal lines 0 through 9 in FIGS. 8 and 11. MOS transistors d are connected between the row signal lines 0' through 9' and the column signal lines 211' through 219', which MOS transistors are disposed in exactly the same manner as that in FIG. 8 and therefore are designated by the same reference characters d as that in FIG. 8. On the other hand, another set of MOS transistors d1 are connected between the row signal lines 0' through 9' and the column signal lines 220 through 230, which MOS transistors are disposed in exactly the same manner as that in FIG. 11 and are designated by the same reference characters d1 as that in FIGS. 8 and 11. Quite similarly, an AND gate 45' is employed for the purpose of displaying the period mark. It is to be noted that the column signal line 219' is connected via an inverter IV to the low level voltage source and the contact 37a of the switch 37. The contact 37c of the switch 37 is grounded or connected to the high level voltage source. Accordingly, if and when the sliding member 37c is caused to contact the contact 37a, the output from the inverter IV becomes the low level, which is applied to the column signal line 219', thereby to disable the display. The contact 37b is similarly connected to the first signal converting circuit 2.

Now, description will be made of the operation of the FIG. 13 circuit arrangement. First, let it be assumed that the switch 37 is placed in the neutral position. Assuming that the contents of the coded numerical value information signal are the value of the numeral one, the coded numerical value information signal representative of the numeral one is applied to the first signal converting circuit 2, which is responsive to the said signal to provide the low level output at the output terminals Sb and Sc. Therefore, the segments b and c in each digit position in the display DIS1 are selected to be ready for light emission therefrom. Further assuming that the same numeral one is the first digit of the multi-digit numerical value information, the timing signal T1 is provided by the digit timing signal generator 4 and is applied to the right most digit position of the display DIS1. As a result, the segments b and c of only the said right most digit position in the display DIS1 are caused to emit light, thereby to display a configuration of the numeral character of the Arabic numeral 1.

On the other hand, the said coded multi-digit numerical value information signal is also applied to the third signal converting circuit 3'. Since the coded numerical value information signal obtainable from the retaining circuit 1 at that timing is "0001", The low level output is applied to the column signal lines 211', 213' and 215', while the high level output is applied to the column signal line 217'. On the other hand, the low level output is applied to the inverters 41', 42' and 43', while the high level output is applied to the inverter 44', so that the output from the inverters 41', 42' and 43' becomes the high level, while the output from the inverter 44' becomes the low level. As a result, the column signal lines 212', 214' and 216' are forced to the low level, while the column signal line 218' is forced to the high level. It is seen that the MOS transistors d are connected between the row signal line 1' and the column signal lines 212', 214' , 216' and 217' in the manner as shown in FIG. 9 and, therefore, these MOS transistors d receive the low level input at the gate electrode thereof. Accordingly, these MOS transistors all become conductive. Meanwhile, if and when the display DIS2 is to be enabled, i.e. the switch 37 has been turned to the right side or placed in the neutral position, the column signal line 219' is supplied with the high level. Therefore, the MOS transistor d' connected between the row signal line 1' and the column signal line 219' also receives the low level input at the gate electrode thereof, whereby the said MOS transistor d' becomes conductive. As a result, the row signal line 1' is forced to the low level. The MOS transistors d1 are connected between the row signal line 1' and the column signal lines 224' and 228' in the manner shown in FIG. 10, so that when the row signal line 1' is the low level, these MOS transistors d1 become conductive because of the low level at the gate electrode thereof, with the result that the column signal lines 224' and 228' become the high level. The high level signal in these column signal lines 224' and 228' are applied through a respective inverting amplifiers 50' and 54' to the display DIS2, thereby to drive the segments e' and i'. When the timing signal T1 is obtained from the timing signal generator in such a situation for the abovementioned reasons, the segments e' and i' in the right most digit position of the display DIS2 emit light, thereby to display a configuration of the numeral character of the Arabian language numeral 1. When the coded numerical value information signal is "0001" representative of the value of the numeral one, the row signal lines 0' and 2' through 9' all are the high level, and accordingly the column signal lines other than those 224' and 228' out of the column signal lines 220' through 230' are all the low level. Therefore, the segments other than those e' and i' in the display DIS2 are not driven and do not emit light. Thus, display is made of the numerical value information by the numeral characters of the Arabic numerals and the Arabian language numerals in the displays DIS1 and DIS2, respectively. Where the period mark is to be displayed, the input DP to the AND gate 45' is made the high level. Accordingly, the output S1' becomes the low level and the segment 1' in FIG. 4 is caused to emit light. In the foregoing, explanation was made of the case where the switch 37 is placed in the neutral position. However, it is appreciated that if and when the switch 37 is turned to the right side the dispaly DIS1 is enabled to display the numeral characters of the Arabic numerals, and if and when the switch 37 is turned to the left side, the display DIS2 is enabled to display the numeral characters of the Arabian language numerals.

As seen from the foregoing description, the FIGS. 5 and 12 embodiments each comprise the first display capable of displaying multi-digit numerical value information by a first kind of group of numeral characters, say the Arabic numerals, and the second display capable of displaying the same multi-digit numerical value information by a second kind of group of numeral characters, say the Arabian language numerals, and selective display is made of the said multi-digit numerical value information by either or both of the first and second different kinds of groups of numeral characters.

FIG. 14 is a perspective view of a desk top electronic calculator of another embodiment of the present invention. The FIG. 14 calculator, as different from the FIG. 1 embodiment, comprises a single display DIS3. The display DIS3 comprises a plurality of digit display tubes each positioned in the respective digit display position and comprising an arrangement of a plurality of a segments a" through m" arranged in the manner as shown in FIG. 15. It is pointed out that these segments are shaped and arranged such that selective light emission from these segments can display selectively a configuration of numeral characters of the Arabic numerals or the Arabian language numerals in the common display position. Such selection of the kinds of the numeral characters, i.e. the Arabic numerals and the Arabian language numerals, can be effected by the turning of the switch EXS'. More specifically, according to the embodiment shown, numeral characters of the Arabic numerals are displayed when the switch EXS' is turned to the first position P3 and the numeral characters of the Arabian language numerals are displayed when the switch EXS' is turned to the second position P4. The other structural features of the FIG. 14 calculator are the same as those of the FIG. 1 calculator.

As briefly described in the foregoing, the display tube incorporated in the display DIS3 of the FIG. 14 embodiment and comprising an arrangement of the segments as shown in FIG. 15 is capable of displaying selectively either of two kinds of numeral characters, the Arabic numerals and the Arabian language numerals. Table 3 shows a relation between the Arabic numerals

and the segments in FIG. 15 to be selected to display a configuration of the respective Arabic numeral characters and a relation between the Arabian language numerals and the segments in FIG. 15 to be selected to display a configuration of the respective Arabian language numerals. Referring to Table 3, the segments to be selected to display the respective numeral characters are shown in the circle mark. For example, the numeral character of the Arabic numeral one, i.e. "1" is to be displayed, the segments e" and j" are caused to emit light, and if and when the numeral characters of the Arabic numeral two, i.e. "2" is to be displayed, the segments a", c", f", h" and l" are caused to emit light. On the other hand, the numeral character of the Arabian language numeral one, i.e. " " is to be displayed, the segments e" and j" are caused to emit light, and if and when the numeral characters of the Arabian language numeral two, i.e. " " is to be displayed, the segments c", e" and j" are caused to emit light.

FIG. 16 is a block diagram of the FIG. 14 calculator, which employs a further embodiment of the display of the present invention. As seen from the figures, the FIG. 16 block diagram is similar to the FIG. 5 block diagram. Therefore, in the following only different portions in the FIG. 16 block diagram will be described in detail. In the embodiment shown, the coded numerical value information signal is applied from the retaining circuit 1 to the signal converting circuit 3", which is responsive to the said numerical value information signal to convert it to a set of segment selecting signals for allowing for selective light emission from the segments to selectively constitute either a configuration of numeral characters of the Arabic numerals or a configuration of the numeral characters of the Arabian language numerals. Whether the signal converting circuit 3" provides the segment selecting signals for allowing for display of a configuration of the numeral characters of the Arabic numerals or the segments selecting signals for allowing for display of a configuration of the numeral characters of the Arabian language numerals is determined by the turning of the said switch EXS'.

FIG. 17 is a schematic diagram of the signal converting circuit 3" in FIG. 16, including a connection diagram of the switch EXS'. The column signal lines 311, 312, 313 and 314 are supplied with the coded numerical value information signal constituted of four-bits weighted of "1", "2", "4" and "8", respectively, and the column signal lines 315, 316, 317 and 318 are supplied with, after inverted by inverters 320, 321, 322 and 323, respectively, the said coded numerical value information signal of four-bits. The row signal lines 0 through 9 each corresponding to a value of one of the numerals 0 through 9 to be displayed are connected by means of MOS transistors d to predetermined ones of the column signal lines 311 through 318 in the manner shown in the figure. The connection of these MOS transistors d is exactly the same as the connection of the left half matrix in FIG. 8 and accordingly a specific connection of the MOS transistor d1 is also exactly the same as that shown in FIG. 9.

The row signal lines 0 through 9 are also connected by means of MOS transistors d1 to predetermined ones out of the column signal lines 331 through 342 and 331' through 342' in the manner shown in FIG. 17. A specific connection of the MOS transistor d1 is substantially the same as shown in FIG. 10. It is to be noted that the column signal lines 331 through 342 are also connected by means of the MOS transistors d0 to the row signal line 343 and the column signal lines 331' through 342 are connected through an inverter 344 and by means of MOS transistors d0 to the column signal line 343. A specific connection of the MOS transistor d0 is shown in FIG. 18. The column signal lines 331 through 342 are connected to the respective one input of AND gates 350 through 361, respectively, and the column signal lines 331' through 342' are connected to the respective other input of AND gates 350 through 361, respectively. The outputs through inverters 450 through 461 from the AND gates 350 through 361 are withdrawn as outputs Sa" through Sl" for selectively driving the segments a" through l", respectively, of the segment arragement shown in FIG. 15.

The column signal line 319 is connected to one input to the AND gate 362 and the other input to the AND gate 362 is connected to receive the signal DP for display of the period mark. The output from the AND gate 362 is inverted by inverting amplifier 462, and accordingly utilized as the signal Sm" for display of the period mark.

Referring now to FIG. 17, the operation of the embodiment shown will be described. If and when the coded numerical value information is to be displayed by the display DIS, the column signal line 319 is forced to the high level, and if and when numeral characters of the Arabic numerals are to be displayed by the display DIS as a result of selective turning of the switch EXS', the row signal line 343 is forced to the high level, while if and when the numeral characters of the Arabian language numerals are to be displayed by the display DIS, the row signal line 343 is forced to the low level.

First consider the case where the row signal line 343 is forced to the high level to display the numeral characters of the Arabic numerals. When the row signal line 343 is forced to the high level, the input to the gate electrode of the MOS transistors d0 connected to the column signal lines 331 through 342 becomes the high level, and therefore these MOS transistors d0 do not become conductive, but the input to the gate electrode of the MOS transistors d0 connected to the column signal lines 331' through 342' becomes the low level because of the inversion to the low level by means of the inverter 344. Accordingly, the MOS transistors d0 connected to the column signal lines 331' through 342' all become conductive, whereby the column signal lines 331' through 342' are all forced to the high level. The column signal lines 331 through 342 remain the low level in that situation. It is appreciated that in such a situation the right side input as viewed in the figure to the AND gates 50 through 61 all become the high level. Now assume that the coded numerical value information "0010" representative of the value of the numeral two is provided by the retaining circuit 1. Accordingly, the column signal lines 311, 313 and 314 becomes the low level, while the column signal line 312 becomes the high level, whereas the column signal lines 315, 317 and 318 become the high level, and the column signal line 316 becomes the low level. In such situation, the column signal lines 315, 312 and 317 are the high level and therefore the input to the gate electrode of the MOS transistors d connected to the row signal line 2 are all the high level and accordingly these MOS transistors d do not become conductive. As a result, the row signal line 2 is the low level. As for the other row signal lines 0, 1, 3 through 9, at least one of the MOS transistors d connected to these row signal lines receives the low level at the gate electrode thereof, so that the said transistor d becomes conductive, whereby the row signal lines 0, 1, 3 through 9 all become the low level. Since the row signal line is the low level, only the MOS transistor d1 connected to the row signal line 2 become conductive. As a result, the column signal lines 331, 333, 333', 335', 336 338, 340', and 342 become the high level. Of these column signal lines, the column signal lines 333', 335', and 340' have become the high level because of the low level output from the inverter 344. Therefore, the column signal lines 331, 333, 336, 338 and 342 are brought to the high level by the low level at the row signal line 2, and the high level in these column signal lines 331, 333, 336, 338 and 342 are applied to the left side input, as viewed in the figure, of the AND gates 350, 352, 355, 357 and 361, whereby the outputs from the AND gates 350, 352, 355, 357 and 361 become the high level and the outputs Sa", Sc", Sf", Sh" and Sl" from the inverting amplifiers 450, 452, 455, 457 and 461 become the low level, with the result that the segments a", c", f" and h" and l" are enabled in each digit position of the display DIS3. Since in such situation the row signal lines 0, 1, 3 through 9 other than row signal line 2 are all the high level, the output from the AND gates other than the AND gates 350, 352, 355, 357 and 361 do not become the high level, whereby the segment other than the segments a", c", f", h" and l" are not enabled. When the period mark is to be displayed, the input DP to the AND gate 362 is brought to the high level, whereby the signal Sm" is provided.

In case where the numeral characters of the Arabian language numerals are to be displayed, the switch EXS' is turned so that the row signal line 343 is brought to the low level. At that time the MOS transistors d0 connected to the column signal lines 331 through 342 become conductive, since the gate input thereto is the low level, and these column signal lines 331 through 342 become the high level. Since the output from the inverter 344 is the high level at that time, the MOS transistors d0 connected to the column signal lines 331 through 342 receive the high level at the gate thereof and do not become conductive. Therefore, the potential of the column signal lines 331' through 342' is the low level, so far as this situation is maintained. Therefore, in such situation the input at the left side, as viewed in the figure, to the AND gates 350 through 361 have become the high level. Then, assuming that the coded numerical value information signal of "0010" representative of the value of the numeral two is provided from the retaining circuit 1 to display the numeral character of the Arabian language numeral two, for example, only the row signal line 2 becomes the low level, while the remaining the row signal lines 0, 1, 3 through 9 are the high level, in the same manner as mentioned above. Accordingly, the column signal lines 331, 332, 333', 335', 336, 338, 340 and 342 become the high level. However, of these lines, the column signal lines 331, 333, 336, 338 and 342 have already become the high level, inasmuch as the column signal line 343 was brought to the low level. Since the column signal lines 333', 335' and 340' have become the high level, the input at the right side to the AND gate 352, 354 and 359 also become the high level, whereby the outputs from the AND gates 352, 354, and 359 become the high level. Accordingly, the outputs Sc", Se" and Sj" from the signal converting circuit 3" become the low level, thereby to drive the display segments c", e", j" in each digit position of the display DIS3. Assuming that the numeral character represented by the coded numerical value information signal "0010" is to be displayed in the right most digit position of the display DIS3, the timing signal generator 4 provides the digit timing signal T1 at that timing, which is applied to the right most digit position of the display DIS3. As a result, only the display segments c", e" and j" of the right most digit position of the display DIS3 are caused to emit light. This light emission from the display segments c", e", and j" represents a configuration of the numeral characters of the Arabian language numeral two, i.e. " ", as seen from FIG. 15. Indication of the period mark is effected by bringing the input DP to the AND gate 362 to the high level.

As seen from the foregoing description, assuming that the coded numerical value information signal is that which corresponds to the value of the numeral two, only the row signal line 2 is brought to the low level, whereby the column signal lines 331, 333, 336, 338 and 342 are brought to the high level, and the column signal lines 333', 335' and 340' are also brought to the high level. The high level in the column signal lines 331, 333, 336, 338 and 342 constitutes a signal for displaying the numeral character of the Arabic numeral two in the display unit as shown in FIG. 15, while the high level in the column signal lines 333', 335' and 340' constitutes a signal for displaying the numeral character of the Arabian language numeral two in the display unit in FIG. 15. It is pointed out that these two kinds of the signals for the different kinds of the numeral characters are obtained simultaneously by conversion of the coded numerical value information on signal obtainable from the register 10, and thus from the retaining circuit 1. The selection signal for selecting the signal for the Arabic numerals is obtained by turning the switch EXS', thereby to bring the row signal line 343 to the high level. More specifically, when the switch EXS' is turned to bring the row signal line 343 to the high level, the signal for displaying the numeral characters of the Arabic numerals, i.e. the high level in the column signal lines 331, 333, 336, 338 and 342, in case of the numeral two, are withdrawn by way of the high level outputs from the AND gates 350, 352, 355, 357 and 361, whereby the numeral character of the Arabic numeral two, i.e., " " is displayed by the display unit as shown in FIG. 15. On the other hand, the selecting signal for selecting the signal representative of the Arabian language numerals is obtained by turning the switch EXS to bring the row signal line 343 to the low level. More specifically, when the switch EXS' is turned to bring the row signal line 343 to the low level, the signals for displaying the numeral characters of the Arabian language numerals, i.e. the high level in the column signal lines 333', 335' and 340', in case of the numeral two, are withdrawn as the high level outputs from the AND gates 352, 354, and 359, whereby the numeral characters of the Arabian language numeral two, i.e. a configuration of " " is displayed by the display unit as shown in FIG. 15. The display unit is responsive to the signal for displaying the Arabic numerals and the signal for displaying the Arabian language numerals obtainable from the signal converting circuit 3' as well as the display mode designating output obtained from the switch EXS' to selectively display a configuration of one of the numeral characters of either the Arabic numerals or the Arabian language numerals.

As seen from the foregoing description, the FIG. 16 embodiment comprises a single display having a plurality of digit display positions each capable of displaying selectively one of numerals 0 through 9 by first and second different kinds of groups of numeral characters, say Arabic numerals and the Arabian language numerals. respectively, thereby to selectively display multi-digit numerical value information by these different kinds of groups of numeral characters. According to the present embodiment, the display may be made simple in structure and hence may be made small sized and yet can be manufactured with low cost.

Although in the foregoing the present invention was described as embodied in a small sized electronic calculator, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation. As readily understood by those skilled in the art, the present invention can be advantageously embodied in any other types of electronic data processing machines such as computer terminal units, electronic cash registers, and the like. The present invention is also applicable to a display of numerical value information by any other kinds of groups of numeral characters such as Roman numerals, Chinese character numerals, and the like. Thus, it is clearly understood by those skilled in the art that various modifications and changes of the present invention may be made without departing from the spirit of the present invention. It is, therefore, intended that the spirit and the scope of the present invention be limited only by the terms of the appended claims.