Time Division Digital Multiplexer Apparatus

The present invention relates broadly to a data transmission system, and in particular to a synchronous time division digital multiplexer apparatus for use with a modem transmission system.

In the prior art, the transmission of digital data over telephone lines by frequency modulations-demodulation techniques is well known. Frequency modulation techniques in which a carrier wave is shifted between two frequencies during successive modulation periods are commonly called frequency shift keying frequency shift keying systems. In these prior art systems, the carrier wave is generated at the transmitter by means of well known analog techniques which utilizes resistors, inductors, etc. Analog carrier wave generators of such prior art transmitters are unstable to some degree which causes unwanted shifts in the transmitted carrier frequency. The stability of such analog circuits may be improved to some extent by the use of crystal controlled oscillators and temperature compensating devices. However, such devices are not only expensive, but do not completely eliminate the instability problem. Furthermore, the close harmonics of the carrier frequencies, for example, third and fifth, are difficult to remove and may result in errors in the demodulated signal.

The present invention utilizes low speed time division digital multiplexer which is adapted to accept thirty parallel inputs that are sequentially sampled and converted to serial data having non-return to zero (NRZ) characteristics. Frequency shift keying (FSK) is utilized to modulate the obtained serial data with a sinusoidal audio carrier. Simultaneously, the system clock is automatically modulated by means of frequency shift keying with another sinusoidal audio carrier, or manually by a repetitive frame synchronization pulse entered by an operator. The data carrier and clock carrier are linearly combined, bandpass filtered, and level adjusted to be compatible with transmission in voice-grade telephone circuit in the simplex mode.

It is one object of the present invention, therefore, to provide an improved time division digital multiplexer apparatus utilizing a parallel to serial data conversion to permit the use of low speed time division multiplexing.

It is another object of the invention to provide an improved time division digital multiplexer apparatus wherein a digital to analog conversion is affected to permit the use of modems in data transmission.

It is still another object of the invention to provide an improved time division digital multiplexer apparatus utilizing frequency shift keying and repetitive frame synchronization signal to provide data transmission over voice-grade telephone circuits to a remote location.

These and other advantages, features and objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiment in the accompanying drawings.

FIG. 1a is a block diagram of the delay equalization and frame synchronization in accordance with the present invention,

FIG. 1b is a graphical illustration of the signal waveforms which are present at the respective designated portions of the apparatus shown in FIG. 1a, and,

FIG. 2 is a schematic diagram of the digital to analog converter utilized in the present invention.

Referring now to FIG. 1a, there is shown a synchronous time division digital multiplexer apparatus utilizing a system clock 10 for repetitive frame synchronization in data transmission betweeen modem units at remote locations with respect to each other. The multiplexer and send modem unit 12 accepts a maximum of thirty parallel inputs which may be interfaced with TTL level inputs and/or high level (to + 48V) inputs. The inputs are sequentially sampled in the time domain and converted to TTL level non-return-to-zero (NRZ) serial data. The serial data is used to modulate (frequency shift key - FSK) a sinusoidal audio carrier. Simultaneously, another sinusoidal audio carrier from the system clock unit 10 is FSK modulated by a data enter pulse at the operator's discretion by switch, S2 or, alternatively, the clock carrier may automatically and periodically be modulated by a repetitive frame synchronization pulse. Within the modem portion of unit 12, the data carrier and clock carrier are linearly combined, bandpass filtered, and level adjusted for compatibility with dedicated military or commercial voice-grade transmission media, simplex mode. The send modem output level is adjustable to -3 dbm maximum.

The receive modem, which is part of the demultiplexer and receive modem 14, has a sensitivity threshold of -30 dbm and, isolates the previously combined data and clock carriers, and then performs conventional FM demodulation. The receive Modem outputs include NRZ serial data, frame synchronization pulses (when selected by the operator), and fully synchronous, phase-locked system clock. The NRZ serial data is distributed via buffer stages to TTL type 7474 latches 16 where it is applied simultaneously to all latch data inputs. Serial to parallel conversion is accomplished by strobing the 7474 clock inputs in time sequence, each strobe coinciding in time with the serial data channel to be decoded. In this manner, each of the thirty latch outputs is a TTL-level reproduction of the digital input to the corresponding channel at the multiplexer input. Latch outputs are buffered in a high level interface compatible with other TTL or high level loads to + 48V.

The delay equalization and frame synchronization is achieved by automatically disabling the strobe generator 18 (TTL 74154) at the end of frame (EOF) time. The demultiplexer remains passive, with no updating of stored data, until a synchronizing (or Data Enter) pulse is generated at the send end and recovered at the receive end. This pulse is conditioned by means of a single adjustment to enable resumption of strobe generation at the precise time required to compensate for clock/data delay differences.

The multiplexer system clock is derived from the voltage controlled oscillator output of a type 560 phase lock loop (PLL) in the receive modem. This phase lock loop is locked in frequency and phase to the system clock in the send terminal and coherently tracks inadvertent frequency drift as well as desired FSK modulation. The phase track loop tracking capability permits use of an economical, noncritical system clock oscillator with no degradation in system reliability.

There is shown in FIG. 1b a timing diagram which represents the waveforms that are present in FIG. 1a at the point designated by the corresponding character. In FIG. 1b, waveform (A) represents the fixed duration sync (Reset) pulse applied to the TTL type 7493 counters at the send end. This pulse is effectively reproduced as waveform (E) in the following manner: The system clock frequency, while not critical, is adjusted to 600 Hz. Two 7493 counters are cascaded, providing output frequencies of 300 Hz (not used), 150 Hz (not used), 75 Hz (2.sup.0), 37.5 Hz (2.sup.1), 18.75 Hz (2.sup.2), 9.375 (2.sup.3), and 4.6875 Hz (2.sup.4). At the end of frame (EOF) the 2.sup.4 signal transitions to the low state, initiating the fixed reset pulse in the 74121. This pulse disables the counters, making them passive to the continuing clock. When S2 (DATA ENTER) is momentarily depressed, a 7401 NAND gate, open collector, is enabled, passing the reset pulses to the send Modem where it modulates the clock carrier. The receive Modem demodulates the clock carrier and shapes the pulse, producing waveform (B) in FIG. 1. The delay from (A) to (B) is a function of the combined delays inherent in the equipment and the transmission media propagation delay. The modems in FIG. 1a are to be collocated (back-to-back), thus eliminating media delay. Since the derived clock and system clock are phase locked, the 7493 counters at the demultiplexer have reached EOF (2.sup.4 transition to the low state) before pulse (B) appears. Waveform (D) is a composite produced by two NAND gates in a WIRE-OR configuration. The first positive transition of (D) is the inverted EOF transition, clocking the high level at 7474 latch DATA terminal into the latch Q terminal, initiating the positive transition of (E). Subsequently, (B) initiates (C) whose duration is adjustable. When (C) is inverted by the NAND gate, the trailing edge clocks the latch Q terminal back to the low state, enabling the 7493 counters to resume normal operation, fully synchronized with their send-end counterparts.

Turning now to FIG. 2, there is shown the digital to analog conversion (DAC) unit. Both the clock oscillator and the data oscillator perform DAC functions. The oscillator itself is a common Bridge-T sinusoidal oscillator, with frequency a function of the resistance R19 + R20. When the open collector output stage of the NAND gate is in the off state, the impedance seen looking into the collector is relatively large in comparison with the R20 impedance; oscillator frequency f.sub.o is then determined by both R19 and R20. When the NAND output is in the on state, R20 is effectively bypassed by the saturated bipolar transistor and the oscillator frequency shifts to f.sub.1 > f.sub.o.

Although the invention has been described with reference to a particular embodiment, it will be understood to those skilled in the art that the invention is capable of a variety of alternative embodiments within the spirit and scope of the appended claims.