US 4,107,667 AGrant
Dual Slope Analog-to-Digital Converter With Unique Counting Arrangement
Issue Date:1978-08-15
•33 Claims
•21 Drawing Sheets
Abstract
In a dual slope analog-to-digital converter, the conversion cycle is divided into three states; a first state in which the system is initialized by discharging an integration capacitor, a second state in which integration is performed with an analog voltage representing the measured parameter and a third state in which integration is performed with an analog reference voltage representing the full scale of the measured parameter. The duration of each state, derived from a counter, is selected according to the particular application in which the analog-to-digital converter is utilized. In one embodiment, each count is representative of a unit of the parameter being measured or a fraction thereof. The count or value which represents the commencement of the third state has a selected relationship to the minimum value of the measured parameter best suited for the particular application. The number of counts in the second state is selected to be equal to or a multiple of the desired full scale range of the parameter to be measured.
Metadata
Assignee
- Texas Instruments Incorporated
Inventor
- John W. Kronlage
Application Information
Application Number:US 7439008
Filing Date:1976-11-22
Priority Date:1976-11-22
Art Unit:236
Classifications
IPC:
H03K 1302H03K 1320G01K 700
Field of Search:
34032473347 M;347 NT;347 AD99 D362 AR;362 R;359
Patent Drawings (21 sheets)
Description
Background of the Invention
This invention relates to analog-to-digital converters, and more particularly, to an improved dual slope analog-to-digital converter.
Dual slope analog-to-digital converters divide the stages within a conversion sequence into three equal time periods of magnitude generally equal to the time required to count through all the states of a digital counter. The first time period is devoted to zeroing the system; the second time period is devoted to integration with the analog voltage, representing the measured parameter, switched into the circuit; and, the third time period devoted to integration with the analog reference voltage, representing full scale of the measured parameter, switched into the circuit. Conventionally, during the first time period, the storage element; i.e., a capacitor, is discharged to 0 volts; during the second and third time periods, the measured parameter voltage is compared to the full scale reference voltage and the results (represented by the counter value at a particular instant) latched in digital form which may be stored, displayed and/or utilized for some other desired purpose.
For most applications, however, complex decoding of the count value is required before the value can be utilized or displayed. Furthermore, where multiple scales (i.e., metric, English, etc.) are utilized, such complex decoding is required for each scale.
A further object of the invention is to provide an analog-to-digital converter which generates easily-decodeable results for use and/or display on multiple scales (i.e., metric, English, etc.).
It is another object of the invention to provide an analog-to-digital converter which is capable of being integrated as a semiconductor circuit utilizing I.sup.2 L techniques.
Still another object of the invention is to provide an analog-to-digital converter which is integratable on a single substrate with digital circuitry to provide a complete analog-to-digital system on a single semiconductor chip.
Yet another object of the invention is to provide an analog input stage for a portable, battery-operable digital thermometer.
Brief Description of the Invention
These and other objects are accomplished in accordance with the present invention in which the conversion cycle of a dual slope analog-to-digital converter is divided into three states which may be of different preselected duration; a first state in which the system is initialized by discharging an integration capacitor, a second state in which integration is performed with an analog voltage representing the measured parameter and a third state in which integration is performed with an analog reference voltage representing the full scale of the measured parameter. The duration of each state, derived from a counter, is selected according to the particular application in which the analog-to-digital converter is utilized. In a preferred embodiment, each count is representative of a unit of the parameter being measured or a fraction thereof. The counter value which represents the commencement of the third state is selected so that it bears a direct selected relationship to the minimum value of the measured parameter which is to be displayed or utilized. The count may be equal to the minimum value of the measured parameter or some convenient derivative thereof to provide a direct relationship between the counter value and the desired digital value which is to be utilized and/or displayed; the count may be zero but not necessarily so. The number of counts in the second state is selected to be equal to or a multiple of the desired full-scale range of the parameter to be measured. By having the counter value control the duration of each of the states, the same circuitry may be utilized to generate the measured parameter in different scales (i.e., metric, English, etc.) by selecting different counter values for each scale based upon the above criteria.
More particularly, one embodiment of a dual slope analog-to-digital converter, in accordance with the present invention, is utilized to provide a digital thermometer with a temperature display. The number of counts comprising the first state is selected to allow sufficient time for discharging the integration capacitor. The number of counts comprising the second state is selected to be equal to a multiple of the desired full-scale temperature range with each count being representative of a fraction (i.e., tenths) of a degree. The counter value, at the commencement of the third state, may be selected to be equal to the minimum value of the measured parameter or, where multiple scales are utilized, a convenient count which is common to the minimum value of the measured parameter for each of the scales. Multiple scales (i.e., .degree. C, .degree. F, .degree. K) are easily selectable by the particular counter values controlling the first, second and third states for each scale. A selection gate circuit may be provided to allow this count selection to be made by changing (i.e., grounding) input to the selection gate. This may be accomplished by a switch or a hardwired/open connection to an internal or external terminal. In one embodiment of the digital thermometer, the selection is made by a selection gate, the input of which is coupled to the display; the selection is made automatically depending upon the presence or absence of a hundreds digit in the display.
Brief Description of the Drawings
Still further objects and advantages of the invention will be apparent from the detailed description and claims when read in conjunction with the accompanying drawings, wherein:
FIGS. 1a - 1c, when assembled according to the composite of FIG. 1, illustrates a preferred embodiment of the present invention;
FIGS. 2a - 2p, when assembled according to the composite of FIG. 2, form a detailed circuit diagram of the digital thermometer of FIGS. 1a - 1c;
FIG. 3a is a circuit diagram of the latch circuits of FIGS. 2a - 2p;
FIG. 3b is a circuit diagram of the flip-flop circuits of FIGS. 2a - 2p; and
FIG. 4 is a circuit diagram of an alternate embodiment of the oscillator utilized in the analog-to-digital converter of the digital thermometer.
Detailed Description of the Preferred Embodiments
Referring then to the drawings, and in particular to FIGS. 1a - 1c, a unique digital thermometer is illustrated in which the present invention is embodied and comprises a novel feature thereof. The digital thermometer is integrated on a single semiconductor substrate, utilizing I.sup.2 L fabrication techniques, with the exception of a few external components; such as, a thermistor or other suitable temperature-sensitive device, LED or other suitable display elements, an integration capacitor and an analog input gain-setting resistor.
The digital thermometer is comprised of two sections; an analog section which measures and converts an analog signal representative of temperature to an appropriate digital signal and a digital section which stores, decodes and digitally displays the digital signal to provide a visible temperature reading.
The analog section is comprised of an analog-to-digital converter which utilizes dual slope integration. The analog-to-digital converter is able to reject unwanted components of signals such as 60-Hz pickup. A stable voltage reference V.sub.REF is provided to the analog-to-digital converter by voltage regulator 12, the output of which does not vary significantly under a wide range of conditions; such as, ambient temperature variations or variations in battery voltage supply (V.sub.CC). The voltage regulator 12, shown in greater detail in FIG. 2m, is described in detail and claimed in copending U.S. patent application, Ser. No. 737,134, for "Temperature-Compensated Voltage Regulator" by Stephen C. Kwan, filed on Oct. 29, 1976 and assigned to the assignee of the present invention. The reference voltage V.sub.REF (1.2 volts in this embodiment) is coupled to the positive (+) input of scaling operational amplifier 10 and reference operational amplifier 11.
The temperature is sensed by thermistor R.sub.T (which, in other embodiments, may be substituted for by light-sensitive devices; such as, photo resistors for light level measurement, or transducer devices for measurement of mechanical stress; such as, pressure or tension) which is coupled between the V.sub.A output of scaling operational amplifier 10 and the negative (-) input of amplifier 10.
Scaling amplifier 10 produces voltage V.sub.A which varies according to the temperature or other parameter being measured. Reference amplifier 11 has a constant resistance internal resistor R4 coupled between its output and its negative (-) input to provide voltage V.sub.B representing the full-scale value of the parameter being measured. Amplifiers 10 and 11 are illustrated in detail in the circuit diagram of FIG. 2i. Referring then to FIG. 2i, the base of transistor 343 provides the positive (+) input and the base of transistor 344 provides the negative (-) input of scaling amplifier 10; the base of transistor 345 provides the positive (+) input and the base of transistor 346 provides the negative (-) input of reference amplifier 11. Transistors 349 and 350, in essence, provide the output of amplifiers 10 and 11, respectively, to switch 13. Analog switch 13 allows either voltage V.sub.A output from amplifier 10 or voltage V.sub.B output from amplifier 11 to be applied by means of transistor 351 and resistor R.sub.0 to the negative (-) input of integrator 14. Switch 13, shown in FIG. 2j, is selectively enabled by switch driver 28 and operates to ground the collectors of either transistor 349 or transistor 350. The output of the amplifier with the non-grounded transistor will be transferred to integrator 14. Switch driver 28, which is comprised of NAND gates 352 and 353, receives selection signals E.sub.0 from three-state counter 26 via one-of-three decoder 27.
Integrator 14, which is illustrated in detail in FIG. 2e, produces a ramp voltage in one direction (e.g., positive) when the voltage V.sub.A is applied via resistor R.sub.0 to the negative (-) input and produces a ramp voltage in the opposite (e.g., negative) direction when the voltage V.sub.B is applied via resistor R.sub.0 to the negative (-) input. An integration capacitor C.sub.0 is connected between output 812 of integrator 14 (at terminal 811) and its negative (-) input (at terminal 810) provided by the base of transistor 813. The base of transistor 814 provides the positive (+) input of integrator 14. The output 812 of integrator 14 is coupled to the positive (+) input provided by the base of transistor 151 of analog comparator 15 shown in detail in FIG. 2f.
The negative (-) input of comparator 15, provided by the base of transistor 153, is coupled to receive V.sub.REF. Comparator 15 produces a logical transition at output 154 when the input signal at the base of transistor 151 crosses the threshold in either direction (positive to negative or negative to positive). Detection of this transition by isolated (non-current injected) NAND gate 156 trips comparator latch 16 which stores the information that the transition has occurred. Comparator latch 16 is comprised of cross-coupled NAND gates 785 and 786.
The output of comparator 15 is selectively fed back to the negative (-) input of integrator 14 by means of switch 29. Switch 29, illustrated in detail in FIG. 2j, is enabled by NAND gates 354 of switch driver 28 in a similar manner to switch 13 in order to discharge capacitor C.sub.0 at the appropriate time during each analog-to-digital conversion cycle.
Input signal scaling of the analog-to-digital converter is provided through selection of input resistors RT and R.sub.1 -R.sub.9. RT is the external thermistor or other condition-sensing device coupled between terminals 347 and 348. R.sub.1 is an external analog input gain-setting resistor coupled between terminal 347 and ground; the remaining resistors R.sub.2 -R.sub.9 may be and are preferably integrated on the semiconductor substrate to avoid excessive external components.
The digital section of the digital thermometer is comprised of current injection logic (I.sup.2 L) which operates from the same voltage supply as the analog section described above. All of the gates (represented by triangles in FIGS. 2a-2p) are NAND gates; the collector outputs (represented by circles at the point of the triangles) are shown for each gate.
The digital section includes a ring oscillator 17 which produces clock pulses (CLK) for the system and three scanning signals (I, II and III) and is shown in detail in FIGS. 2a and 2e.
Referring then to FIGS. 2a and 2e, ring oscillator 17 is comprised of a plurality of cascaded NAND gates 501-509 coupled in a ring configuration to achieve a plurality of astable states. Thus, the output of each of the gates 501-508 is respectively connected to the input of the next gate 502-509 in the cascade and the output of gate 509 is coupled to the input of the gate 501 to complete the ring configuration. The system clock which typically runs at 20 kHz, is taken from the outputs of NAND gates R.sub.1, R.sub.3, R.sub.5 and R.sub.7 which are NAND'd by NAND gate 810 according to the equation CK = R.sub.1 .multidot.R.sub.3 .multidot.R.sub.5 .multidot.R.sub.7. The output of NAND gate 810 is applied to the base of driver transistor 524 and by the collector of transistor 524 to flip-flop circuit 801. Flip-flop circuit 801 provides the clock signal for the rest of the digital circuitry.
A unique feature of oscillator circuit 17 is that provision is made for frequency adjustments by lead pattern selection in the fabrication process to provide discrete variations in oscillator injector current levels. Lowering injector currents increases delay time between each of the astable states provided by NAND gates 501-509, and, therefore, results in a lower clock frequency. In the illustrated embodiment, seventy-two discrete adjustments in frequency are available. The ranges are: MAX I.sub.LOW INJ = 3/13 I.sub.HIGH INJ ; MIN I.sub.LOW INJ = 1/24 .times. 1/13 I.sub.HIGH INJ (i.e., 3 MAX to 1/24 MIN) where: I.sub.HIGH INJ is the injector current of the I.sup.2 L gates in the rest of the digital circuitry of the system, and I.sub.LOW INJ is the injector current of the I.sup.2 L gates in the ring oscillator chain. These adjustments can best be understood from the following description of the current biasing utilized in the digital thermometer. I.sup.2 L gate 528 is comprised of a 25-collector transistor connected as a current sink. The injector of transistor 528 is biased from the main system current injector 900 (shown in FIG. 2n), which provides, for example, 10 .mu.A per gate. Collector 804 is utilized to sink current and the other 24 collectors 805 are selectively utilized in the feedback connection to the input of gate 528. The single sink collector 804 will sink from 1/24th of the 10 .mu.A (with all collectors 805 connected in the feedback) to 10 .mu.A (with only one collector 805 connected in the feedback).
The parallel connection of transistors 525 and 526 provides eight collectors, each biased at 1/24th of 10 .mu.A to 10 .mu.A. Transistor 527, a high-gain substrate PNP, is utilized to compensate for the low-gain of transistors 525 and 526 by providing a path for their base current to ground.
In the illustrated embodiment, three of the eight collectors of transistor 526 are coupled together at 525 to provide drive current A to drive the injectors of the nine I.sup.2 L gates 501-509 comprising the ring oscillator and NAND gate 810. Thus, the injector current, realized by gate 528, undergoes division by 24, multiplication by 3 and division by 10; this is the current at which ring oscillator gates 501-509 are biased. The factors 24 and 3 are adjustable in integral steps making a division ratio of 1/24 to 3 possible by selective connection in the fabrication process of the collectors of transistors 525, 526 and 527, as required.
In the digital thermometer, adjustable oscillator frequency is important to optimize the circuit for maximum sensitivity and accuracy and for compensation of the circuit for inaccuracies in device parameters which are process dependent, and not completely and accurately calculable, and thus, not under direct control. This technique, along with its obvious modifications, namely, varying the number of collectors on both the transistor of gate 528 and parallel transistors 525 and 526, is considered broader in application than the digital thermometer; it is applicable to all circuits which utilize an I.sup.2 L ring oscillator that is integrated on the same substrate as other I.sup.2 L circuitry, the oscillator being of low cost and yet adjustable within a high degree of accuracy.
In the embodiment of the ring oscillator illustrated in FIGS. 2a and 2e, the clock signal rate is reduced to about 2 kHz by flip-flops 201-204 comprising tenths decode counter 19a, shown in FIGS. 2b and 2c. The output of D.sub.0 counter flip-flop 204 is input to flip-flops 802 and 803 of oscillator circuit 17 to provide display multiplexing signals I, II and III which are applied to display multiplexer circuit 22a and digit drivers 25.
In an alternate embodiment, the multiplexing signals I, II and III are derived directly from the ring counter along with the system clock signal as illuatrated in FIG. 4. The resulting circuit operates as indicated in Table I below. The system clock signal is taken from R.sub.8, the output of gate 509, which provides a 50% duty cycle. Scan outputs I, II and III, for three-phase scanning, are derived as follows: I = R.sub.1 .multidot. R.sub.3 .multidot. R.sub.5 ; II = R.sub.2 .multidot. R.sub.4 .multidot. R.sub.6 and III = R.sub.0 .multidot. R.sub.2 .multidot. R.sub.7.
Dead time during states 2, 8 and 14 prevents "ghosting" of the display elements caused by overlapping digit multiplexing signals. The advantage of this embodiment is that the flip-flops 801-803 are eliminated and reduce the total surface area required for the oscillator circuit.
Ring oscillator 17 is coupled to a binary-coded-decimal counter having two-and-a-half stages, tenths-decade counter 19a, units-decade counter 19b and tens counter (flip-flop) 19c. The decade counters provide two functions: first, the counters are decoded at various stages to provide system timing, and second, the counters generate the digital equivalent of the sensor parameter value which, in the embodiment of the digital thermometer, is the digital equivalent of the temerature sensed by thermistor R.sub.T.
As previously discussed, comparator 15 produces a logical transition when the signal applied to the positive (+) input terminal thereof crosses the threshold voltage in either direction. Each time the transition occurs, comparator latch 16 is tripped, thereby storing the information that the transition has occurred. The output of comparator latch 16 is coupled to strobe generator 21. Strobe generator 21, illustrated in detail in FIG. 2f, also receives scanning signals I and II, and operates to strobe latches 20a-20c at the appropriate time to store the results of a present conversion from counters 19a-19c, respectively. The results of the conversion, stored in latches 20a-20c, is then decoded and displayed while the analog-to-digital converter portion of the system proceeds to make the next conversion. The unique counting scheme utilized in accordance with a novel feature of the digital thermometer, will now be described in detail.
Tenths decade counter 19a is comprised of flip-flop circuits 201-204, units decade counter 19b is comprised of flip-flop circuits 301-304 and tens counter 19c is comprised of flip-flop circuit 203, each of the flip-flop circuits being identical to the flip-flop circuit of FIG. 3b. The output A.sub.0 B.sub.0 C.sub.0 D.sub.0 of tenths counter 19a is decoded by means of tenths decode circuit 31a, shown in detail in FIGS. 2b and 2c; the output A.sub.1 B.sub.1 C.sub.1 D.sub.1 of units decade counter 19b is decoded by units decode circuit 31b, shown in detail in FIGS. 2c and 2d; and, the output A2 of tens counter (flip-flop) 19c, is decoded by tens decode circuit 21c, shown in detail in FIG. 2d.
Three-state counter 26 is utilized to generate three instantaneous states of the analog-to-digital converter. Counter 26, shown in detail in FIG. 2g, is comprised of flip-flop circuits 701 and 702, each of the flip-flop circuits being identical to the flip-flop circuit illustrated in FIG. 3b. The duration of the clock signal applied to counter 26 during any particular state is governed by clock gate circuitry 12 which is coupled to the clock (CK) input of flip-flops 701-702. The output of flip-flop circuits 701 and 702 are decoded by a one-of-three decoder circuit 27 to generate the three operating states T.sub.0, T.sub.1 and T.sub.2. During the time period T.sub.0, capacitor C.sub.0 is being discharged. The discharging of capacitor C.sub.0, as previously discussed, is accomplished by controlling switch 29 which is coupled to the T.sub.0 output of decoder circuit 27 by means of switch driver circuit 28. During the state T.sub.1, integration progresses with voltage V.sub.A being applied to the input to integrator 14, and during state T.sub.2, integration progresses with voltage V.sub.B being applied to the input to integrator 14. Switch 13, which controls the application of the voltage V.sub.A or V.sub.B to the input of integrator 14 is controlled by enable signal E.sub.0 which is derived from decoder 27 to control switch 13 to input voltage V.sub.A during state T.sub.1 and voltage V.sub.B during state T.sub.2.
Unlike standard dual slop analog-to-digital converters which divide the states within a conversion sequence into three equal time periods (i.e., T.sub.0 =T.sub.1 =T.sub.2), each being equal to the time required to count through all of the states of a digital counter, a counting scheme is utilized in the present system which is uniquely selected for each application. Firstly, the duration of each of the states T.sub.0, T.sub.1 and T.sub.2 is individually selected to best suit the application, and may encompass a different number of counts of the counter, and therefore, be of different duration from one another. Secondly, the minimum measured parameter value may be given other than by the number 000 in order to best suit the application. In order to best understand the count scheme, the following exemplary discussion will be limited to the digital thermometer application, and more particularly, to a digital fever thermometer having a range limited to 95.degree.-108.5.degree. F, or 35.degree.-42.5.degree. C.
Decade counters 19a-19c, which count to 200 states in the present embodiment, are capable of resolution to one part in 200; however, for thermometer application, each count is selected to represent 0.1.degree. and the resolution is restricted below 1 in 200 parts to accommodate both Fahrenheit and Centigrade units. Considerable reduction in circuit components results in utilizing the count ranges indicated in Table II below.
Two models may be provided utilizing the identical circuitry: a Fahrenheit model and a Centigrade model, or a single model incorporating the circuit may be provided which includes a selection switch to change from Fahrenheit to Centigrade scale. The change is accomplished by gate 33 which causes clock gating circuit 32 to alter the number of counts in the T.sub.1 mode in the respective models. Two passes through the counter states (a total of 400 counts) is made; count 050 on the second pass (actually the 250th clock pulse in a conversion cycle) is utilized for minimum scale in both .degree. F and .degree. C models. Temperature range and scale range are the same in both models considering absolute temperature. However, resolution is closer in Fahrenheit than in Centigrade by the ratio of 1.8 to 1.0; the resolution is acceptable in both models because the resolution of 0.1.degree. C is well within the requirements for a fever thermometer, and the convenience of relating one counter state to 0.1.degree. in both the .degree. F or .degree. C system is very desirable. Higher resolutions may, of course, be accomplished by increasing the total number of counts provided by the counter.
The system parameters, selected in TABLE I for a fever thermometer, namely, 050 count for minimum scale and 0.1.degree. increments for each count, also provide simplification of the circuitry which would otherwise be required for decoding the results of the conversion for a decimal display. The last two digits in the results of each conversion directly represent the desired last two digits to be displayed in both the Centigrade and Fahrenheit models; for example, count 050 represents 95.0.degree. F or 35.0.degree. C; 099 represents 99.9.degree. F or 39.9.degree. C; count of 125 represents 102.5.degree. F and 42.5.degree. C; etc. Another scheme which may be utilized in accordance with the invention would be to indicate the minimum temperature of 35.0.degree. C (which is equal to 95.0.degree. F) by a count of 350 (or 950 for .degree. F).
The above counting scheme is accomplished in the present embodiment by decoding selected state from counters 19a-19c in decoder circuits 31a-31c, and applying the decoded signals, along with an indication of the present state T.sub.0, T.sub.1 or T.sub.2 from decoder circuit 27, to clock gating circuit 32. Clock gating circuit 32, illustrated in detail in FIG. 2g, is comprised of NAND gates 771-779 which receive the above-indicated signals and provide a controlled clock signal to the clock (CK) input of latch circuits 701 and 702 comprising three-state counter 26. Overrange flip-flop 761, illustrated in detail in FIG. 2h, comprises overrange circuitry 30 which is capable of detecting an overrange condition in both .degree. C and .degree. F, overrange circuitry 30 being responsive to .degree. C/.degree. F selection circuitry 33 and to the decoded output from decoder circuits 31a-31c. Overrange circuitry 30 is arranged to provide a predetermined display (e.g., all digits except hundreds blanked) by the occurrance of an overrange condition. Tens encoder circuitry 34, also illustrated in detail in FIG. 2h, encodes the tens digit information derived from tens flip-flop 19c and stored in latch 20c and, the overrange information derived from flip-flop 761, to provide the binary coded decimal equivalent of the tens digit A.sub.2 B.sub.2 C.sub.2 D.sub.2. As previously mentioned, the tenths binary coded decimal digit A.sub.0 B.sub.0 C.sub.0 D.sub.0 is stored in tenths latches 20a and the binary coded units digit A.sub.1 B.sub.1 C.sub.1 D.sub.1 is stored in units latches 20b. The binary coded decimal bits comprising the tenths, units, and tens digits are then multiplexed by multiplex circuitry 22a which is controlled by scanning signals I, II and III from oscillator circuitry 17. Thus, during the period in which signal I is being applied to NAND gate 280, the binary coded decimal equivalent of the tenths digit is applied via gates 219-222 to the four inputs of decoder 22b; during the period in which signal II is being applied to NAND gate 380, the binary coded decimal equivalent of the units digit is applied via NAND gates 319-322 to the four inputs of decoder 22b; and, during the period in which state III is being applied to NAND gate 480, the tens binary coded decimal digit generated by encoder circuit 34 is applied via gates 419-422 to the four inputs of decoder circuit 22b.
Decoder circuit 22b, illustrated in detail in FIGS. 2l and 2p, is a 4-line binary coded decimal to one-of-ten line decoder.
The ten lines providing the output of decoder 22b are coupled to the inputs of one-of-ten to seven-segment decoder and segment driver circuit 23. Decoder circuits 22b and 23, in combination, therefore, convert one of the tenths, units or tens digits from binary coded decimal to seven segment format. The scanning signals I, II and III, which are applied to multiplexer circuit 22a, are also applied to digit drivers 25 comprised of driver transistor pairs 677, 687 and 697, respectively. Driver transistors 677, 687 and 697 provide digit driver signals DI, DII and DIII to drive the seven-segment display digits; such as, LED-type display digits 41-43, respectively. The two-segment hundredths digit 44 is driven directly by decoder circuit 67, and controlled by overrange circuitry 30. Thus, since the corresponding segments of the tenths, units, and tens digits 41-43 of display 40 are wired together at the LED anodes, for example, digit drivers 677-697 apply appropriate (ground) signals DI, DII and DIII to the cathodes to allow only the desired digit simultaneously selected by multiplexing circuit 22a to be energized both under control of scanning signals I, II and III.
The analog-to-digital conversion circuit is capable of making a continuous series of conversions, in the digital thermometer embodiment however, after the first conversion, thermistor R.sub.T is cooling down, and any reading derived therefrom would be erroneous; therefore, only the first conversion is accepted. Display latch 25a, illustrated in detail in FIGS. 2n and 2o, is initialized to keep the display off with low battery drain until a first conversion is received. When latch circuit 25a is tripped by comparator latch 16, the display is turned on and further conversions are rejected.
As previously mentioned, two models .degree. C and .degree. F are provided by the illustrated circuit. A single connection to transistor 880 of select gating circuit 33, shown in detail in FIG. 2h, converts the .degree. C range to the .degree. F range. Where a hardwire is utilized, in accordance with a unique feature of an embodiment of the invention, the selection is made automatically. .degree. C is automatically selected by connecting a three-digit display (tens, units and tenths) for a range of 35.degree. C-42.5.degree. C, and .degree. F is automatically selected when a four-digit display is connected to the circuit (hundredths, tends, units and tenths) for a range of 95.degree. F to 108.5.degree. F; the emitter of transistor 880 being coupled to the circuit terminal pins which receive hundredths segments 44 of display 40.
A unique feature of the above-described digital thermometer is that all of the component circuits: operational amplifiers 10 and 11, integrator 14 and analog comparator 15, as well as all of the digital circuitry, operate from a single low-voltage, low-power voltage supply. The single reference voltage utilized by all of the analog circuits is internally generated from the single low-power voltage supply. Where V.sub.CC is provided by, for example, a 5-volt (e.g., battery) supply, power consumption somewhat less than 50 mW for the entire circuit (not including the display drive power which varies according to the particular display utilized) is achievable.
Another unique feature of the digital thermometer is the provision made for calibration of the analog circuits. Calibration is accomplished by unique stepwise calibration circuit 35, illustrated in detail in FIG. 2j and FIG. 2m. Calibration circuit 35 makes use of binary weighted current sources which may be activated in any combination by selective connection to sets 103, 104 and 110 of calibration terminals provided at a convenient point on the integrated circuit chip and/or through pins on the integrated circuit package. Three types of calibration are provided in the present embodiment. Offset calibration circuit 35a adjusts the zero scale value of the unknown parameter; slope calibration circuit 35b adjusts the full scale of the unknown parameter; and final trim circuit 35c adjusts the assembled digital thermometer for correct measurements to a bath of known standard temperature. No external components are required for calibration, only grounded or open circuit calibration terminals or pins. The usual problems encountered by analog circuits with potentiometer calibration are avoided (ie, drift from the calibrated condition).
Transistors 105, 106 and 111-116 are connected to provide a current sufficient to bias transistors 121-125, 131-134 and 141-142 at a particular current level. Resistors 107 and 108 provide current feedback for circuit stabilization and a voltage drop which is related to downward ratioing of successive current sources in the binary weighted string. In this embodiment, eleven current sources are provided: five, 121-125, for offset calibration; two, 141-142, for final trim and four, 131-134, for slope calibration. Offset current sources 121-125 and trim current sources 141-142, are collectively biased from the base of transistor 112; slope current sources 131-134 are biased from the base of transistor 114.
Offset current source transistors 121-125 are of successively smaller geometry so that approximately equal emitter-base voltage drops, at currents successively smaller by a factor of two, are maintained. Similar geometry adjustments are made in transistors 131-134 and 141-142, respectively. An example of emitter current and resistance values for the eleven current sources for one embodiment of the digital thermometer are shown in TABLE III.
Current sources 121-125, 131-134 and 141-142 of each calibration set, are individually selectively activated by grounding the terminals of the various emitter resistors which are each connected to a pin of the external sets of pins 103, 104 and 110, respectively. Thus, for offset calibration, the five IC package pins coupled to the set of terminals 103 provide 32 discrete conditions from 0 to 310 .mu.A in 10-.mu.A steps. For calibration, the four IC package pins, coupled to terminals 110, allow 16 steps from 10 to 300 .mu.A in 20-.mu.A steps. For final trim, the two package pins, coupled to terminals 104, provide four steps, 0 to 30 .mu.A in 10-.mu.A steps. These parameters are, of course, pertinent only to the example of TABLE III; it is obvious that any number of variations may be provided resulting in any desired number of calibration steps and current variations per step.
Offset and trim currents are summed at the collectors of the selected ones of transistors 121-125 and 141-142, and flow through resistor R9; slope currents are summed at the collectors of the selected ones of transistors 131-134, and flow through resistor R8. The other terminal of resistors R8 and R9 are connected to a 1.2-volt reference voltage provided by V.sub.REF regulator 12. The respective voltage drops across resistors R8 and R9 are then adjusted voltages programmed by external pin connections; these adjustable voltage drops are then respectively applied to operational amplifier circuits 10 and 11 to effect the desired calibration adjustments.
As previously discussed, the above-described system incorporates an analog-digital integrated circuit fabricated on a single semiconductor substrate. The analog and digital circuitry, being comprised of bipolar devices, are fabricated utilizing standard I.sup.2 L technology. A P-type substrate having a P+ buried layer and an N-type epitaxial layer of between 0.2-0.3 mils (nominally about 0.25 mils) in thickness on the surface thereof is utilized.
The novel features of the invention have now been described in detail with respect to preferred embodiments thereof. Since it is obvious that many changes and modifications can be made in the above details without departing from the nature and spirit of the invention, it is understood that the invention is not to be limited to said details except as set forth in the appended claims.
Claims
What is claimed is:
1. A dual slope analog-to-digital converter comprising: (a) an integrator circuit having input and output means; (b) controllable switch means coupled to the input means of said integrator circuit for selectively switching an analog voltage representing a measured parameter and a reference voltage representing the full scale of said measured parameter alternately to the input means of said integrator circuit, said integrator circuit for producing a ramp voltage in one direction when the analog voltage representing the measured parameter is applied to the input means thereof and produces a ramp voltage in the opposite direction when the reference voltage is applied to the input means thereof; (c) comparator means coupled to the output means of said integrator circuit for producing a logic signal when the integrator ramp voltage crosses a predetermined threshold voltage; (d) oscillator means for generating a clock pulse signal; (e) decade counter means having a plurality of binary coded decimal stages coupled to said oscillator means for counting the pulses of said clock pulse signal and for generating a binary coded decimal output signal indicative of said count; (f) transfer means coupled to said comparator means and to said counter means for transferring the counter value from said counter means each time said logical signal is generated, said transferred counter value being indicative of the binary boded decimal representation of said measured parameter; and (g) control means coupled to said counter means and to said controllable switch means for controlling said controllable switch means to apply the analog voltage representing the measured parameter to said integrator means for a first predetermined time period represented by said counter means counting from a first counter value to a second counter value and for applying said reference voltage to the input means of said integrator circuit for a second predetermined time period represented by said counter means counting from said second counter value to a third counter value, said second counter value being selected so that a plurality of the lowest order digits thereof are equivalent to the respective lowest order digits of the minimum value of the parameter being measured, wherein each count represents a unit of the parameter being measured whereby the binary decimal equivalent of the lowest order digits of the parameter being measured are directly readable from respective stages of said decade counter means.
2. The analog-to-digital converter according to claim 1, wherein the lowest order digits of the minimum value of the parameter being measured are non-zero and wherein said second counter value is selected so that the respective lowest order digits thereof are equivalently non-zero.
3. The analog-to-digital converter according to claim 1, wherein the total number of counts comprising the duration of said first state is selected to be equal to the desired full-scale range of the parameter to be measured.
4. The analog-to-digital converter according to claim 1, wherein each count of said counter means represents a decimal fractional unit of the parameter being measured.
5. The analog-to-digital converter according to claim 1 including a second controllable switch means coupled to said integrator circuit for selectively discharging an integration capacitor of said integrator circuit, said control means including selector means coupled to the first and second controllable switches for activating said switches in a predetermined sequence, said selector means activating said second switch to discharge said integrator capacitor during the duration of a third time period represented by said counter means counting from said third counter value to said first counter value.
6. The analog-to-digital converter according to claim 1, wherein said transfer means includes controllable latch means having a control input coupled to said comparator means and data input means coupled to said counter means for storing the count of said counter means when triggered by said comparator means.
7. The analog-to-digital converter according to claim 1, wherein said control means includes decoder means coupled to said counter means, said decoder means being selectively responsive to said first, second and third counter values.
8. The analog-to-digital converter according to claim 7, wherein a plurality of sets of first, second and third counter values are decodable by said decoder means, each set providing a different scale of measurement for the parameter being measured, and wherein said control means further includes means for selecting a single set of first, second and third counter values to select a respective scale.
9. The analog-to-digital converter according to claim 8, wherein at least one set of counter values is selectable to provide for the measurement of said parameter in metric units of measurement and at least one other set of counter values is selectable to provide for the measurement of said parameter in English units of measurement.
10. The analog-to-digital converter according to claim 8, wherein the second counter value is selected to be the same for both scales, the lowest order digits of the minimum value being selected to be the same for both scales.
11. A dual slope analog-to-digital converter comprising: (a) oscillator means for generating a clock pulse signal; (b) counter means having a plurality of binary coded decimal stages coupled to said oscillator means for counting the pulses of said clock pulse signal and for generating a binary coded decimal output signal indicative of said count; (c) first and second operational amplifier means each having at least an input and an output means; (d) an integrator circuit having an input means, an output means and an integration capacitor for producing ramp voltage signals; (e) means coupled to the input means of said first operational amplifier means for receiving an analog signal representative of a measured parameter; (f) means coupled to the input means of said second operational means for receiving a reference voltage signal; (g) first controllable switch means for alternately coupling the outputs of each of said operational amplifier means to the input of said integrator circuit; (h) second controllable switch means coupled to said integrator circuit for selectively discharging said integration capacitor; (i) selector means coupled to said first and second controllable switches for activating said switches in a predetermined sequence, said selector means activating said second switch to discharge said integration capacitor during the duration of a first time period, activating said first switch to apply a scaled analog voltage representing the measured parameter to the input of said integrator circuit during the duration of a second time period, and activating said first switch to apply a scaled reference voltage representing the full-scale range of said analog signal during a third time period; (j) control means coupled to said counter means and to said selector means for controlling the duration of each of said first, second and third time periods wherein said second time period is represented by the duration of said counter means counting from a first counter value to a second counter value, said third time period is represented by said counter means counting from said second counter value to a third counter value and said first time period is represented by said counter means counting from said third counter value to said first counter value, said second counter value being selected so that at least a plurality of the lowest order decimal digits thereof are equivalent to respective lowest order decimal digital of the minimum value of the parameter being measured, each count of said counter means representing a unit of the parameter being measured whereby the binary decimal equivalent of the lowest order digits of the parameter being measured are directly readable from the respective lowest order stages of said counter means; (k) comparator circuit means coupled to said integrator circuit for producing a logical transition when the ramp voltage produced by said integrator circuit crosses a threshold voltage; (1) controllable latch means having a control input coupled to said comparator circuit means and data input means coupled to said counter means for storing the binary coded decimal count of said counter means when said logical transition is produced by said comparator circuit, the stored count being a binary coded decimal representation of said analog signal, a plurality of the lower order digits of which are directly readable therefrom.
12. The analog-to-digital converter according to claim 11, wherein the lowest order digits of the minimum value of the parameter being measured are non-zero and wherein said second counter value is selected so that the respective lowest order digits thereof are equivalently non-zero.
13. The analog-to-digital converter according to claim 11, wherein the total number of counts comprising the duration of said first state is selected to be equal to the desired full-scale range of the parameter to be measured.
14. The analog-to-digital converter according to claim 11, wherein each count of said counter means represents a decimal fractional unit of the parameter being measured.
15. The analog-to-digital converter according to claim 11, wherein said control means includes decoder means coupled to said counter means, said decoder means being selectively responsive to said first, second and third counter values.
16. The analog-to-digital converter according to claim 15, wherein a plurality of sets of first, second and third counter values are decodable by said decoder means, each set providing a different scale of measurement for the parameter being measured, and wherein said control means further includes means for selecting a single set of first, second and third counter values to select a respective scale.
17. The analog-to-digital converter according to claim 16, wherein at least one set of counter values is selectable to provide for the measurement of said parameter in metric units of measurement and at least one other set of counter values is selectable to provide for the measurement of said parameter in English units of measurement.
18. The analog-to-digital converter according to claim 16, wherein the second counter value is selected to be the same for both scales, the lowest order digits of the minimum value being selected to be the same for both scales.
19. A digital thermometer comprising: (a) thermistor means for producing an analog signal indicative of a measured temperature; (b) oscillator means for generating a clock pulse signal; (c) counter means having a plurality of binary coded decimal stages coupled to said oscillator means for counting the pulses of said clock pulse signal and for generating a binary coded decimal output signal indicative of said count; (d) an integrator circuit having an input and an output means for producing ramp voltage signals; (e) first and second operational amplifier means, each having at least an input means and an output means, the input means of said first amplifier means coupled to said thermistor means and the input means of said second amplifier means coupled to receive a reference voltage signal; (f) controllable switch means coupling the output means of said first and second amplifier means to the input means of said integrator circuit for selectively switching an analog voltage representing the measured temperature from said first amplifier means and a scaled reference voltage representing the full temperature scale alternately to the input means of said integrator circuit, said integrator circuit for producing a ramp voltage in one direction when the analog voltage representing the measured temperature is applied to the input means thereof and for producing a ramp voltage in the opposite direction when the scaled reference voltage is applied to the input means thereof; (g) control means coupled to said counter means and to said controllable switch means for controlling said controllable switch means to apply the analog voltage representing the measured temperature to said integrator means for a first counter value to a second counter value and for applying said scaled reference voltage to the input means of said integrator circuit for a second predetermined time period represented by said counter means counting from said second counter value to a third counter value, said second counter value being selected so that a plurality of the lowest order digits thereof are equivalent to the respective lowest order digits of the minimum value of the temperature being measured and wherein each count represents a decimal fraction of a degree whereby the binary coded decimal equivalent of at least a plurality of the lowest order digits of the temperature being measured are directly readable from respective stages of said controllable storage means; (h) comparator means coupled to the output means of said integrator circuit for producing a logical signal when the integrator ramp voltage crosses a predetermined threshold voltage level; (i) controllable storage means having a control input coupled to said comparator means, said storage means having a plurality of stages respectively coupled to the states of said counter means for storing the binary coded decimal count of said counter means in response to said logical signal being generated by said comparator means; and (j) a digital display means coupled to said controllable storage means for digitally displaying the measured temperature.
20. The digital thermometer according to claim 19, wherein said control means includes decoder means coupling said counter means to said controllable switch means.
21. The digital thermometer according to claim 19 including decoder means coupling said controllable storage means to said digital display means for decoding the stored counter values from binary coded decimal format to display coded format.
22. The digital thermometer according to claim 21 including multiplexer means coupling said controllable storage means to said decoder means wherein said digital display is multiplexed.
23. The digital thermometer according to claim 19, wherein the lowest order digits of the minimum temperature being measured is non-zero and wherein said second counter value is selected so that the respective lowest order digits are equally non-zero.
24. The digital thermometer according to claim 19, wherein the total number of counts comprising the duration of said first predetermined time period is selected to be equal to the desired full-scale range of temperature and the number of counts comprising the duration of said second predetermined time period is selected to be greater than the desired full-scale range of temperature.
25. The digital thermometer according to claim 19, wherein each count of said counter means represents one tenth of a degree of temperature.
26. The digital thermometer according to claim 19, wherein said control means includes decoder means coupled to said counter means, said decoder means being selectively responsive to said first, second and third counter values for providing said first and second predetermined time periods.
27. The digital thermometer according to claim 26, wherein a plurality of sets of first, second and third counter values are decodable by said decoder means, each set providing a different scale of temperature measurement, and wherein said control means further includes means for selecting a single set of first, second and third counter values to thereby select a respective scale, each count of said counter means being equivalent to one decimal fractional unit of a degree in the selected scale.
28. The digital thermometer according to claim 27, wherein at least one set of counter values is selectable to provide for the measurement of temperature in degrees Centigrade and at least one other set of counter values is selectable to provide for the measurement of temperature in degrees Fahrenheit.
29. The digital thermometer according to claim 28, wherein the second counter value is selected to be the same for both scales, the lowest order digits of the minimum vlaues being the same for both degrees Centigrade and degrees Fahrenheit.
30. The digital thermometer according to claim 27, wherein the display means for one of said scales has at least one digit more than the display means for the other of said scales and wherein said means for selecting the set of counter values is responsive to the display selected to control said decoder means accordingly.
31. A digital thermometer comprising: (a) temperature-sensitive means for producing an analog electrical signal indicative of a measured temperature; (b) a dual slope analog-to-digital converter coupled to said thermistor means for converting said analog electrical signal to a digital signal, said analog-to-digital converter including: (i) an analog integrator means, (ii) counter means having a plurality of binary coded decimal stages for generating a binary coded decimal count indicative of the measured temperature, (iii) storage means having a plurality of stages respectively coupled to said counter means for storing the binary coded decimal count when said count is indicative of the measured temperature, and (iv) control means for controlling said integrator means to integrate with said analog signal indicative of the measured temperature for a first predetermined time period represented by said counter means counting from a first counter value to a second counter value and to integrate with a reference voltage for a second predetermined time period represented by said counter means counting from said second counter value to a third counter value, said control means including: (A) decoder means coupled to said counter means, said decoder means being selectively responsive to a plurality of sets of first, second and third counter values, each such set providing a different scale of temperature measurement, and (B) selection means for selecting a single one of said sets of first, second and third counter values to thereby select a respective scale of temperature measurement, each count of said counter means being equivalent to one decimal fractional unit of a degree in the selected scale, said second counter values being selected to be identical for each of said scales, and (c) a digital display means coupled to said storage means for displaying the stored counter value, at least a plurality of the lowest order digits of said stored counter value being directly readable in either selected scale.
32. The digital thermometer according to claim 31, wherein at least one of said sets of counter values is selectable to provide for the measurement of temperature in degrees Centigrade and at least one other set of counter values is selectable to provide for the measurement of temperature in degrees Fahrenheit.
33. The digital thermometer according to claim 31, wherein the display means for one of said scales has at least one digit more than the display means for the other of said scales and wherein said selection means is responsive to the selected display to control said decoder means accordingly.
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