Low Power JFET Switch

This invention relates to integrated circuit analog devices and, more particularly, to a transistor switching circuit for switching an input voltage to an output.

A known JFET switch has been utilized having a three transistor common gate configuration, since this results in a minimum die area during fabrication and high speed characteristics. Three FETs are placed on a common isolated epitaxial island and occupy only fractionally more area than that required by the main switch. The switching speed is increased because of the reduction in the gate capacitance which is a major factor in determining speed.

The prior art approach has the disadvantage that in order to achieve the fast switching characteristics, a large idle current is allowed to flow when the switch is off, thus wasting power and increasing the overall size of the device.

It is therefore an object of this invention to improve the performance of the Tri-JFET switch by reducing the wasted idle power for high speed operation with the resulting reduction in silicon die area.

Briefly, the above object is accomplished in accordance with the present invention by providing a bipolar transistor circuit in combination with the turn-on JFET such that the bipolar transistor turns on only during the transition from open to closed of the switch, and during this transition amplifies the source to drain current of the turn-on transistor to thereby discharge the gate capacitance of the circuit.

The circuit has the advantage that the additional transistor by providing current amplification, makes it possible for the turn-on JFETs to be made small because of their reduced current requirements, without sacrificing any of the high speed switching capabilities of the circuit.

The circuit has the further advantage that it is easy to manufacture because the JFET device and the bipolar device can share one epitaxial island, thus providing considerable area saving on the chip and a sizeable reduction in the common gate capacitance C.sub.g.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

FIG. 1 is a circuit diagram of a prior art tri-JFET switch;

FIG. 2 is a circuit diagram of a tri-JFET switch modified in accordance with the present invention; and

FIG. 3 is a plan view of an integrated circuit layout implementation of the switch of FIG. 2.

Referring now to FIG. 1, the prior art switch will be described. J1 functions as the pass transistor, and J2 and J3 function as the turn-on circuit. The clamp voltage V.sub.CL is designed to be equal to or higher than the highest analog input voltage V.sub.in to be switched. When the drive voltage V.sub.dr rises to a level equal to or higher than the sum of V.sub.CL + V.sub.be + V.sub.p, (where V.sub.be is the diode base to emitter voltage drop and V.sub.p is the pinch-off voltage of the JFET) the transistors J1 and J2 turn off. The source-to-drain current (I.sub.dss) is referred to under these conditions as the idle current. The source-to-drain current (I.sub.dss) of transistor J3 now flows into the clamp circuit. When the drive terminal is open or when the drive current is not available, transistors J2 and J3 turn on. Transistor J3 is on but it does not conduct current and therefore its gate voltage is equal to its drain voltage. It follows that the gate voltage of J2 is equal to its source voltage, and J2 is turned on. Since J2 does not conduct current, therefore its drain voltage is equal to its gate voltage. This places a short across the gate and source of transistor J1 and it turns fully on. The size (W/1) of transistors J2 and J3 where w is the channel width and 1 is the channel length, determine the switching speed and the idle power of the circuit, since it is the I.sub.dss current which discharges the common gate capacitance C.sub.g. While this circuit achieves fast switching, it is at the expense of a large idle current which is allowed to flow, thus wasting power and increasing the overall size of the device.

Referring now to FIG. 2, the present invention will be described. The circuit of FIG. 2 is identical to the circuit of FIG. 1 with the addition of a bipolar transistor Q1 and a JFET J4. Also, the sizes of J2' and J3' are made smaller since their current needs are not as large for high speed switching.

When the switch is open, the drive voltage V.sub.DR and hence the voltage at the common gate point is greater than the sum of V.sub.CL + V.sub.be + V.sub.p where V.sub.p is the pinch-off voltage. V.sub.CL is maintained higher than the analog input voltage V.sub.IN. Thus, when the switch is open, J2', J4 and Q1 are off and J3' conducts. When the switch is closed, J3' is not conducting, J2' and J4 are biased on but are not conducting, and the gate voltage V.sub.g is equal to V.sub.IN. Therefore, Q1 is biased off. Q1 turns on only during the transition from open to closed of the switch. When this occurs Q1 amplifies the I.sub.dss of J3' to thereby discharge the common gate capacitance C.sub.g. The current amplification is determined by the ratio between W/1 of J2' and J4. With Q1 in the circuit, J2' and J3' can be made smaller since their current needs are not as large for the same high speed switching capabilities.

Referring now to FIG. 3, the integrated circuit chip layout of the circuit of FIG. 2 is shown. The four FETs and the bipolar transistor are placed in a common expitaxial island and occupy almost the same amount of space that the prior art circuit occupies.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.