Method for Fabricating Self-Aligned CCD Devices and Their Output Self-Aligned MOS Transistors on a Single Semiconductor Substrate

This invention relates generally to a self-aligned charge coupled device (CCD) and a process for making same. More specifically, it relates to a two-phase or four-phase self-aligned gate CCD and its output self-aligned gate field effect transistors. Both the CCD and the transistors are formed on the same semiconductor body during the same processing operations.

A charge coupled device is a semiconductor apparatus used for storing and sequentially transferring charges, representing information, between potential wells created adjacent the surface of the semiconductor body under a dielectric layer. These potential wells are induced by the sequential application of voltages to an array of conducting electrodes located on top of the dielectric layer adjacent the semiconductor body, and interconnected to establish a two-phase, three-phase or four-phase operation.

Two-phase CCD structures employing differential gate insulator thicknesses to produce a different interface potential for a given gate voltage are generally well known. These structures usually have overlapping electrodes isolated from each other by a dielectric material and are connected in pairs. Sometimes they also have ion implanted regions in the substrate which are self aligned with a first set of electrodes. The two sets of electrodes either partially overlap each other or have small interelectrode gaps. When they overlap, they produce a coupling capacitance, which permits the feedthrough of clock voltages and degrades the performance of the device, especially at high frequencies. When interelectrode gaps exist, the charge transfer efficiency of the device is degraded.

In addition, very often the frequency response of a CCD structure is limited by the response of its output MOS transistors.

Early charge coupled semiconductor devices were disclosed, for example, in an article entitled "Charge Coupled Semiconductor Devices," B.S.T.J. April, 1970, pages 587-593 inclusive. The article discloses a structure comprising a semiconductor substrate, an insulating layer overlaying one of its surfaces and a plurality of metal electrodes disposed over the insulating layer. It is a three-phase device which moves packets of minority carriers along a region close to the semiconductor insulator interface by the sequential application of voltages to the three sets of electrodes. The voltages create potential wells of varying depth in which charges can be injected and stored until they are forced to spill over and be collected in an adjoining potential well, thus moving along in the desired direction. The third electrode is in effect a blocking electrode which prevents the charges from flowing back. The transfer of charges is not without loss, and much of the transfer inefficiency is due to the interelectrode distances. Thus, etching small gaps between the electrodes provides a considerable practical limitation to the operational efficiency of this structure. A diagrammatic cross-sectional view of such a structure is shown in FIG. 1, which is described in some detail at a later section of the specification.

U.S. Pat. No. 3,651,349 of D. Kahng et al. discloses a two-phase CCD cell. In this structure the need for a third electrode in every cell is eliminated by using two overlapping electrodes and non-uniform dielectric thicknesses to achieve an asymmetrical potential well necessary to enhance the transfer of charges in a predetermined direction and impede their flow in the opposite direction. A diagrammatic cross-sectional view of such a structure is shown in FIG. 2, which is also described in some detail at a later section of the specification.

A major limitation of this device is its high coupling capacitance caused by the overlapping of adjacent electrodes. This produces voltage spikes which permit the feedthrough of clock voltages. Also the gate electrode overlap makes possible the generation of electrical shorts when the quality of the insulating dielectric layer is poor.

The general purpose of this invention is to provide a new and improved CCD structure with two sets of self-aligned gate electrodes and an output self-aligned gate field effect transistor and the fabrication process therefor, having most if not all of the advantages and desirable features of similarly employed devices and related processes, while eliminating many of the aforementioned disadvantages of prior art structures.

To accomplish this purpose, I have provided a method of fabricating a semiconductor charge coupled device with an output transistor structure wherein initially a first layer of an electrically insulating material is formed on a surface of a semiconductor substrate having a first type of conductivity. A first layer of semiconductor material is then disposed over predetermined portions of the first layer of electrically insulating material. A second layer of electrically insulating material is formed over the first semiconductor layer and a second layer of a semiconductor material is disposed over selective predetermined portions of the second insulating layer. The exposed portions of the electrically insulating material are removed and a conductivity determining impurity is diffused into the exposed semiconductor material, and the exposed portions of the semiconductor substrate, using the first and second semiconductor layers as diffusion masks. This impurity is capable of forming a second type of conductivity in the substrate material into which it diffuses and converts the first and second insulating semiconductor materials into conductors. A truly self-aligned CCD/MOS structure is achieved with this process. The two sets of electrodes are in perfect alignment with each other, thus assuring an optimum coupling of the potential wells and a minimum of coupling capacitance and noise. Similarly, in the output stage, the transistor gate is used as a diffusion mask for the formation of the source and drain regions. This improves the transconductance of the transistor and thus improves its high frequency characteristics. An added advantage of this process is that the CCD electrodes, the conductive transistor gate, and the transistor source and drain regions, are all formed during the same single diffusion operation.

The frequency response of a CCD structure is very often limited by the response of its output transistor. My process makes possible the fabrication of output self-aligned gate field effect transistors fabricated on the same substrate with the main body of the CCD and during the same processing steps. This can be done regardless of whether the CCD electrodes are self aligned. For example, my invention can be practiced by building a CCD with two sets of polycrystalline electrodes and a self-aligned MOS output transistor all in a single semiconductor body during the same processing steps. If the CCD electrodes are not self aligned, then the first set of electrodes should be fabricated using doped polycrystalline silicon and the second set using either doped or undoped polycrystalline silicon. This is because the electrodes of the second set and parts of the electrodes of the first set will be doped again during the formation of the source and drain regions of the output transistor.

A structure may be constructed in accordance with this invention where instead of diffusion, ion implantation may be used for the doping of the gate electrodes and the formation of the source and drain regions.

Using this invention, both N-channel and P-channel structures can be constructed with good high frequency response and low noise. Although most discussion in this specification focuses around the P-channel CCD structures, the same principles apply to the fabrication of both P- and N-type structures. Similarly, while most discussion focuses around silicon devices using polycrystalline silicon gates, there is nothing to limit the invention to this combination of materials.

Accordingly, it is an object of the present invention to provide a new and highly reproducible process for the fabrication of a charge coupled device and its output transistors.

Another object is to provide a novel method for fabricating a charge coupled device and its input and output structures on the same semiconductor body using the same processing steps.

Another object of this invention is to provide a method for making a self-aligned CCD and a self-aligned MOS transistor where the CCD electrodes, the transistor gate electrodes and the transistor source and drain regions are all formed during the same impurity doping operations.

Another object of this invention is to provide a new CCD/MOS transistor structure having an improved frequency response and an improved signal-to-noise ratio.

These and other objects of the invention will become apparent in the following description taken in conjunction with the accompanying drawings.

FIG. 1 shows a cross-sectional view of a portion of a prior art CCD structure;

FIG. 2 shows a cross-sectional view of another prior art CCD structure;

FIG. 3 is a sectional view of the CCD/MOS structure fabricated in accordance with the present invention;

FIGS. 4a through 4f illustrate, in a series of diagrammatic cross-sectional views, a sequence of some of the most important process steps utilized in fabricating a CCD/MOS structure in accordance with the present invention; and

FIGS. 5a through 5e illustrate, in a series of cross-sectional views, a sequence of alternate steps utilized in fabricating a CCD/MOS structure in accordance with the present invention.

Referring now to FIG. 1, there is shown a portion of a prior art CCD, generally designated 5. The structure includes a semiconductor substrate 8, a dielectric layer 10, and a set of metal electrodes 12. Every third electrode is connected to a common conductor which makes this structure a three-phase device. Such a device was described by W. S. Boyle and D. E. Smith in an article published in the Bell Systems Technical Journal of April 1970, on pages 587-593, inclusive. The three sets of electrodes are formed from a single layer of metal which is etched to form a set of narrow interelectrode gaps. The major limitations of such a structure are associated with the quality and size of these gaps. The gaps must be as small as possible, so that the potential wells can couple efficiently. However, it is difficult to sufficiently reduce their size and at the same time be able to maintain an acceptable processing yield.

Referring now to FIG. 2, there is shown a portion of a prior art CCD, generally designated 15. The structure includes a semiconductor substrate 18, a dielectric layer 20, and a set of electrodes 22. This is a two-phase device, so every other electrode is connected to the same conductor. Such a device is described in more detail in U.S. Pat. No. 3,651,349 of D. Kahng et al. One limitation of this structure is due to the high coupling capacitance generateed by the overlap of adjacent electrodes. This becomes more important at high operating frequencies.

Referring now to FIG. 3, there is shown a cross-sectional view of a monolithic integrated CCD/MOS structure constructed in accordance with the present invention. It includes an input diode, an array of CCD cells, and two output MOS transistors, all fabricated on a single substrate during the same processing steps. The CCD cells are constructed with two sets of self-aligned electrodes wired for a two-phase operation. The same structure may also be wired for a four-phase operation. The output structure contains two self-aligned insulated gate field effect transistors. Although the structure shown in FIG. 3 was fabricated on an N-type silicon substrate, the invention is not limited to N-type silicon or to devices built in silicon. This is just one example of a structure fabricated using the present invention. It comprises an N-type silicon substrate 30, having a typical resistivity on the order of 3 ohm-centimeters. On the top of this substrate there is a layer of silicon dioxide 32, insulating the substrate from two sets of polycrystalline silicone electrodes (referred to as polysilicon electrodes). A first set 34 is within approximately 1,000 A from the substrate and a second set 38 is within approximately 3,000 A from the substrate. The electrodes of the second set partially overlap the electrodes of the first. The two sets are insulated from each other by a layer of SiO.sub.2 36. In addition, the parts 39 of the electrodes of the first set that are covered by the electrodes of the second set are not conductive, so that the effective electrodes of the two sets are in perfect alignment with each other, thus keeping the coupling capacitances between the upper and lower electrodes to a minimum.

The function of the two transistors at the end of the structure is to process the output signals. Each one uses a gate electrode belonging to the first set of polysilicon electrodes and insulated from the substrate by the same layer of SiO.sub.2 that insulates the other electrodes of the first set. The source regions 40 and 41 for the reset and output transistors, respectively, and drain regions 42 and 43 for the reset and output transistors, respectively, are made P.sup.+ during the doping of the two sets of electrodes and using the same electrodes as diffusion masks.

The P.sup.+ region 44 of the input diode is also formed during the same diffusion operation used for the formation of the P.sup.+ regions of the transistors.

Referring now to FIGS. 4a through 4f, there is shown, in a series of cross-sectional views, a sequence of some of the most important process steps which may be utilized to fabricate a CCD/MOS structure in accordance with the present invention. In FIG. 4a there is shown a semiconductor substrate 30, which may be N-type silicon on which a first dielectric layer 32 is formed. Typically, when the semiconductor substrate is silicon, the dielectric layer is a layer of silicon dioxide (SiO.sub.2) grown through the thermal oxidation of silicon and having a thickness on the order of 1,000 A. On the top of the first dielectric layer a first semi-insulating semiconductor layer, such as undoped polycrystalline silicon (referred to as undoped polysilicon) is deposited. The thickness of this layer is, for example, on the order of 5,000 A. Through conventional masking techniques, a gate electrode pattern is formed on the polysilicon layer, and through etching a first set of semiconductor strips is formed.

In FIG. 4b there is shown a set of polysilicon strips 34, formed adjacent to a first SiO.sub.2 layer. These strips will be used to make the first set of CCD electrodes and the gate electrodes of the output MOS transistors.

In FIG. 4c there is shown the processed structure after the formation of a second dielectric layer 36 on the top of the semiconductor strips and parts of the first dielectric layer. When the strips are made of polysilicon, the second dielectric layer may be silicon dioxide formed by the oxidation of the polysilicon and the further oxidation of parts of the silicon substrate that are not covered by the polysilicon strips. On the top of the second dielectric layer, a second semi-insulating semiconductor layer, such as undoped polycrystalline silicon, is deposited. The thickness of this layer is, for example, on the order of 4,000 A. Through conventional masking techniques a new gate electrode pattern is formed on the second semi-insulating layer, and through etching a second set of semiconductor strips is formed.

In FIG. 4d there is shown this second set of strips 38. The strips of the second set are spatially disposed over the intermediate areas between the strips of the first set and partially overlap these strips. However, the strips of the two sets are electrically insulated from each other and from the semiconductor substrate by the first and second dielectric layers.

In FIG. 4e there is shown the processed structure after the exposed parts of the dielectric layers have been removed. This exposes the top surfaces of the strips of the second set 38 and parts of the strips of the first set 34, and predetermined parts of the substrate for the source and drain regions of the output transistors.

The next step is to form the source and drain regions of the output transistor and the gate electrodes by diffusing a conductivity determining impurity different from the conductivity type of the substrate, into the exposed parts of the substrate and the exposed parts of the semiconductor strips. If the substrate is N-type, then a P-type impurity, such as boron, may be diffused in sufficient quantities to make the resistivity of the strips 50-100 ohms per square. The semiconductor strips are used as diffusion masks. Parts of the strips of the first set are left undoped, and therefore nonconducting, while the other parts are in perfect alignment with the strips of the second set, thus assuring an optimum coupling for the potential wells and a minimum of coupling capacitance and noise. Similarly, since the gate electrode of the output transistor was used as a diffusion mask, it is perfectly aligned to the source and drain regions.

Referring now to FIGS. 5a through 5e, there is shown, in a series of cross-sectional views, an alternate sequence of process steps utilized in fabricating a CCD/MOS structure in accordance with the present invention. The main difference between these process steps and the ones described before is in the method of introducing impurities for the formation of the gate electrodes of the whole structure and the source and drain regions of the transistors. In the process steps shown by FIGS. 5a through 5e, ion implantation is used instead of diffusion. In FIG. 5a there is shown a semiconductor substrate 60, such as, for example, an N-type silicon substrate with a resistivity on the order of 3 ohm-centimeters, on which a first dielectric layer 62 is formed. Typically, when a semiconductor substrate is silicon, the dielectric layer is silicon dioxide, grown thermally and having a thickness on the order of 1,000 A. On the top of the first dielectric layer 62, a first semi-insulating semiconductor layer, such as undoped polysilicon, is deposited. The thickness of this layer is on the order of 5,000 A. Through conventional masking techniques a gate electrode pattern is formed on the polysilicon layer, and through etching a first set of polysilicon strips 64 is formed. Using the polysilicon strips as an ion implantation mask, N-type ions, such as phosphorous ions, are implanted into the substrate. The concentration of these ions is on the order of 10.sup.12 atoms/cm.sup.2. The resultant impurity concentration of these implanted regions is higher than the original impurity concentration of the substrate. This forms shallow N.sup.- regions 66 in the implanted areas of the substrate as shown in FIG. 5b. The reason for forming these N.sup.- regions is in order to shift the threshold under the second polysilicon layer to be formed. The structure is then oxidized again in a dry oxygen ambient to achieve a second silicon dioxide layer 68, as shown in FIG. 5c. In FIG. 5d there is shown the same structure after the formation of the second set of polysilicon strips 70. The strips of the second set fill the area between the strips of the first set and partially overlap them. In FIG. 5e there is shown the same structure after the growing of a new SiO.sub.2 layer 72. The purpose of this layer is to facilitate the ion implantation step to follow. The thickness of the SiO.sub.2 layer over the strips of the second set is on the order of 1,000 A, while the combined thickness of the two SiO.sub.2 layers on the top of the strips of the first set and over the predetermined source and drain regions of the output structure is on the order of 2,000 A or less.

The next step is to plant into the strips and the substrate, ions of a different conductivity type to that of the substrate. For the N-type substrate of our example, ions of a P-type impurity, such as boron, may be used for this purpose. The polysilicon strips are used as implantation masks to assure the formation of two perfectly aligned sets of CCD electrodes and for the output structure the formation of source and drain regions 74 and 76, respectively, perfectly aligned to the gate electrodes. The ion concentration (on the order of 10.sup.15 atoms/cm.sup.2) during this implantation is sufficiently heavy to overcompensate the N.sup.- dopants previously implanted in the source and drain regions, and transform these same regions into P.sup.+ type regions.

While the invention has been described in connection with a preferred sequence of process steps used to fabricate a basic CCD/MOS structure, it will be understood that the invention is not to be limited to those particular process steps, their sequence, or the final structures depicted in the drawings. On the contrary, it is intended to cover all alternatives, modifications and equivalents, as may be included within the spirit and scope of the invention as defined in the appended claims.