Time Signal Clock

The present invention relates to a time signal clock which indicates the time by moving a pointer by a motor drive, under the control of a quartz oscillator or commercial power frequency as the standard frequency, while giving time signals by sound.

The construction of a conventional quartz oscillator controlled clock is shown schematically in to FIG. 1. In the clock of FIG. 1, the standard frequency is established by the quartz vibrator 1 which serves as the standard frequency oscillation source; the aforementioned standard frequency is divided to obtain the desired frequency by the dividing circuit 2; and a signal of this desired frequency is transmitted to the driving means 3 including a step motor, etc., so that the time is indicated on the time indicating means 5 such as a graduated face by motor driven pointer means 4 having a long hand, a short hand, a second hand, etc. The power is supplied normally at a voltage of 1.5 V .about. 3.0 V to the dividing circuit or the drive 3. While in the clock of FIG. 1, the standard frequency is obtained from the quartz vibrator, the commercial power frequency can also be used as the standard frequency.

With conventional clocks of this type, it is possible to provide visual perception of time by making the analogue indication of time the angle of the pointer, but they can not be equipped with a time signal giving means such as will produce a striking sound like such means provided in mechanical clocks.

The making of part or all of the chronometric device as shown in FIG. 1 electronic has brought about remarkable improvements in the accuracy of clocks and improved the simplicity of the chronometric devices themselves, but it has not been possible to provide means for detecting the time to be signaled. There has thus been provided clocks with high accuracy, but which are incapable of giving a time signal.

However, not only the visual but also the auditory senses as a means of perceiving time are very important. For example, it is possible to readily perceive a time indicating sound signal while engaging in work without glancing at the clock from time to time. Further, the time as signaled by sound may be perceived by a person outside the angle from which the face of the clock is visible. The conventional electronic clocks with indicating hands are deficient in that they have no time indicating signal giving means as described above.

This invention provides a novel time signal clock equipped with time indicating signal giving means, such as a sound or light signal, which also indicates the time by moving a pointer means, such as hands, by a motor drive under the control of a quartz vibrator or commercial power frequency providing the standard frequency.

A more detailed description of the invention is given in the following specification with reference to the accompanying drawings in which:

FIG. 1 is a schematic block diagram of the construction of a conventional quartz clock;

FIG. 2 is a schematic block diagram of the construction of a time signal clock according to the present invention;

FIG. 3 is a schematic block diagram of a modified form of the clock of FIG. 2;

FIG. 4 is a front view of a time signal clock embodying the present invention;

FIG. 5 is a sectional side elevation view of the time signal clock shown in FIG. 4;

FIG. 6 is a perspective view showing a speaker mounted on the time signal clock of the present invention;

FIG. 7 is a block diagram showing the construction of a time indicating signal giving circuit;

FIGS. 8 and 9 are circuit diagrams of time indicating signal giving electronic circuits employed in the present invention;

FIGS. 10, 11R6, 11B, 11C and 11D are wave form diagrams of the signals at various points in the time indicating signal giving electronic circuits;

FIGS. 12 and 13 are circuit diagrams of modified forms of the time indicating signal giving electronic circuit shown in FIG. 9; and

FIG. 14 is a view showing a bell mounted on the time signal clock of the present invention.

Embodiments of the time signal clock according to this invention are shown schematically in FIGS. 2 and 3. The time signal clock of this invention is composed, as shown in FIG. 2, of a mechanism capable of giving an indication, such as a visual indication, of time and having of the standard signal source 1, driving means 3 including a dividing circuit such as the circuit 2 in FIG. 1, and an indicating means 5, and a mechanism capable of giving an auditory indication of time and having a time signal circuit 6 operated by an output from the indicating means 5, and the output of which is, in turn, converted into sound by means of a sound generator 7 consisting of a speaker, or the like. While in the embodiment of FIG. 2 the source for the input to the time signal circuit 6 is the indicating means 5, in the case of analogue electronic clocks, time pulses paralleling those supplied to the indicating means 5 can be taken out of the driving means 3 as an output and be used as the input to the time signal circuit 6 to operate the time indicating signal giving mechanism.

The main components of the time indicating signal giving mechanism include the time detecting means for producing an output from the indicating means 5, a time signal circuit 6 and time indicating signal giving means 7. One example of the time detecting means is shown in FIGS. 4 and 5. This example of the time detecting means of this invention is composed of a permanent magnet and a magnetically sensitive switch, for example, a reed switch. The most essential key to finding a way of detecting the time for which a signal is to be given is that at all such times, the long hand is superposed on a graduation on the indicating means. For example, as shown in FIGS. 4 and 5, the reed switch 22 which is operated by magnetic force is located at the position of the graduation 21 for 12 o'clock provided on the clock face mounted in housing 8, and a permanent magnet 24 is fixed to the tip of the long hand 23 at a position such that it moves across the aforementioned reed switch at a specified distance therefrom. Accordingly, when the long hand 23 comes to the graduation for 12 o'clock, that is, at the set time, the aforementioned reed switch is actuated, i.e. is either opened or closed, by the magnetic force of the permanent magnet 24 mounted on the long hand 23. In that way, a signal is transmitted from the reed switch to the time signal circuit each hour. This example of the detecting means of this invention can be adapted for producing a signal for any desired time merely by providing the detecting means at a position on the indicating means corresponding to the desired time.

FIG. 6 shows one way of mounting a sound generator 7 which is in the form of a speaker 9 in the housing 8 of the clock. The speaker 9 for giving the time indicating signal is shown as being mounted on the side of the housing. While with the construction of FIG. 6, the sound of the time indicating signal will be heard from the side of the clock, the speaker may be installed at any desired position, such as the top, bottom or front of the housing 8.

The construction of the time signal circuit will be described with reference to FIG. 7. This circuit is composed of the time detecting circuit 10 attached to part of the indicating means 5, a switch circuit 11 connected to the time detecting circuit 10 for shaping the wave form of the output of the time detecting circuit, a counting circuit 12 connected to the switch circuit and which records the time given by the indicating means 5, a comparison circuit 15 connected to the counting circuit, a series connected delay circuit 14 and pulse series producing circuit 13 connected to the switch circuit 11 in parallel with the counting circuit 12 and which provides a delay of the inputs to the pulse series producing circuit 13. The comparison circuit 15 is connected to the pulse series producing circuit for comparing the output of the counting circuit 12 with the number of pulses from the pulse series producing circuit 13 which produces a number of pulses corresponding to time indicated by the indicating means 5. A modulation circuit 16 converts the pulses from pulse series producing circuits into audible frequencies, thereby providing a reverberation effect, and an amplifier circuit 17 subjects the output from modulation circuit 16 to DC amplification and the output thereof is connected to the sound generator 7 which turns this output into sound. It is to be noted that if the signal produced by the time detecting circuit 10 is free of noise, the switching circuit 11 may be omitted, but its presence is preferred for prevention of misoperation. Sometimes, depending on the circuit construction of the pulse series producing circuit 13, the delay circuit 14 may be omitted, and the modulator circuit may be omitted and the time signal sound produced directly from the output signal of the circuit 13.

In the following, the construction of the time signal circuit shown schematically in FIG. 7 is described further in detail with reference to FIG. 8. At the position on the face plate of the indicating means 5 corresponding to the time to be indicated by the signal, for example, the position 21 for 12 o'clock, the magnetically sensitive switch 22 is installed, and on the side of the long hand 23 toward the clock, the permanent magnet 24 is mounted, as shown in FIG. 4. One end of the magnetically sensitive switch 22 is, as shown in FIG. 8, connected to the high potential (hereinafter designated by V.sub.DD) side of the power supply, and the other end A shown in FIG. 8 is joined to the low potential (hereinafter designated by V.sub.SS) side of the supply through the resistance R.sub.1, thus providing an output from the time detecting circuit 10 at A. This output is the input to the switch circuit 11 having an integrating circuit composed of the resistance R.sub.2 and condenser C.sub.1, the output of this integrating circuit being fed as the input D.sub.1 to the shift register (hereinafter designated by SR) SR.sub.1. The output of SR.sub.1 is used as the input to SR.sub.2, and the clock signal T.sub.1 for SR.sub.1 and SR.sub.2 is the output from the CR oscillator circuit composed of inverters (hereinafter designated I) I.sub.1, I.sub.2 and I.sub.3 and resistor R.sub.3 and condenser C.sub.2, which output is that from the inverter I.sub.3, the period of the clock signal being T = (1/C.sub.2 R.sub.3). The output from the NOR circuit (hereinafter designated by NO) NO.sub.1 to which the inverse phase output signal Q.sub.1 from SR.sub.1 and the output signal Q.sub.2 from SR.sub.2 are supplied as input is fed as the input to the inverter I.sub.4, thereby forming a one-shot circuit, and the output from I.sub.4 is supplied both as the input D.sub.3 to SR.sub.3 and with the input .phi..sub.7 to the flip-flop (hereinafter designated by F/F) F/F.sub.7. The output from SR.sub.3 is linked to the input to SR.sub.4, and the output from SR.sub.4 to the input to SR.sub.5. The, the same clock signal T.sub.1 given to SR.sub.1 and SR.sub.2 is supplied to SR.sub.3, SR.sub.4 and SR.sub.5. The output Q.sub.5 from SR.sub.5 is used as the input to F/F.sub.6, and the output of the series of pulses from the pulse producing circuit 13, that is, the output from the inverter I.sub.18 shown in FIG. 9, is supplied as the reset input R.sub.6 to F/F.sub. 6. The inverse phase signal Q.sub.6 which is the output from F/F.sub.6 is used as the input to the pulse producing circuit, 13, being the input to the inverter I.sub.14. The outputs of the flip-flops F/F.sub.7 -F/F.sub.10 are connected to the CMOS transfer gates (hereinafter designated by TG) TG.sub.1, TG.sub.2, TG.sub.3 and TG.sub.4 which become conductive when the signal N enters the gates and with the transfer gates (hereinafter designated by TG') TG'.sub.1, TG'.sub.2, TG'.sub.3 and TG'.sub.4 which becomes conductive when the inverse phase signal N as the output from I enters. The output Q.sub.7 from F/F.sub.7 is used as the input to F/F.sub.8 ; the output Q.sub.8 from F/F.sub.8 as the input to F/F.sub.9, and the output Q.sub.9 as the input to F/F.sub.10. Outputs Q.sub.7 and Q.sub.9 and the output Q.sub.10 from F/F.sub.10 are supplied to the NAND circuit (hereinafter designated by NA) NA.sub.1 as the input; the output thereof is used as the input to the inverter I.sub.5, and the output of inverter I.sub.5 is supplied to F/F.sub.7 as its set input and to F/F.sub.8, F/F.sub.9 and F/F.sub.10 as their reset inputs. F/F.sub.7 is a set type flip-flop, in which when a signal at a V.sub.DD level, hereinafter designated as a signal at the "1" level, a signal at a V.sub.SS level hereinafter being designated as a signal at the "0" level, is impressed thereon, the output Q.sub.7 is set to the "1" level. Other flip-flops F/F.sub.6, F/F.sub.8 .about. F/F.sub.14 are reset type flip-flops in which when a signal at the "1" level is impressed on the reset terminals, the outputs from the F/F's are at the "0" level.

As shown in FIG. 9, the output Q.sub.7 from F/F.sub.7 is used as the input to TG.sub.1, and the output thereof is supplied to the inverter I.sub.6 as the input thereto and to TG'.sub.1 as the input thereto. The output of I.sub.6 is used as the input to the inverter I.sub.7, and the output from I.sub.7 associated with the output from TG'.sub.1 is provided to the Exclusive-OR circuit (hereinafter designated by EX) as its input. In the same way as the output Q.sub.7 from F/F.sub.7 is used as the input to the latch circuit composed of TG.sub.1 and TG'.sub.1, and I.sub.6 and I.sub.7, and the output thereof is supplied to EX.sub.1 as the input thereto, the outputs Q.sub.8, Q.sub.9 and Q.sub.10 are respectively used as the inputs to the latch circuit composed of TG.sub.2 and TG'.sub.2, and I.sub.8 and I.sub.9, to the latch circuit composed of TG.sub.3 and TG'.sub.3, and I.sub.10 and I.sub.11 and to the latch circuit composed of TG.sub.4 and TG'.sub.4, and I.sub.12 and I.sub.13, and their respective outputs are provided to the Exclusive-OR circuits, EX.sub.2, EX.sub.3 and EX.sub.4, as their inputs. The output from the inverter I.sub.14 is linked to the reset terminals of F/F.sub.11 .about. F/.sub.14 and to the input terminal D.sub.15 of SR.sub.15. As the input to F/F.sub.11, the output from the series of pulses producing circuit, i.e., the output from I.sub.18, is used. Then, the output Q.sub.11 from F/F.sub.11 is used as the input to F/F.sub.12 ; its output Q.sub.12 as the input to F/F.sub.13 and the output Q.sub.13 as the input to F/F.sub.14. Outputs Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14 are also provided to the Exclusive-OR circuits, EX.sub.1, EX.sub.2, EX.sub.3 and EX.sub.4 as their inputs, and the outputs from EX.sub.1, EX.sub.2, EX.sub.3 and EX.sub.4 are all supplied to the NOR circuit NO.sub.2 as the input thereto. The output from NO.sub.2 is connected to the reset terminal of the flip-flop F/F.sub.16.

F/F.sub.16 is an RS flip-flop in which when a "1" level signal is impressed on the set terminal S.sub.16, and a "0" level signal on the reset terminal R.sub.16, the output Q.sub.16 is obtained at the "1" level; when a "0" level signal is impressed on S.sub.16 and a "1" level on R.sub.16, output Q.sub.16 is obtained at a "0" level; and when a "0" level signal is impressed on both S.sub.16 and R.sub.16, the output remains in its former state. The clock signal T.sub.2 to SR.sub.15 is provided by the output from the CR oscillator circuit composed of the inverters I.sub.15, I.sub.16 and I.sub.17 and condenser C.sub.3 and variable resistor R.sub.4, that is, the output from the inverter I.sub.17. Its period is T = (1/C.sub.3 R.sub.4).

The output Q.sub.15 from SR.sub.15 is supplied to the set terminal S.sub.16. The output Q.sub.16 from F/F.sub.16 and the output from the inverter I.sub.17 are fed into the NAND circuit NA.sub.2 as the input thereof; the output therefrom is fed into the inverter I.sub.18 as the input thereto, and the output therefrom, which is the output of the series of pulses producing circuit, is fed into F/F.sub.11 as its input thereto and into F/F.sub.6 shown in FIG. 8 as the reset input thereto. Moreover, the output (the output from I.sub.18) is fed into a differential circuit composed of C.sub.4 and R.sub.5 as the input thereto, and the output B of this differential circuit is led to the gate of the n-channel MOS transistor Tr.sub.1. While the source of Tr.sub.1 is connected to the V.sub.SS terminal, and its drain C to V.sub.SS through the resistance R.sub.6, one terminal of an condenser C.sub.5 having the other terminal linked to V.sub.SS is joined to the input terminal of an transfer gate composed of a p-channel transistor Tr.sub.2 and an n-channel transistor Tr.sub.3 with their sources and drains mutually associated, and the output D of the transfer gate is linked to V.sub.DD through a variable resistor R.sub.7. The output from the CR oscillator circuit composed of the inverters I.sub.20, I.sub.21 and I.sub.22 and the condenser C.sub.6 and variable resistor R.sub.8, i.e. the output from I.sub.22, is fed into the gate of Tr.sub.3 and the inverter I.sub.19 as the inputs thereto, and the output from I.sub.19 is led to the gate of Tr.sub.2.

The movable terminal of the resistor R.sub.7 is connected to the base of a PNP transistor Tr.sub.4, and the collector of Tr.sub.4 to the base of a NPN transistor Tr.sub.5. The emitter of Tr.sub.5 is linked to the V.sub.SS terminal. One terminal of the speaker 7 is connected to the emitter of Tr.sub.4 and the collector of Tr.sub.5, while the other terminal is linked to the V.sub.DD terminal.

In the following, the operation of the time signal circuit of this invention is described in reference to the waveforms of FIGS. 10, 11R6, 11B, 11C and 11D. First, as the magnetically sensitive switch 22 installed on the face at the position corresponding to 12 o'clock is actuated by the permanent magnet 24 mounted on the long hand 23 to indicate the time at which it is desired to produce a time indicating sound signal the magnetically sensitive switch 22 closes the time detecting circuit 100, and as a result, the signal at one terminal A of the switch 22 undergoes a change from a "0" level to a "1" level for producing noise, as shown by waveform A in FIG. 10. After the long hand passes through the position for 12 o'clock, the signal at the point A again goes from the "1" level back to the "0" level. The signal at the point A which has risen from the "0" to the "1" level is eliminated by making use of the integrating circuit composed of R.sub.2 and C.sub.1, yielding the wave form D.sub.1.

Q.sub.1 changes from the "1" level to the "0" level at the time when the level of the clock signal T.sub.1 falls the first time after the signal D.sub.1 has risen. Q.sub.2 changes from the "0" level to the "1" level at the time when the level of the clock signal T.sub.1 falls the second time after the signal D.sub.1 has risen. Accordingly, the input to the NOR circuit NO.sub.1 is at the "0" level only for one period of clock signal T.sub.1 from the time when the level of the clock signal T.sub.1 falls the first time after D.sub.1 has risen, thereby setting the output from NO.sub.1 at the "1" level for that one period only. The output from I.sub.4 is, then, converted to a signal held on the "0" level for one period of the clock level T.sub.1 as shown by D.sub.3. Since the same clock level T.sub.1 is applied to SR.sub.3, SR.sub.4 and SR.sub.5, Q.sub.5 is produced for one period only after a delay of 3 periods of clock signal T.sub.1 as compared with D.sub.3.

Then, the output Q.sub.6 from F/F.sub.6 changes from the "1" level to the "0" level when Q.sub.5 falls from the "1" level down to the "0" level. If F/F.sub.7,8,9,10 have been memorizing the condition of 1 o'clock, that is, if Q.sub.7 is on the "1" level, while Q.sub.8, Q.sub.9 and Q.sub.10 are on the "0" level, then, when the signal at D.sub.3 changes from the "1" level to the "0" level, Q.sub.7 changes to the "0" level and Q.sub.8 to the "1" level, while Q.sub.9 and Q.sub.10 remain at the "0" level; thus, F/F.sub.7,8,9,10 change state so as to memorize the condition of 2 o'clock.

It is to be noted that in the counting circuit 12 composed of F/F.sub.7.about.10, NAND circuit and inverter I.sub.5, as soon as the condition of 13 o'clock is produced, that is, Q.sub.7, Q.sub.9 and Q.sub.10 change to the "1" level, the output of I.sub.5 turns to "1", causing F/F.sub.7 to be reset, and as a result, the respective outputs Q.sub.7, Q.sub.8, Q.sub.9 and Q.sub.10 are changed to the levels of "1", "0", "0" and "0". That is to say, this counting circuit 13 is a binary counter which memorizes the decimal numbers 1-12 as binary coded signals.

F/F.sub.11 .about. F/F.sub.14 have also been memorizing the condition of 1 o'clock, that is, the outputs Q.sub.11, Q.sub.12, Q.sub.13 and Q.sub.14 are being held on "1", "0", "0" and "0" levels, and accordingly, the respective inputs to the Exclusive OR circuits EX.sub.1, EX.sub.2, EX.sub.3 and EX.sub.4 are in agreement. For this reason, all the outputs of the Exclusive OR circuits are at "0" levels; the reset R.sub.16 of F/F.sub.16 is at the "1" level; the output from NA.sub.2 is at the "1" level; and the output of the series of pulses producing circuit 13, i.e., the output from I.sub.18, is at the "0" level.

TG.sub.1 .about. TG.sub.4 are conductive because Q.sub.6, and thus, N, is at the "1" level. If at this time, the signals Q.sub.7 .about. Q.sub.10 change from "1", "0", "0" and "0" to "0", "1", "0" and "0", the inputs to EX.sub.1 and EX.sub.2 change so as to be in disagreement changing their output to the "1" level, and consequently the output from the NOR circuit NO.sub.2, and thus the reset input R.sub.16 to F/F.sub.16, changes to the "0" level. Then, when the signal Q.sub.6 changes from the "1" level to the "0" level, the reset inputs to F/F.sub.11 .about. F/F.sub.14 change from the "0" level to the "1" level, bringing all the outputs Q.sub.11 .about. Q.sub.14 to the "0" level. Q.sub.15, and thus the set input S.sub.16 to F/F.sub. 16, changes from the "0" level to the "1" level at the time when the clock signal T.sub.2 of SR.sub.15 changes from the "1" level to the "0" level the first time after the signal Q.sub.6 changes from the "1" level to the "0" level. At this time, since the reset R.sub.16 is at the "0" level as described hereabove, the output Q.sub.16 from F/F.sub.16 undergoes a change from the "0" level to the "1" level in coordination with the time at which S.sub.16 turns from the "0" level to the "1" level. Accordingly, the output from the NAND circuit NA.sub.2 provides a signal T.sub.2 which is in the inverse phase to the clock signal T.sub.2, and the inverter I.sub.18 produces the signal T.sub.2 as its output. Since the output from I.sub.18 is fed to the reset of F/F.sub.6, when the output from I.sub.18 is changed from the "0" level to the "1" level by the first pulse, Q.sub.6 turns from the "0" level to the "1" level. Then, the reset signal to F/F.sub.11 .about. F/F.sub.14 is removed. When the output from I.sub.18 is changed from the "1" level to the "0" level, the outputs from F/F.sub.11 .about. F/F.sub.14 change from "0", "0", "0" and "0" to "1", "0", "0" and "0". Then, when the output from I.sub.18 again changes from the "0" level to the "1" level, producing a second pulse, Q.sub.11 .about. Q.sub.14 change from "1", "0", "0" and "0" to "0", "1", "0" and "0". At this time, because the outputs from I.sub.7, I.sub.9, I.sub.11 and I.sub.13 are at the levels of "0", "1", "0" and "0", the inputs to EX.sub.1 .about. EX.sub.4 are all in agreement, their outputs all becoming "0". Then, the output from the NOR circuit NO.sub.2, and thus, the reset R.sub.16 for F/F.sub.16, changes from the "0" level to the "1" level, and as a consequence, the output Q.sub.16 therefrom changes from the "1" level to the "0" level. Consequently, the output from the NAND circuit NA.sub.2 is obtained at this "1" level, producing an output from the inverter I.sub.18 at the "0" level.

The foregoing description shows that when the time indicated on the face plate is just 2 o'clock, the magnetically sensitive switch becomes conductive; then, the inverter 18 produces only two clock pulses with a period of T.sub.2 as its output. The two clock pulses (R.sub.6 in FIG. 11R6) are differentiated to produce the wave form shown in FIG. 11B at the point B, in FIG. 9, causing the N-channel transistor TR, to be ON for a short period of time relative to T.sub.2. Then, the wave form at the point C may be altered to be a relaxation signal as shown in FIG. 11C by giving appropriate values to the resistance R.sub.6 and condenser C.sub.5. The CR oscillator, composed of the inverters I.sub.20, I.sub.21 and I.sub.22 and variable resistor R.sub.8 and condenser C.sub.6 is so set as to produce a frequency f.sub.3 in the audible range. When the output from I.sub.22 is at the "1" level, the P-channel transistor Tr.sub.2 and the N-channel transistor Tr.sub.3 turn ON, permitting the wave form at the point C to be delivered to the poing D in FIG. 9 as it is. If the output from I.sub.22 changes to the " 0" level, however, Tr.sub.2 and Tr.sub.3 turn OFF, and as a result, the potential at the point D is brought to the level of V.sub.DD due to the variable resistor R.sub.7. Consequently, the wave form at the point D is that of the relaxation signal of FIG. 11C modulated the audible frequency f.sub.3, as shown in FIG. 11D, with a time constant determined by the resistance R.sub.6 and condenser C.sub.5.

When a potential difference of more than 0.6 V is produced between the emitter and the base of Tr.sub.4 Tr.sub.4 is turned ON, and a current hfe.sub.4 times as large as the base current flows in the collector, and thus, in the base of Tr.sub.5. Accordingly, in Tr.sub.5, the potential difference between the base and the emitter becomes larger than 0.6 V, and a current hfe.sub.4 x hfe.sub.5 times as large as the base current of Tr.sub.4 flows as the collector current. Thereby the speaker produces an electronic sound which has the reverberation effect corresponding to the relaxation signal at an audible frequency of f.sub.3. On the other hand, when the potential at the point D is at the V.sub.DD level, the potential difference between the emitter and the base of Tr.sub.4 is smaller than 0.6 V, and accordingly, Tr.sub.4 and thus Tr.sub.5 are OFF; with no current flowing in the speaker 16, no electronic sound is produced.

The foregoing description shows that the period of the CR oscillator composed of inverters I.sub.15, I.sub.16 and I.sub.17 and variable resistance R.sub.4 and condenser C.sub.3 determines the interval between the time indicating sound signals, the interval being alterable by the variable resistance R.sub.4.

The frequency of the CR oscillator composed of inverters I.sub.20, I.sub.21 and I.sub.22 and variable resistor R.sub.8 and condenser C.sub.6 determines the tone of the time indicating sound signal, the tone of the time indicating sound signal being alterable by means of the volume R.sub.8. Furthermore, since the variable resistor R.sub.7 determines the amplitude of the signal at the point D, the strength of the time indicating sound signal may be altered by changing the volume R.sub.7.

The above-described time indicating sound signal circuit is so composed that the same number of electronic sounds as the numeral representing the time (e.g., two electronic sounds are produced at the time of 2 o'clock) can be produced even if only one signal enters the circuit at the predetermined time. Such a circuit obviously will find use not only in analogue type electronic clocks, but in conventional electrical clocks, alarm clocks, spring driven clocks or leaf type digital clocks as well.

When making the time indicating signal circuit of this invention as an integrated circuit, a F/F.sub.17 can be used in place of the differential circuit composed of condenser C.sub.4 and resistance R.sub.5, as shown in FIG. 12; the output of the inverter I.sub.18 is applied as the input .phi..sub.17, and the clock signal T.sub.1 of SR.sub.1 is applied to the reset input R.sub.17, and the output Q.sub.17 therefrom is fed into the gate of the N-channel transistor Tr.sub.1. Moreover, in the place of the resistance R.sub.6, a P-channel transistor Tr.sub.6 can be used, with its source connected to V.sub.DD and its gate and drain to the drain terminal C of Tr.sub.1. Furthermore, the resistances R.sub.1 and R.sub.3 can be replaced by similar load MOS transistors such as Tr.sub.6. In that way, the resistance R.sub.2, which in practice is on the order of several tens of K.OMEGA., can be integrated as the P well resistance, and the condenser C.sub.1, which is on the order of several PF, is amenable to integration.

In the electronic clock described hereabove, the signal detected by the time detecting circuit 10 which detects the predetermined time by the movement of the clock hands is cleared of noise; the signal which has had its wave form shaped by the switching circuit 11 is counted by the counting circuit 12; the input signal to the counting circuit is delayed; a number of pulses which are to be produced is controlled by comparing, in the comparison circuit 15, the output from the counting circuit 12 with the information memorized by the series of pulses producing circuit 13; the timing for the start of the pulses constituting the time indicating signal is set by the output of the delay circuit 14; the number of pulses to be transmitted from the start to the end of the time signal is memorized, and the number of pulses corresponding to time indicating signals equal to the numeral representing the time indicated by the short hand on the clock are produced as the output from the series of pulses producing circuit. Then, the time indicating signals produced as the output from the series of pulses producing circuit are converted into relaxation signals through the modulation circuit 16, and these signals are amplified, to produce the time indicating sound signal from the speaker 70.

Thus, the output from the time detecting circuit 10 is fed into the switching circuit 11 as its input; the output of the aforementioned switching circuit 11 is delivered to the counting circuit 12 and the delay circuit 14 as inputs thereto; the output from the counting circuit is supplied as one input to the comparison circuit 15, the outputs from the delay circuit 14 and the comparison circuit 15 are supplied as the inputs to the pulse producing circuit 13; the output from the pulse producing circuit 13 is supplied to the comparison circuit as a second input thereto and to the modulation circuit 16 as the input thereto; the output from the modulation circuit 16 is supplied to the amplifier circuit 17 as the input thereto, and finally, the output from the amplifier circuit is supplied to the input side of the speaker 70.

It is to be noted that SR's may be substituted for the F/F's shown in FIGS. 8 and 9.

FIG. 13 shows another embodiment of the present invention. Generally, a person becomes more sensitive to sound at night and there is a possibility the sound will be heard as a harsh noise. For this reason, the time indicating signal producing device of FIG. 13 is so constructed that a speaker is used as a time indicating signal producing means in the day time and a light producing means is used in place of the speaker in the night time.

In FIG. 13, the same numerals are used for to the same elements as in FIG. 9 so that the explanation of the functions of these elements is omitted.

Referring to FIG. 13, fixed terminals x.sub.1 and y.sub.1 of a switch SW.sub.1 are connected to the variable terminal of the variable resistance R.sub.7 and the output terminal of NA.sub.2, respectively. The movable terminal Z.sub.1 of the switch SW.sub.1 is connected to the base electrode of Tr.sub.4. Fixed terminals x.sub.2 and y.sub.2 of a switch SW.sub.2 are connected to one terminal of the speaker 70 and one terminal of a lamp 71, the other terminals of which are connected to V.sub.DD, respectively. The movable terminal Z.sub.2 of the switch SW.sub.2 is connected to the collector electrode of Tr.sub.5. A light detector x which is a main element of Cds, Se, or the like which has a characteristic that its internal resistance decreases when it is irradiated with light and an electromagnetic relay Ry which operates the switches SW.sub.1 and SW.sub.2 are connected in series between V.sub.DD and V.sub.SS terminals. In FIG. 9, the emitter electrode of Tr.sub.4 is connected to the collector electrode of Tr.sub.5, but in FIG. 13, the emitter electrode of Tr.sub.4 is connected to the V.sub.DD terminal.

In FIG. 13, when the light detector x receives light for example during the day time, current flows through the electromagnetic relay RY and the movable terminals Z.sub.1 and Z.sub.2 of SW.sub.1 and SW.sub.2 are connected to the terminals x.sub.1 and x.sub.2, respectively. Thus, when pulses are transmitted from the output terminal of NA.sub.2, the speaker produces an electronic sound. On the other hand, the light detector x does not receive light during the night time, so that movable Z.sub.1 and Z.sub.2 of SW.sub.1 and SW.sub.2 are connected to terminals y.sub.1 and y.sub.2 because the electromagnetic relay is not operated. Thus, when pulses are transmitted from the output terminal of NA.sub.2, the pulses are amplified by hfe.sub.4 x hfe.sub.5 by Tr.sub.4 and Tr.sub.5 and the lamp 71 turns on and off in accordance with the number of pulses.

Furthermore, shown in FIG. 14, as for a sound producing means, a bell may be used instead of the speaker. In FIG. 14, numeral 41 designates an electromagnet; 43 a hammer; 44, a spring, one end of which is connected to the hammer 43; and 46, a sound producing member which produces sound when struck by the hammer 43.

When time signal 45 is supplied to electromagnet 41, the hammer 43 strikes the sound producing member 47 when attached by the electromagnetic 41.

The shape and kind of the sound producing member 41 may be selected freely and a plurality of sound producing members which respectively have different frequencies may be also employed.

Further, in FIG. 14, although the sound producing member produces sound when the electromagnet attracts the hammer, the arrangement could be reversed so that when the hammer is released from the attractive force of the electromagnet, it strikes the sound producing member. The Effects of This Invention:

(1) As described hereinabove, the time signal clock of this invention is a clock capable of giving an accurate time indication by hands driven by electronic circuits, and in which a time indicating signal is produced at predetermined times without fail by means of a set of detecting means installed at a position corresponding to the time at which the time indicating signal is desired.

(2) Hitherto, with electronic clocks, only the visual sense has been usable as the means for perceiving time. By the present invention, the auditory sense has now been made usable for perceiving time, so that a person need not bother to observe his clock when he wants to have definite perception of time. The clock of the present invention can also be modified to give a visual indication of the exact time even in dark places, as at night.

(3) When applied to quartz clocks, the time signal functions may be provided easily without disturbing the visual image.

(4) The time signal circuit contains rather a small number of elements, and is amenable to being formed as an integrated circuit except for variable resistors R.sub.4, R.sub.7 and R.sub.8, condensers C.sub.2, C.sub.3, C.sub.5 and C.sub.6 and transistors Tr.sub.4 and Tr.sub.5. Accordingly, a clock capable of giving a time indicating signal can be made at a low cost merely by adding, as the time indicating signal mechanism, the detecting device including the magnetically sensitive switch, permanent magnet, etc., and the speaker, etc.

(5) Because the circuit is so composed that the time indicating sounds signal is produced with a frequency which is most comfortable to the human ears, and with a sustain or reverberation effect, easy auditory perception of time is possible even in a noisy environment.