US 4,096,567 AGrant
Information Storage Facility With Multiple Level Processors
Issue Date:1978-06-20
•8 Claims
•122 Drawing Sheets
Abstract
An information storage facility with multiple level processors for relieving one or more external host computers or intelligent terminals from conventional time consuming record searching functions, such as record formatting, indexing, buffering and the like. Three processor levels are provided: a communications level for handling external communications, a DBMS level for performing syntax scanning, hashing and coding/decoding routines, and data access functions e.g. indexing, searching, buffering, blocking, deblocking, storage management, and error recovery functions; and a storage level for performing data storage and retrieval, error recovery and storage device management. A direct memory access bus is also provided which enables high speed data transfer among the several processors included within the storage facility and also external host computers or intelligent terminals.
Metadata
Inventors
- William H. Millard
- Allan J. Killian
- Bruce A. Van Natta
Application Information
Application Number:US 7142129
Filing Date:1976-08-13
Priority Date:1976-08-13
Art Unit:237
Classifications
IPC:
G06F 1516G06F 1540G06F 1300
Field of Search:
340364172.5200 MS File
Patent Drawings (122 sheets)
Description
TABLE OF CONTENTS
Abstract of Disclosure
Background of the Invention
Summary of the Invention
Brief Descripton of the Drawings
Description of the Preferred Embodiments
General System Operation
Syntax
Commands and Responses
System Hardware
Processors
Mpu
Ram4
Prom4
P10
S10
Pic-8
Dmab
Detailed System Operation
Communications Level
Dbms level
Storage Level
System Software
Introduction
System Symbols/MACROS
Communications Level
Dbms level
Subroutines (all levels)
Storage Level
BACKGROUND OF THE INVENTION
This invention relates to digital information storage systems of the type accessible by a central processing unit.
Digital information storage facilities are known which are designed to store large quantities of information in digital form and which are normally accessible by a general purpose digital computer. In such systems, the digital information is typically stored on magnetic record media, such as disk packs or magnetic tapes and forms a data base of user information, such as inventories, payroll and accounting records, weather data, seismic data and the like. The storage facility is normally associated to a general purpose digital computer capable of extracting information from the record media, processing the extracted information and returning processed information to the record media.
In the past, all significant data processing functions have been performed in the host digital computer, and the information storage facility has functioned merely as a slave to the host computer or at best as a simple fixed location single key search, and has been provided with a functional capability of merely transferring information thereto. In a typical installation, the host computer is provided with a resident program for specifying the manner in which information is to be processed and, once operational, one or more application programs are performed step by step in the host computer until a step in a given program is reached which requires information from the storage facility. Thereafter, further activity in the specific program is terminated and the host computer transmits a request to the information storage facility to retrieve a first index block. That block of information is located and transferred to buffer storage in the host computer after which the computer searches for a reference, commonly termed a pointer. Once the pointer has been located, another index block is requested by the host computer and transferred from the storage facility to the host computer buffer storage, after which the second index block is searched for an additional pointer. This process continues for several iterations until the particular record block has been located in the storage facility and transferred to the host computer, whereupon the application program may be resumed. The application program then must extract the individual data item of interest. Each transfer of information between the host computer and the storage facility requires a high speed data path in order for the process to operate with some degree of efficiency, which in turn requires that the host computer be in close physical proximity to the information storage facility. This requirement of close physical proximity is inconvenient in some applications and totally undesirable in others.
An even greater disadvantage to known systems of this type is the fact that a large percentage of the functional capability of the host compouter is diverted from the execution of the application program, and thus wasted, due to the relatively large amount of computer time spent in obtaining a file, record or item from the information storage facility. As the size or use of the data base expands, the amount of host computer time spent on index retrieval and searching expands accordingly, which renders known systems of this type even more inefficient. While some information storage facilities have been designed for use with more than one host computer, such systems have not remedied the disadvantages noted above.
SUMMARY OF THE INVENTION
The invention comprises an information storage facility provided with plural levels of processing capability, which permits symbolic access by the host computer to information stored therein and frees the host computer to perform processing functions while information is being stored in and retrieved from the storage facility. In addition, the invention is entirely expandable and can be tailored to meet the exact requirements of any data base.
In its most general aspect, the system comprises three processing levels, viz. a communications level, a data base management system (DBMS) level, and a storage level, with the central DBMS level separated from the other two levels by a pair of shared memory units. Communications between processors and/or levels is accomplished via shared memories and/or Direct Memory Access (DMA) bus, which bus may optionally be controlled by a separate processor. In all implementations, the use of the DMA bus may be incorporated to supplant or supplement the use of shared memory. The communications level processor is configured to communicate with a host computer. an intelligent terminal or other processor devices on either a serial, parallel or DMA basis and performs all communication functions with such external devices, such as handshake, protocol and the like. The communications level processor exchanges information with the DBMS level processor by means of a first shared memory unit, and is dedicated to predetermined external processors. The storage level processor is configured to operate the associated storage devices, such as tape memory transport or, in the preferred embodiment, one or more disk storage devices and performs data storage and retrieval, error recovery and storage device management. The storage level processor communicates with the DBMS level processor via a second shared memory unit. The DBMS level processors are configured to perform syntax scanning functions and hashing and coding/decoding routines, as well as all data access functions including indexing, searching, buffering, blocking, deblocking, storage management, and error recovery functions.
The one or more processors at each of the three levels is also configured to perform mailbox routines whereby requests or responses are cached in the appropriate adjacent shared memory facility for use by one of the processors at the appropriate adjacent level. For example, a request from the communication processor to the DBMS processor is transferred via a mailbox in the shared memory unit coupled therebetween, while the request from the DBMS processor to the storage level processor is transmitted via a mailbox in the shared memory unit therebetween. In all cases describing messages, commands and/or data as moving via shared memory mailboxes, this implementation can be augmented or supplanted by use of a DMA bus facility, to move any of the above classes of information.
The system architecture is modular so that each processor level and each shared memory unit may be expanded or contracted as dictated by the requirements of any given application. Thus, the system can grow along with an expanding data base or an expanding number of external processor devices by simply inserting additional processor and/or shared memory modules.
In operation, each processor at each level is continuously searching for a task to perform. When an incoming message is received, it is acknowledged by the communications level processor associated to the particular external processor at which the message originated, processed into a DBMS level request and placed in a mailbox in the shared memory unit juxtaposed between the communications level and the DBMS level. The cached request is fetched from that mailbox by a DBMS processor which translate the request into DBMS routines necessary to perform the tasks inherent in the originally received message. The tasks required at the storage level are placed in a mailbox in the shared memory unit juxtaposed between the DBMS level and the storage level. The storage level processor fetches these tasks and directs the required operation of the data storage devices associated thereto. Informaton flow from the storage level to the communications level proceeds in reverse fashion.
Each processor at each level is provided with a resident program preferably stored in a programmable read only memory (PROM) for supervising and directing operations thereof. The communications level processors are additionally provided with both serial and parallel input/output devices to permit communication with external processors, which may be remote or proximate; while the storage level processors are each associated to a storage controller, such as a disk controller to permit data storage and retrieval, as well as error recovery and disk management.
For a fuller understanding of the nature and advantages of the invention, reference should be had to the ensuing detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a general system block diagram illustrating the invention;
FIG. 2 is a block diagram of a microprocessor unit;
FIGS. 3A-E and 4A-F are circuit schematics of the microprocessor unit and RAM memory units, respectively;
FIG. 4G is a diagram of a jumper socket for the RAM of FIG. 4;
FIGS. 5A-E are circuit schematics of the PROM unit;
FIGS. 5F and G are jumper diagrams for the FIG. 5 PROM unit;
FIGS. 6A-E are circuit schematics of the PIC 8 unit;
FIGS. 6F-H are jumper diagrams for the FIG. 6 unit;
FIGS. 7A-G are schematic diagrams of the SIO unit; FIGS. H-Q are jumper diagrams and illustrative examples illustrating connections for the FIG. 7 SIO unit;
FIGS. 8A-E are schematic diagrams of the PIO unit;
FIGS. 8E and G are jumper diagrams for the FIG. 8 unit;
FIGS. 9A-E are schematic diagrams of the optional controller panel assembly;
FIG. 10 is a block diagram and FIGS. 11A-E, 12A-D, 13 and 14A-E are circuit schematics illustrating a shared memory unit;
FIGS. 15-22 are circuit schematics showing the disk controller TIFA unit;
FIGS. 23-30 are schematic diagrams illustrating the disk controller TIFB unit;
FIGS. 31-47 are flow charts for all three processor levels of the system;
FIGS. 48 and 49-51 are a block diagram and detailed diagrams, respectively, of a disk controller unit;
FIG. 52 is a circuit schematic of the CRC circuitry;
FIGS. 53 and 54 are illustrative memory maps; and
FIGS. 55-75 are detailed and schematic diagrams illustrating the DMAB unit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
GENERAL SYSTEM OPERATION
Initially it is noted that the terms STORAGE LEVEL, MEMORY LEVEL, and DISK LEVEL have equivalent meaning in the ensuing description. Further, in all implementatons, the movement of messages, data, or commands may be accomplished via a DMA bus facility in lieu of or in addition to a shared memory. Such DMA buses may be used to connect processors, levels, shared memories (if any) and one or more external computers, terminals, modems, or communications line interface devices.
Turning now to the drawings, FIG. 1 is a generalized system diagram illustrating the preferred embodiment of the invention. As seen in this FIG. the system includes a communications processor level comprising a plurality of microprocessors, 10, 11 each dedicated to a different group of external processor units, such as a host computer 12 and an intelligent terminal 13, as well as a modem 14 for permitting remote communication. Each communications microprocessor is configured in such a manner as to be capable of both serial and parallel information transfer with units 12 and 13. Also included in the system is a direct memory access bus (DMAB) 15 controlled by a separate processor 16 for enabling high speed data transfer of large blocks of information between host computers 12, 12' and the data storage devices described below.
Each communications microprocessor 10, 11 is coupled to a shared memory unit 20 termed an expandable cache memory. Memory unit 20 is shared with a plurality of DBMS level microprocessors 21-24, each of which is also coupled to a second shared memory unit 25. Memory unit 25 is shared with a plurality of microprocessors 26, 27 at the storage level, each of which is coupled to an associated data storage device 28, 29, respectively and data storage device controller 30, 31, respectively. In the preferred embodiment, the data storage devices 28, 29 are disk storage devices of conventional design; however, other types of data storage devices may be employed as desired, such as magnetic tape devices or the like.
General system operation proceeds as follows. With the system in operation, processors 10, 11 continuously look for incoming messages, processors 21-24 look for tasks from shared memory unit 20 and results from shared memory unit 25, while processors 26, 27 look for tasks from shared memory unit 25. When an incoming message is received by processors 10, 11, it is error checked, acknowledged and passed on to a mailbox in shared memory unit 20. The first processor of the processor group 21-24 which tests the filled mailbox assumes responsibility for performance of that task. If processor 22, for example, assumes responsibility of the particular task, it communcates to the appropriate disk control processor 26 or 27 via one or more mailboxes in shared memory unit 25 until the task is completed. Once the task is completed, an appropriate message is transferred back to the mailbox in shared memory unit 20 by the responsible processor 22, after which the message is fetched by the communications processor 10 or 11 and transmitted to the external processor.
To summarize, the communications level microprocessors perform line handling functions, error routine and mailbox routines; the DBMS level processors handle the syntax scanning funtions and hashing and coding/decoding routines, all data access functions including indexing, searching, buffering, blocking, deblocking, storage management, and error recovery functions. In addition, the DBMS processors handle read/update, add/delete, lock/unlock, save/restore, index, and mailbox routines. The disk control processors 26, 27 handle disk management read/write, error recovery, and mailbox routines.
At the communications level, messages are handled by communications service routines which buffer a message and handle all the protocol with regard to the message. The message is then passed via a mailbox routine and shared memory unit 20 to the DBMS level. The DBMS level examines the message, checks syntax, converts symbolic names to 3-byte internal codes, determines the appropriate command routine and executes that routine using various utility subroutines. The command routine causes information to be read or written from the data storage disks 28, 29 by sending messages through the mailbox routine and shared memory unit 25 to the disk control level processors 26, 27. Upon receiving the required information or completing the required task, the DBMS level processor then sends a message or messages to the communications level which then sends these messages back to the external device which initiated the command.
Both serial and parallel interfaces are provided between the communications level processors 10, 11 and the external devices. Message protocol for either serial or parallel mode comprise an ACK-NAK handshaking sequence. Each character or a received message is checked for parity errors and the entire message is checked against the check sum contained in the message as transmitted. If there is a parity error of if the calculated check sum does not match the check sum received with the message, a NAK message is returned to the sender who may then repeat the message. The reception of a NAK is an indication that the receiver denies all responsibility for the message and stores no information about the message. If there are no parity errors and the check sum matches, an ACK is returned signifying that the receiver has taken responsibility for the message.
It should be noted that the handshaking sequence may be modified by providing automatic time-out routines which assume reception of a NAK message upon expiration of a predetermined time period. Further, other standard message protocols may be employed, as desired.
SYNTAX
Command syntax is as follows:
COMMAND, COMMAND ID, ARG 1, ARG 2, ARG 3, ARG 4 where the command is a string of characters, e.g. UPDATE or LOCK. COMMAND ID is a user selector identifier used to identify the command and is returned with the response. COMMAND ID may be the null string, i.e. may be missing. However, the delimiter following COMMAND ID must be present. The arguments to a command are character strings separated by commas (or any non-alphanumeric character). In any argument position where a symbolic file, record or item name can be used, a number can be used to refer to a file, record or item by its sequential position rather than its name.
Response syntax is as follows:
COMMAND ID, TRANSACTION #, ERROR CODE, DATA where TRANSACTION # is the unique string of digits used to identify a transaction for use in reprocessing transactions during recovery from a problem. A TRANSACTION # is returned only for operations which involve modification of the data storage disk, i.e. disk 28 or 29. COMMAND ID is the command identification in the command which invoked this response. An ERROR CODE which identifies the error type and location is returned if an error occurs at any level. If no error occurs, the delimiters are still present but the error code is not. Data can take one of several forms depending on the command executed. For example, if the command caused the return of an item, the data will simply be that item value. If the command caused the return of a record, the data will have the format:
ITEMNAME L ITEMVALUE
where ITEMNAME is the internal three-byte code for the item name, L is the length 0 to 127 of the item value and the ITEMVALUE is simply the itemvalue as referred to above. If the command causes return of a file, the data will have the format:
RECORDNAME L RECORD RECORDNAME L RECORD
where RECORDNAME is the internal three-byte code for the record name, L is the length of the record and RECORD is the record in the same format as immediately above. If the command causes the return of a sector off data storage disk 28 or 29, the data will be in exactly same form as it existed on the disk.
Response messages are returned 128 bytes of data at a time. If a response requires more than one message, then more than one message is returned.
The COMMAND ID is included in every message. The last message of a series of messages in response to a command contains and end-of-response indicator: a transaction number of 1.
Commands and Responses
Update: the UPDATE command has the form:
UPDATE COMMANDID, FILENAME,RECORDNAME,ITEMNAME,DATA and results in the specific item having a value of DATA. If the file, record or item mentioned in the command does not exist, it is added to the data
The response to this command is:
COMMANDID,TRANSACTION#,ERRORCODE
If updating a record or file is required, then only FILENAME, RECORDNAME or FILENAME are given. The data must be in the proper format as noted above.
Errors that may occur other than standard internal errors are:
Item is locked
record is locked
file is locked
read: the READ command has the form:
Read commandid,filemane,recordname,itemname
and results in the return of the item's value as previously set by an UPDATE command.
The response format is:
Commandid,errorcode,data
if reading of a record or file is required, then only FILENAME, RECORDNAME or FILENAME is specified. The data will have the form noted above.
Errors that may occur other than standard internal errors are:
File is locked
record is locked
item is locked
file is non-existent
record is non-existent
item is non-existent
get: the GET command has the form:
Get commandid,diskid,trackid,sectorid
the result is the return of the data on the track and sector on the disk mentioned. It is in the form:
Commandid,errorcode,data
the data is the exact data that resides on the disk in that sector. Errors that may occur other than standard internal errors are:
Disk does not exist
track does not exist
sector does not exist
put: the PUT command has the form:
Put commandid,diskid,trackid,sectorid,data
the result of this command is the writing on the disk of the data in the specified place.
The response has the form:
Commandid,transaction#,errorcode
other than standard internal errors the only errors possible are:
Disk does not exist
track does not exist
sector does not exist
sector not allocated by a request command
request: the REQUEST command has the form:
Request commandid,diskid,trackid,sectorid
the result of a REQUEST command is the return of a TRACKID and SECTORID near the specified track or sector on a specified disk and the marking of that track and sector as allocated for user use.
The response format is:
Commandid,transaction#,errorcode,diskid,trackid,sectorid
the only errors other than standard internal errors are:
No more sectors on disk
disk does not exist
track does not exist
sector does not exist
return: the RETURN command has the form:
Return commandid,diskid,trackid,sectorid
the result of the RETURN command is the deallocation for user use of the specified sector.
The response format is:
Commandid,transaction#,errorcode
the only errors other than standard internal errors are:
Not an allocated sector
disk does not exist
track does not exist
sector does not exist
lock: the LOCK command has the format:
Lock commandid,filename,recordname,itemname
the result of the LOCK command is that an item (record or file, if only record or file is specified) is locked and unavailable for reading or updating by any other terminal. The item remains locked until an UNLOCK command is given for that item, record or file.
The response format is:
Commandid,transaction#,errorcode
other than standard errors, the only errors are:
File locked by another terminal
record locked by another terminal
item locked by another terminal
file non-existent
record non-existent
item non-existent
unlock: the UNLOCK command has the form:
Unlock commandid, filename, recordname, itemname
the result of the UNLOCK command is that the file, record or item is unlocked only if the file, record or item was previously locked by the same terminal now originating the UNLOCK command. The response format is:
Commandid,transaction#,errorcode
other than standard internal errors, the only possible errors are:
File locked by another terminal
record locked by another terminal
item locked by another terminal
file non-existent
item non-existent
file is not locked
record is not locked
item is not locked
name: the NAME command has the form:
Name commandid,filename,recordname,itemname
this command returns the symbolic name of the item specified or of the file or record specified if the FILENAME,RECORDNAME or FILENAME is given. Normally, the NAME command is only used when a sequence number is in place of ITEMNAME or when sequence numbers are used in place of ITEMNAME and RECORDNAME or when the sequence numbers are used in place of FILENAME,RECORDNAME or ITEMNAME.
The response is:
Commandid,,errorcode,data
where DATA is the symbolic name being returned.
The only errors other than standard internal errors are:
Filename does not exist
recordname does not exist
itemname does not exist
add: the ADD command has the form:
Add commandid,filename,recordname,itemname
the result of the ADD command is the addition of the item to the data base. If only the file and record names are specified, the result is the addition of only the record to the data base. If only FILENAME is specified, only the file is added to the data base.
The response is:
Commandid,transaction#,errorcode
in the case where file, record and item are specified, the only errors are:
File does not exist
record does not exist
in the case where only file and record are specified, the only error is:
File does not exist
in the case where only file is specified, only standard internal errors are possible.
Delete: the DELETE command has the form:
Delete commandid,filename,recordname,itemname
the result is to delete the item from the data base. In the case where only FILENAME and RECORDNAME are specified only the record is deleted. If FILENAME is only specified, then the file is deleted. When none are specified, the entire data base is deleted. The response is:
Commandid,transaction#,errorcode
the only possible errors, other than standard internal errors are:
Record does not exist
file does not exist
item does not exist
copy: the COPY command has the form:
Copy commandid,diskid1,diskid2
the result of this command is the copying of the entire contents of disk 1 onto disk 2, destroying any data formerly residing on disk 2. This is a straight copy and involves no reorganization of the data. The response is:
Copy commandid,disk
commandid,transaction#,errorcode
the only error other than standard internal errors is:
Disk does not exist
the following are several elementary examples illustrating the use of various of the commands available in the system of FIG. 1.
Each command, as given in this section, will assume, unless otherwise stated, that all previous commands in this section have been executed and all previous explicit assumptions about what exists in the disk data base apply.
Assuming that there are 3 files in the disk data base (PAYROLL, ACCOUNTS RECEIVABLE, and INVENTORY) and there are two terminals connected to the data base (Terminal 1 and Terminal 2), and assuming that the PAYROLL file has a record in it by the name of GEROGE-ALLEN and that the record now has no items in it, a message from Terminal 1 such as:
Update d1,payroll, george-allen,payrate,7.39
would invoke a response from the system of:
Cmd1,473652,,
where CMD1 is the COMMANDID from the command, the 473652 is the TRANSACTION# and the two commas at the end indicate there was no error. The result of the command is that the PAYRATE item was added to the GEORGE-ALLEN record of PAYROLL and received an item value of 7.39. If, later, a message is sent such as:
Update payroll,george-allen,payrate,1.21
the response would be:
,4736700,,
Note that there is no COMMANDID in the response although the delimiter comma is there and that the TRANSACTION# is larger than the previous TRANSACTION#. This command results in the changing of the item value from the previous value of 7.39 to 1.21.
Now, if the message
Namex531,payroll,george-allen,1
was sent, the response would be
X531,,,payrate(5a274b)
the X531 is the COMMANDID, there is no TRANSACTION# or ERRORCODE and the data returned is PAYRATE, the symbolic name of item 1 is the GEORGE-ALLEN record. The 5A274B in parentheses is the hexadecimal representation of the 3-byte internal code. Now, a command
Read payroll,george-allen,payrate
would invoke the response
,,,1.21
as the COMMANDID is null, there is no TRANSACTION# and no errors. Note that the delimiter after the null command in the READ command is a space. If the LOCK command is now performed:
Lock xx, payroll
the response
Xx,47398,,
is received and the PAYROLL is locked and no terminal may access it except the terminal that gave the LOCK command. The PAYROLL updating program might use this command to prevent access to the PAYROLL file by any other terminal. Now a command
Delete foo,payroll
would result in a response
Foo,7file is locked
where the 7FILE IS LOCKED indicates that the file is locked, and therefore cannot be deleted. To delete the PAYROLL file, it would be necessary for TERMINAL 1 (which issued the LOCK command) to issue the command
Unlock payroll
which will receive the response
,475411,,
The PAYROLL file would then be unlocked and available for deletion. Even if only a single record was locked within the PAYROLL file, the file could not be deleted because deletion of a locked record is not permitted. Of course, deletion of a locked item or file is not permitted either.
A series of commands might be issued at this point to back up the entire data base. Assuming a two-spindle configuration with two disk packs to be backed-up, the operator would place the first pack to be save on DRIVE1 and a fresh pack on DRIVE2. The command
Copy drive1, drive2
would be issued to copy the contents of the pack on DRIVE1 to the new pack on DRIVE2. The DRIVE1 (old) and DRIVE2 (new) packs would then be set aside. Then, the second pack to be backed-up would be placed on DRIVE2 with a fresh pack placed on DRIVE1. The command
Copy drive2,drive1
would then be issued to copy the contents of old pack DRIVE2 onto new pack DRIVE1. The new pack DRIVE1 would then be set aside and the first pack to be copied would then be replaced on DRIVE1. The result is that the copies of the two packs would be shelved (labeled as, for instance, COPY1 and COPY2) and the two original packs would then be in position on their respective spindles ready for further commands. Another command which may be issued by a systems program run on one of the terminals is:
Get drive1, track17,sector25
and the response would be
,,,(string of data)
The string of data would be the contents of a particular sector. This command could be issued for any sector on the disk.
A corresponding PUT command attempting to write on a given sector on the disk would not be permitted as no REQUEST command had been executed to gain excess to a particular sector and make it available for PUT usage.
The following shows how several commands can work together to produce the desired result. The example chosen is an algorithm for listing the entire contents of a data base in a very structured manner.
The format that the data base lister will use is:
(1) FILENAME1(1C)
(1) recordname1(1c)
(1) itemname1(1c) itemvalue
(2) itemname2(1c) item value
(3) . . .
(n) itemnamen(1c) itemvalue
(2) recordname2(1c)
(1) itemname1(1c) itemvalue
(2) itemname2(1c) itemvalue
(3) . . .
(n) . . .
(3) . . .
(n) . . .
(2) filename2(1c)
(1) . . .
(1) . . .
(n) . . .
(n) . . .
(3) . . .
(n) . . .
the data base lister will be presented as an algorithm rather than a program. The particular operations in the algorithm such as OUTPUT, INPUT and PRINT will not be strictly defined. In particular, OUTPUT will mean output from the external device to the system, a string or a command; INPUT will mean the data received from one of these commands; and PRINT will mean to print on a lineprinter associated to the external device lineprinter the string following that. Other operations, such as DO will assume their normal meanings.
The Data Base Lister is as follows:
To summarize, the required commands are as follows:
SYSTEM HARDWARE
The system hardware is fabricated primarily from commercially available units, subunits and components and FIGS. 3-30, and 55-75 are schematic diagrams illustrating the preferred embodiment of the invention.
Processors 10, 11 21-24, 26 and 27 are preferably designed around the Intel Model 8080A microprocessor chip, and the basic processor is shown in FIGS. 2-6. FIGS. 7 and 8 show the serial and parallel interface subunits employed with processors 10, 11.
Shared memory units 20, 25 are each arranged in the manner shown in FIG. 10 and comprise random access memory 41, at least one transfer switch unit 42 and a controller 43. Access to the RAM memory 41 is via switch unit 42 under control of the controller unit 43 and information is transferred to and from RAM memory 41 via bidirectional data buses 44, 45 coupled to upper and lower level processors respectively. For example, for the RAM memory 41 located in shared memory unit 20, buses 44 and 45 are coupled respectively to communications level processors 10, 11 and DBMS level processors 21-24, respectively. Transfer switch unit 42 is shown in FIG. 11, while controller 43 is shown in FIG. 12. FIG. 13 illustrates representative termination networks.
Not illustrated in FIG. 10, but located at the microprocessor end of data buses 44, 45 is a buffer unit shown in detail in FIG. 14.
Disk controllers 30, 31 each comprise two separate boards termed T1FA, T1FB which are illustrated in detail in FIGS. 15-22 and FIGS. 23-30, respectively. Disk controllers 30, 31 are specifically designed to interface with a TRIDENT disk drive manufactured by CalComp Inc. PROCESSORS-MPU
The MPU-A board (FIGS. 3A-E) is the processor board for all MPUS in the System.
The 8224 clock driver chip and an 18 Megahertz crystal are used to generate the 2-phase, 2 Megahertz non-overlapping clock for the 8080A. An 8212 is used as a latch for the status signals and two 8216 tri-state bi-directional bus drivers are used to interface the 8080A with the input and output data buses. All other address, status, and control lines are driven by tri-state bus drivers.
Unregulated +16, -16, +8 volts, and ground must be supplied to the bus. On-board regulation is used to arrive at the power supply levels needed to run the chips. Integrated circuit power regulators with overload protection are used. The board is supplied with ample bypass filtering using both disc ceramic and tantalum capacitors.
Power-on reset is included on this board along with pull up resistors for all inputs required so that the power-on reset will start the program at position 0 out of a ROM. The MPU-A board provides interfacing between the 8080A chip and the data and address busses, clock and synchronization signals, and the voltage regulation necessary for the 8080A and other chips. The internal functioning of the 8080A is well known.
The address lines from the 8080A drive the address bus on the back plane through 8T97 tri-state buffer drivers. These drivers may be disabled through the ADDRESS DISABLE line on pin 22 of the back plane. Intel 8216 bi-directional bus drivers connect the 8080's bi-directional data bus to the back plane's dual uni-directional DATA IN and DATA OUT busses. The direction of data transmission is determined by the DIRECTION ENABLE line. The DIRECTION ENABLE line is in turn controlled by the front panel and the processor status signals DATA BUS IN and HALT ACKNOWLEDGE. The 8216 can be disabled by the DATA OUT DISABLE line on pin 23 of the back plane.
The 8080A's bi-directional data bus is also connected to the data bus socket and the 8212 status byte latch. The data bus socket is used to connect the front panel to the bi-directional bus, while the 8212 latch transfers the status byte to the back plane via 8T97 drivers. These drivers are disabled by the STATUS DISABLE line on pin 18 of the back plane. The 8212 is latched up by the STATUS STROBE signal of the 8224 clock chip to store the status information for each instruction cycle.
One K pullup resistors to +5 volts are connected to all the bi-directional bus lines to ensure that during the time the bus is not drive, the 8080A reads all 1's.
The 8224 clock chip and crystal oscillator, provide the two-phases non-overlapping 2 MHZ system clock for the 8080A. These clocks are also driven onto the back plane through 8T97 tri-state buffered drivers. The CLOCK line on the back plane is driven from the TTL Phase II clock line through a delay. Six sections of a 7404 are used for this delay to provide greater simplicity and higher reliability than a one-shot. The 8224 chip also provides the power-on reset function through use of a 4.7K resistor and 33 ufd capacitor connected to the reset input of the 8224. The power-on reset is applied to the 8080A and is applied to the POWER ON CLEAR line, pin 99 on the back plane.
The two BACK PLANE READY signals are ANDed and connected to the 8224 for synchronization with the Phase II clock before being connected to the 8080A chip. The INTERRUPT line is connected directly to the 8080A, while the HOLD REQUEST line is synchronized with the Phase II clock and then connected to the 8080A.
The six processor status signals (sync write, STROBE DATA BIT IN, READ STROBE, INTERRUPT ENABLED, HOLD ACKNOWLEDGED, and WAIT ACKNOWLEDGE) are all driven onto the back plane through 8T97 tri-state buffered drivers. These drivers may be disabled by the CONTROL DISABLE line, pin 19 on the back plane.
The +5 volts is regulated from the +8 volts by a 7805 integrated circuit regulator, while the -5 volts is regulated by a 5 volt zener and a 470 ohm resistor from the 16 volt bus. The +12 volts is regulated by a 12 volt Zener and connected to the +16 volt line by two 82 ohm 1/2 watt resistors in parallel. All voltages are filtered with 0.33 microfarad tantalum and disc ceramic capactors.
Ram 4
the RAM-4 board (FIG. 4) provides up to 4K bytes of static random access memory. Designed to utilize the Intel 2111 or 8111 chips, the RAM-4 board can be flexibly configured to contain up to 4K bytes in 256 byte increments. The board address can be switch-or jumper-selected to any 4K block of the computer's 64K memory space. Either of the Intel 8111 or 2111 devices can be used on the RAM-4 board. The board has provisions for the use of standard as well as selected (high speed-450 n.s.) 8111 memories. Special circuitry allows extra delay time (1 extra cycle) for use by the slower memory. The memory units provided with the RAM-4 board are 450 n.s. 8111's requiring 0 wait cycles.
The RAM-4 also features write-protect, a capability useful in the development and debugging of programs. Four separate write-protect switches are provided on the RAm-4 board, each controlling a separate 1K of memory.
The MPU-A board requires no jumpers or user options for its use. The board is ready to function after connection to the back plane and the bi-directional bus. The bi-directional bus lines are provided by a 16-conductor cable from the CPA board, connected via a 16-pin DIP plug in location A-10.
The clock crystal frequency is 18 megahertz, and the 8224 device derives from this 18 MHz signal the necessary 2 MHz two-phase non-overlapping system clock. These 2 MHz clocks are brought out onto the back plane for use by other system boards.
The RAM-4 board has space for 4K bytes of memory which consist of 32 chips of Intel 8111 or 2111 type random access memory organized 256 words .times. 4 bits wide in each chip.
These RAM devices are arranged on the board in a 2.times.N (1.ltoreq.N.ltoreq.16) array, with the top row A containing bits 0, 1, 2, 3, of all the data and Row B contaning bits 4, 5, 6, and 7 of all the data. Read/write and address control is provided by a support network of Gates (C8, C9, C13) and a Decoder (C10). Bi-directional tri-state bus drivers (C15, C16) are used to receive and transmit data to and from the System bus.
To beging the Read or Write Cycles, the board must be enabled. As shown in the schematic, the board enable is produced by an 8-input NAND (741s30 in position C13). Four of the NAND inputs are the jumper selected board address bits (A12, A13, A14, A15 or complements), and the remaining two are the inverted status bits SINP and SOUT. When the board is properly addressed, the NAND output is driven low. The 8205 1-of-8 decoder is then enabled, addressing a particular memory chip pair uniquely determined by the states of A8, A9, A10 and A11.
The 8T97 bus driver (C14) is also driven by the NAND (C13). When the input to the 8T97 is the signal, PWAIT, a cycle delay for the slower memory is produced by this buffered driver. When sufficiently fast memory chips are used, the input to this gate should be connected to the tie 5 line so that the processor gets a ready signal immediately upon the board enable and does not wait one cycle. The tie 5 line appears on C10 Pin 6 and is simply a high logic level provided through the 1K resistor to +5 volts. Also enabled at this time are the 8216, (C15, C16) tri-state bi-directional bus drivers.
The direction of data flow is determined by the 7402 in position C8 which when low selects a data path going from the 8080 data bus to the RAM-4 board's data bus. This is made low by either the memory write line from the control panel or the complement of the memory read status signal from the processor. Thus for normal operation, witht the machine running, the status signal memory read determines whether these data bus drivers are driving to the 8080 data-in bus or are receiving inputs from the 8080 data-out bus. In addition to selecting the direction of data flow thru the bi-directional data bus drivers, the direction control signal is also inverted and applied to the output disable pin on the 8111's so that during writing the 8111 is receiving data on its bi-directional data pins and not attempting to drive. The write strobe is applied to the 8111's thru a 4 section data out DIP switch which enables the programmer to turn off the write pulse for each K for debugging purposes. When the machine is running normally, the write strobe comes from the processor write strobe line (pin 77 on the back plane) and when the front panel is being used, the write strobe line comes from the front panel on the memory write line (pin 68 on the back plane.) Two other sections of the 7402 are used to take either one of these write strobes and buffer them to drive the memory chips.
The RAM-4 board uses Intel 8111 or 2111 memory chips which are organized 256 .times. 4 bits so that the minimum increment possible in the memory space is 256 .times. 8 .times. 8 bits or an increment of 256 bytes which consists of 2 memory chips.
The board is organized so that the appropriate low and high order bits are always in the same column. The positions are arranged in ascending order according to address, starting from column 1 thru column 16. Thus, while a 4K board has column 1 thru 16 all full, a 2K board which uses the lower 2K of the 4K memory space, would have columns 1 through 8 filled and a 1K board that uses the lower 1K of the memory space in the 4K board would have column 1 thru 4 filled.
It should be remembered that each position (A1-16, B1-16) represents a unique address, and that Row A contains bits 0-3 of all data, while Row B contains bits 4-7 of all data. Thus, the user has several options as to the possible structure of his memory space. For example, if a user desired a 512 byte memory, and, additonally, wanted those 512 bytes in the lower half of the 3rd K, he would place his memory chips in positions A9, A10, B9 and B10.
If in some column only one chip of the A-B pair is present, the appropriate position of the byte (A-0, 1, 2, 3, or B-14, 5, 6, 7) does exit in memory. The upper and lower byte portions are all independent, and the absence or presence of a chip in any position does not effect the operation of any other chip.
The section write/protect switch is located between the power regulator heat sink and the left edge of the board. Each section of this switch affects 1K out of the 4K memory space on the board, and corresponds with the order of the memory chips on the board. That is, switch pole 1 controls wrting in the lower 1K of the board, (columns 1 thru 4) and switch pole 2 controls writing in the second 1K block on the board, (columns 5 thru 8).
In order to write, these switches must be on. After a trial program has been written into memory, the appropriate switch may be placed off (without interrupting the power) and the program or panel will be unable to write into that block of memory. The data remains in memory, and reading from memory is not affected. This feature is very useful for debugging programs or when it is desired to run a program but eliminate any possiblity that mis-programming will cause any of the program to be over-written.
It is suggested that pins 9, 11, 13 and 15 be used to input as desired either a 0 or a 1 from the address bits so that for any address bits desired to be O, the jumper will extent directly across the header and for any address bits desired to be 1, the jumper will extend diagonally across the header. For instance, if A15 were to be 1, the jumper would extend from pin 7 to pin 9. This makes it easy to visually tell what address the board is jumpered for. An example jumper for the address block beginning with the address C hex is shown in FIG. 4G.
The board address select jumper location is C11. It permits any one of the 16 possible 4K blocks of memory space to be jumpered to form the board enable.
The jumper location accepts a standard 16 pin IC socket and the jumpers can be soldered on to a header which can be plugged into the socket and changed easily without any resoldering from the board.
Address bits 12, 13, 14 and 15 are available on pins 1, 3, 5, and 7 and their respective complements on pins 2, 4, 6 and 8. These signals should be jumpered to the input of the board select circuitry which appears on pins 9 thru 16. An 8 position DIP switch similar to that used for write enable may be inserted into this location should very frequent changes of address be desired. For a board whose address is expected to remain the same, jumpers may be inserted directly on the board. PROM-4
The PROM-4 board (FIGS. 5A-E) provides up to 4K bytes of non-volatile read-only assembly. Designed to utilize the Intel 1702 or 8702 read-only memory devices, the PROM-4 board may be flexibly configured to contain up to 4K bytes in 256 increments. The board address can be switch or jumper-selected to any 4K block of the computer's 64K memory space.
The PROM-4 board provides sockets for 16 1702 or 8702 PROMS. The socket locations are marked for easy selection of PROM addresses. A user-selectable memory read delay feature allows efficient use of fast or slow PROM devices. Two on-card regulators provide the +5 and -9 volts required by the 8702-1702 chips.
The PROM-4 board provides up to 4K of addressable Read-Only-Memory, utilizing the Intel 8702-1702 PROM devices. The board contains 256 bytes of memory for each 8702-1702 chip installed.
Address lines A0 through A7 are run directly to all PROM positions to select one o the 256 internal byte positions, while address lines A8 through A11 are used to select and enable one particular PROM Position through 8205 decoders. Address lines A12 through A15 are jumper-selected to determine the board's enabling address.
The board is enabled when the 74LS30 NAND (Cl) inputs are all high, namely when the selected address appears on the address bus, and the Status line SMEMR is high. The Processor Ready line is controlled by a 74195 shift register via an 8T97. The 74195 provides a user-selected memory read delay, selectable with jumpers in the delay select socket. The 74195 shift register is reset on the rising edge of the inverted Board Enable (BDENA) signal.
When addressed and enabled, an 8702-1702 PROM puts out its data on the D0 through D7 lines. The data output lines of all PROMS are tied to these lines, and these lines are buffered via 8T97 sections to th DI0 through D17 back plane bus lines.
Power for the card logic is provided by a +5 volt regulator and a -5 volt regulator-4 volt zener combination to yield +5 and 31 9 volts. Tantalum and disc ceramic by-pass capacitors eliminate noise from the power distribution busses.
In the PROM-4 board the minimum increment possible in memory space is 256 bytes or 1 8702-1702 chip. The board is designed to contain up to 16 8702-1702 devices, which is the full 4K of PROM. Each of the 16 PROM sockets has its own unique address, and each PROM operates independently of any other PROM. Thus, the user may structure his memory space in any way desired merely by placing his PROM(s) in the desired location(s).
The PROM-4 board is structured so that the memory address corresponds to a physical location on the board. The PROM sockets are arranged in a 2 .times. 8 rectangular array, and a particular PROM socket is addressed by address bits A8, A9, A10 and A11. A particular byte in the selected PROM is addressed by address bits A0 through A7. The sockets are labeled LOW 1 through 8 and HIGH 1 througgh 8, and the following shows the relationship between address and selected socket.
The delay jumper socket (C9) of the PROM-4 board allows selection of the one of four possible memory read cycle delays. The available delay times are 0, 1, 2 or 3 machine cycles, which translates to 500, 1000, 1500 and 2000 nanoseconds. This read cycle delay is necessary to insure the data from PROM is correct before transmission to the data bus. Most 1702-8702 chips available are either 1000 or 1500 nanosecond access time chips. The chips provided by IMSAI with the PROM-4 board are 1000 ns access time devices. After determining the access time of the slowest PROM on the board, the user should jumper the delay socket to produce that necessary delay.
The following is a list jumper pin numbers for the possible delays. In all cases, jumper the selected pin to pin 16.
The example shown in FIG. 5F is jumpered to a 1000 ns delay.
The board address select jumper location is C2. It permits any one of the 16 possible 4K blocks of memory space to be jumpered to form the board enable.
The jumper location accepts a standard 16 pin IC socket and the jumpers can be soldered onto a header which can be plugged into the socket and changed easily without any resoldering from the board.
After selecting a board address, the user must properly jumper the socket. Very simply, to enable the board, all address inputs to the NAND gate must be high. Therefore, any address bit not a 1 at the selected address should be inverted before connection to the NAND input.
Address bits 12, 13, 14 and 15 are available on pins 1, 3, 5 and 7 and their respective complements on pins 2, 4, 6 and 8. These signals should be jumpered to the input of the board select circuitry which appears on pins 9 through 16. An 8 position DIP switch similar to that used for write enable may be inserted into this location should very frequent changes of address be desired. For a board whose addrss is expected to remain the same, jumpers may be inserted directly on the board.
It is suggested that pins 9, 11 13 and 15 be used to input as desired either a 0 of a 1 from the address bits so that for any address bits desired to be 0, the jumper will extend directly across the header and for any address bits desired to be 1, the jumper will extend diagonally across the header. For instance, if A15 were to be 1, the jumper would extend from pin 7 to pin 9. This makes it easy to visually tell what address the board is jumpered for.
An example jumper for the Address Block beginning with the Address C hex is shown in FIG. 5G.
Pio
the PIO board (FIGS. 8A-E) provides for up to four input and four output ports of eight bits each parallel input and parallel output. Each input and each output port has it own latch and both input and output latches are provided with hand-shaking logic for conventional eight bit parallel transfers.
the handshake logic on any input or output logic port will generate an interrupt. The priority level of the interrupt is selectable. The address of the four ports is four sequential addresses, and this block of four addresses may be jumper-selected to be any block of four sequential addresses in the 256 I/O address space. The board may also be addressed with memory-mapped I/O, in which case normal memory read or write instructions are used to read or write data to the Input/Output ports. When using memory-mapped I/O, board addressing is done by selectable jumpers for the lower byte of address and the upper byte of address is hex FF or octal 377.
Provision is made for each of the four output ports to drive eight LED's for a total of 32 on-board LED's.
This feature can be used to provide program-controlled output for dedicated processor applications in which case this PI0 board would be plugged in where the front panel would normally be mounted and a special photographic mask made to put in front of it with the appropriate labels for the specific purpose the controller is to be used. The front panel can still be used during development by plugging it into an extender card in another slot.
The board enable is the output of the 74LS30 in position C9. Input to this 8 input NAND gate is the true or complement address bits 2 through 7, according to how they are jumpered. The input and output status bits are logically ORed and the output or its complement is also jumpered to the NAND gate in position C9. These two are used for I/O reference instructions or these two inputs to the NAND gate are taken from the complement of the status input or output instruction and the high address line which comes from the 74LS30 in position C6. This NAND gate in position C6 is active when all the high order of address bits 8 through 15 are true--that is, high. Address 0 and 1 and their complements are fed into a one-of-4 decoder consisting of the 7427 in position and part of the 7402 in position C11 along with one inverter.
Also as a condition in this one-of-four decoder is the board enable. The outputs of this one-of-four decoder are fed directly to the enable pins on the respective 8212 input or output ports. The DATAIN bus on the 8080 system is driven directly from the output of the four input latches. This is a tri-state output and is enabled only when the chip is selected by the one-of-four decoder.
The DATA OUTPUT bus in the 8080 goes directly to the four 8212 output ports. The second enable line on each of the input ports is connected to the PROCESSOR DATA BUS-IN signal such that the data is placed on the 8080 bus during the time that the processor wishes to read it. The other device select line in output port 8212's is driven by the ORed condition of the PROCESSOR WRITE STROBE or FRONT PANEL WRITE STROBE, these coming from pins 77 and 68 on the 8080 back plane respectively. The PROCESSOR DATA BUS IN signal appears on pin 78 of the 8080 back plane.
Handling the interrupt levels from the four input and four output ports requires only the interrupt select jumper socket in position 2 so that the appropriate interrupt levels which are already originated by the 8212 chips can be connected as desired to the proper priority interrupt line on the 8080 back plane. The remainder of the interrupt function is affected by the PIC-8 board, the Priority Interrupt/Clock board.
The PI0 Board has four input ports and four output ports. Each port has an eight bit latch associated with it. These ports may be addressed in one of two different ways: First, addressed as an input/output port with input or output instructions; second, they may be addressed with memory reference instructions. The type of addressing is selectable by jumpers and the board cannot have both types of addressing at the same time. The four input ports form a block of addresses that are four sequential addresses and the four output ports form a block of four sequential addresses which are the same four addresses as the input port. In other words, the same address used with an input instruction to linput on port number 0 is the same address used to output on port number 0.
When the board is being used with memory-mapped I/O, any 8080 instruction which either reads or writes a byte from lmemory can be used to either read or write respectively a byte from an input or output port on the I/O board. That is, a load accumulator, from the address that this board is jumper-selected to respond to, will load the accumulator with the data from the input port addressed. Each of the four input and each of the four output latches are equipped with data strobe lines. Each port has both an interrupt line and a strobe line which can be used as hand-shake signals for conventional parallel data transfers. In the case of the output ports, a low pulse on the strobe line will set the interrupt line low. The interrupt line changes on the falling edge of the strobe line and the strobe line would normally be kept high.
The interrupt line is made high again upon the trailing edge of the WRITE strobe of the processor which is writing la new eight bits of data into the output port. Thus, the strobe line would be the input hand-shaking line and the interrupt line would be the output hand-shaking line. The interrupt line may also be jumpered to one of the 8080 priority interrupt lines on the back plane to effect an interrupt to the processor when it goes low, that is, when the strobe line has been pulsed low to indicate it has been taken by the peripheral device.
If it is not desired to use hand-shaking lines, it is not necessary to jumper them or take any other action. Successive bits may be put out to the output ports with no further action by any other device. In this case, the strobe line would remain high from the on-board pull-up resistor and the interrupt line would remain high for lack of any strobe signal to affect it. l
The input ports also have one strobe line and one interrupt line each. Each of the strobe lines for the input ports also has an on-board pull-up resistor. If the strobe line is not connected or if it is driven high, the data in the latch will follow the input lines. The program can read input from the input lines and it will read the data that is present at the instant that the input instruction is executed. When the strobe line is made low the data that is present on the input lines at the falling edge of the strobe lines is latched into the input latch and remains there as long as the strobe line is held low. As soon as the strobe line is raised, the data in the latch will again follow the input lines. On the falling edge of the strobe lines the interrupt line will change from high to low.
This can be jumpered to the priority interrupt lines to create an interrupt to the processor, and/or it may be used as an indication that the processor has not yet read the latched data. If, while the strobe line is being held low, the processor reads data from the input port, then the interrupt line will return high at the trailing edge of the read strobe, thus indicating to the peripheral device that the processor has read that data and the latch is available for latching the next data byte into it. Each input and each output port has its own strobe and interrupt line. They may be driven together or separately.
All four of the output port strobe, interrupt and data lines appear on the 50 pin connector on the upper left edge of the board, and all four of the input port strobe, interrupt and data lines appear on the 50 pin connector on the upper right-hand edge of the board.
Also appearing on these connectors is ground and +5 volts
Each of the data input lines on the input ports is tied to +5 volts through a 1K resistor so that unused lines will be read as a high data level or true data level.
Position C2 on the PIO Board is the interrupt select jumper socket. Appearing at the pins of this socket are all eight of the priority interrupt lines for the 8080, the four input interrupt lines and the four output interrupt lines of the PI0 board. Thus, any interrupt line desired to be used may be jumpered from the appropriate pin.
If an interrupt is desired to be used, the jumper may be put between the interrupt line from the desired input or output port to the desired priority interrupt on the 8080 back plane. The PIC-8 board may be used to monitor these interrupt lines and originate the interrupt to the processor according to which line is requesting an interrupt. If more than one line is requesting an interrupt at the same time, the higher priority line rules. FIG. 8F shows an example for connecting the interrupt line from input port 2 to level 5 priority and the interrupt line from output port 2 to level 2 priority interrupt. l
The board address is selected by jumpers or a DIP switch in locations C8 and B9. There are two cases for which this board may be jumpered: 1) to respond to input/output instructions and 2) to respond to memory access instructions. The case of input/output instructions will be treated first.
In selection location B9, pins 8 and 9 must be jumpered together and pins 5 and 12 must be jumpered together. Address bits 0 and 1 determine which of the four input or output ports will be addressed. Port address bits 2 and 3 are also selected on location B9 with jumpers. If, for instance, address bit 2 is desired to be a 0 when the board responds, then pins 4 and 13 would be jumpered together. If address bit A2 was desired to be a 1, then either pins 3 and 13 may be jumpered together, since 13 and 14 are tied to the common address selection input.
It is suggested, however, that when jumpers are being used, pins 3 and 13 be connected together to provide an easy visual indication of whether the address bit is a 1 or a 0 since that will correspond to whether the jumpers are slanted or straight across the jumper socket. Pins 13 and 14 were tied together so than an 8 position DIP switch can be inserted in this location and used to select the address.
Address bits, 3, 4, 5, 6 and 7 are jumpered in a similar manner. Address bit 3 is also on location B9, address 4, 5, 6 and 7 are jumpered on position C8. See FIG. 8G for pin numbers lfor each address bit. l
If it is desired to use the board in a memory-mapped I/0 capacity, then in position B9 the jumpers between pins 8 and 9 and 5 and 12 must be removed and two jumpers inserted between pins 7 and 10 and between 6 and 11. The remaining jumpers for bits 2 through 7 function exactly the same and affect the lower eight bits of the memory address. The upper eight bits of the address will always be all ones, that is hex FF or octal 377.
When used as a memory-mapped I/O board, all instructions that normally affect the memory will operate on the I/O ports. For example, an increment memory instruction would read the data from the addressed input port, increment that data by one and output it on the same address output port. SIO
The SIO Board (FIGS. 7A-G) provides a serial input/output capability for the System. It contains two serial I/O ports, providing two complete RS232 full duplex data lines with all control signals. Data lines for both channels are provided in RS 232, TTL level and current loop formats. Asynchronous or synchronous lines utilizing full or half duplex can be run with this board at any rate up to 9600 baud in the Asynchronous mode and 56,000 baud in the Synchrounous mode.
The SIO Board may be jumper-selected to respond either lto input and output instructions from the System or to memory reference instructions for memory-mapped I/O. l
Operation of the board requires 16 I/O port or address locations, which are selected by address bits 0 through 3. When the board is used with input and output instructions, address bits 4 through 7 form the remainder of the board address and are jumper selectable. When the board is used as memory-mapped I/O, the lower byte of address is jumper selected exactly the same as an I/O port address and the upper byte of address is hex FE or octal 376.
The SIO Board is structured around a pair of Intel 8251 USART (Universal Synchronous-Asychronous Receiver-Transmitter) devices.
The 8251 chips provide for extensive program control of the input/output functions including the RS232 Control Line and sync character selection in the Synchronous mode and error condition sense and recovery. The board provides interrupt generation for received characters, empty transmitters buffers, and sync characters detected with provision for jumper selecting the priority of the interrupt. The interrupt works in conjunction with the Priority Interrupt/Clock board (PIC-8).
All functions may also be program controlled so that the full capability of the board is available to the machine without the use of interrupts. All RS232 level drivers and receivers necessary for two complete RS232 lines are included on the board.
Control lines included are DSR, DTR, RTS, CTS, and Carrier Detect. RS232 level drivers and receivers are also provided for receive and transmit clocks for use in Synchronous Mode. Jumper options permit the SIO board to be used either as the receiving (terminal) end of an RS232 line, or as the originating (computer) end.
Jumper options are available so that the two serial I/O ports may be used together so that the control lines are connected together on the two ports and the data lines are received and originated by the 8251 USARTS. l
This configuration permits breaking an existing RS232 line and inserting the System between the ends so that the control signals pass straight through and the System intercepts, processes, and retransmits the data. This configuration is extremely useful where format adaptation or other changes must be made to data travelling on RS232 Systems.
Jumper-selectable baud rates are provided on the board for standard asynchronous and synchronous rates up to 9600 baud asynchronous and up to 38,400 baud synchronous. Other rates may be obtained through the use of the SIOC board which contains a jumper-programmable divider which mounts directly onto the SIO Board.
TTL and current loop serial input and output are connected to unused pins on the input/output connector. TTL levels are available on the connector for DTR, DATAIN, and DATAOUT, to provide maximum flexibility and utility. A current source is available on the connector for use with current loops. Current loop driving is done through opto-isolators for complete isolation of current loop lines.
To enable the SIO board, it must be properly addressed. In the I/O port addressed mode, address bits A4 through A7 are jumpered to the 74LS30 (8 input NAND) in C8. The status bits SINP and SOUT are NORed, this intermediate value inverted, and applied (via jumper on D6) to another of the NAND inputs. Remaining NAND inputs in this mode are jumpered (via D6) to a +5 volt level. Thus, when the selected address appears on A4-A7, and the MPU sends a SINP or SOUT pulse, the NAND output goes low and the board is enabled.
In the memory-mapped I/O mode, the jumpering in socket C7 still selects an address. The high-order address is interpretted in another 8 input NAND (D8), and hard-wired to respond to the hex value FE. The jumper in socket D6 should be wired to put the inverted output of D8 into an input of C8, and the NORed output of the status bits SINP and SOUT directly connected to the (C8) NAND's input.
The +5 volt tie line jumper in D6 should not be connected for memory-mapped I/O. In this mode, when the corrected high and low order bits are on A4 through A15, and the MPU does not send a SINP or SOUT pulse, the board is enabled.
The SIO board has a bi-directional data bus on the board which connects to the 8251 chips and to the input and output portion of the SIO board control port. The bi-directional bus is connected to the DATA IN and DATA OUT busses on the back plane through 8216 bi-directional bus driver chips. The board enable signal selects these bi-directional bus driving chips and the processor's data bus in signal (DBIN) is used to determine the direction of driving of the bi-directional chips.
8T97's are used to gate the control port data on the bi-directional data bus on the board. They are enabled by the DBIN strobe from the processor and address bit 3.
The 4 output bits of the control port on the SIO board are latched into the 74177 which is clocked by a combination of board enable and address bit 3 and the write strobe either from the processor or from the front panel.
The 8251 chips are selected by address bits 1 and 2, respectively, with address bit 0 determining whether the chip is in control or data mode. The read and write strobes are supplied to complete the control, enabling the chip to read data or write data onto the bi-directional data bus on the board.
The four control lines desired for interrupt generation are ORed through 7425 and the resultant value supplied to an interrupt select jumper socket (D3). The 7425 OR gate may be disabled by two of the output port bits (IEA or IEB) when interrupts are not desired.
The two megacycle system clock phase II is divided to provide the standard baud rates for jumper selection to channel A and B. It is first divided by 13 through the use of a 7493 with external gating. This produces a rate extremely close to 16 times 9600 baud.
Further division of two are made by 7493's to provide most of the other standard baud rates. 110 baud for a standard teletype is achieved by a divide by 11 from the 2400 baud line which is then divided by 2 to create a symmetrical output and supplied to the jumper socket for 110 baud.
The phase II clock, +5 volts and ground are also supplied to the data rate select socket for use by the SIOC board which connects to the SIO board through the data rate select socket (B11) to provide a jumper-selectable baud rate generator for special rates.
The data and control outputs of the 8251 chips are driven or received through 1488 or 1489 TTL to RS232 level converters as appropriate to the functions. The TTL levels for data and control are driven through open-collector peripheral drivers and a 220 ohm pull-up to +5 volts. The current loop input and output are driven through opto-isolators and are designed to work adequately with either 20 or 60 milliampere current loops.
The IMSAI SIO Board provides 2 independent channels of serial data input and output. Utilizing the Intel 8251 USART devices, the SIO Board provides 2 channels of RS232, TTL, and current loop data lines with complete control signals.
The SIO Board also includes all logic necessary to control the 8251 devices from the Back Plane.
Both the memory-mapped and jumper-wired I/O configurations use the lower 4 bits of the address bytes (A1 through A3) to select and control the board's functions. Bits 4 through 7 of the board address (A4 - A7) are jumper-selected. If the board is jumper-selected to run as an input and output port type board, then A0 - A7 form a complete address. If the board is jumper-selected to respond to memory-mapped I/O, then A0 - A7 form the lower byte of address and the upper byte of address is hex FF or octal 376.
Address bits 1 and 2 select serial I/O channel A or channel B respectively. That is, when address bit 1 (A1) is high, serial I/O channel B is enabled. When address bit 2 (A2) is on, serial I/O channel B is enabled.
Address bit 0 determines whether the I/O channel selected will respond to the current byte as a control byte or a data byte. If address bit 0 is a 1, the control functions are selected, and if address bit 0 is a 0, the byte is assumed to be data. Thus, to write a control byte into serial I/O channel A, the lower 4 bits of address would normally contain hex 3 or octal 03, while the normal address for channel B control bytes would be hex 5 or octal 05. Address bit 3 (A3) selects the board control I/O port. When address bit 3 (A3) is high, the control port will be enabled. Thus, when use is being made of the control port, the lower 4 bits of address would normally be hex 8 or octal 10.
The control I/O byte selected by address bit 3 is divided into the upper 4 bits and the lower 4 bits. The lower 4 bits, 0 through 3, serve the channel A serial I/O circuit. The upper four bits, 4 through 7, serve the second I/O channel B functions. Bits 0 and 4, for channel A and B respectively, control the interrupt enable separately for each channel. When this bit is a 1, the interrupts are enabled and the processor will receive and interrupt whenever any one of the following 4 lines are active: the transmitter ready line, the transmitter empty line, the receiver ready line, and the sync detect line.
If bits 0 or 4 (as appropriate to channel A or B) are made 0, then no interrupts will be generated from the affected channel. Bits 1 and 5 serve channel A and B, respectively, to output the carrier detect signal. This is operative only when the jumper in jumper socket BJ has selected the board to act as the originator of the carrier detect line. Bits 2, 3, and 6, 7 are not functional in the output mode for the SIO control byte. When an input is read from the SIO control byte, bits 0, 1, 4 and 5 are not functional. These 4 bits will always be read as a 1.
Bits 2 and 6 read the condition of the carrier detect receiver for channels A and B, respectively. The signal is operative only when jumper socket BJ is jumpered to read the condition of the carrier detect line.
Bits 3 and 7 serve channel A and B, respectively, to read the condition of the clear-to-send (CTS) control signal. TThis is provided because it is not possible to read the condition of CTS through programmed input from the 8251.
When the TTL inputs are not being used, they should be left open or held high so as not to affect data input from other sources.
The TTL Data Input line must be left open and not held high when the current loop inputs are used. The current loop input drives opto-isolators and will respond to either 20 or 30 milliamperes. In applications where a significant reverse voltage may be experienced, such as when inductive circuits (i.e., relays) are coupled to the data line, a protective diode should be put across the line such that any reverse voltage spikes will cause the diode to conduct and thus protect the LED in the opto-isolator from too large a reverse voltage.
The current loop output is switched by an isolated transistor through an opto-isolator and is provided with a transient-shunting diode across the output transistor so that it may be used to drive relays without risk of damage to the output circuit. Typical wiring connections are shown in FIGS. 7J and K, both with and without the current source being used.
Setting the baud rate for serial I/O channels A and B is done on the jumper select socket RJ in position B11. The baud rates designated in FIG. 7L for rate select are correct when the 8251 is programmed for a 16X asuynchronous clock rate and a 1X synchronous clock rate.
The jumper selection socket in A3 serial I/O channel A and the jumper selection socket in B8 serves serial I/O circuit B. Their functions are the same for their respective channels. The function of this jumper socket is to permit the serial I/O port RS232 to be wired so as to either serve as the terminal end of a 232 line or the computer end of a 232 line with no special cable wiring required off the Serial I/O board.
With pins 1, 2, 4, 5, 7 and 8 wired directly across the jumper socket as shown in FIG. 7H for the terminal end, the function of the lines correspond one to one with the names of the RS232 control lines referred to in the 8251 specifications.
The inputs and outputs are arranged as appropriate for the SIO board to serve as the terminal end of an RS232 line. Should it be desired for the SIO board to serve as the computer end of a standard RS232 line, use jumpers connected as shown in FIG. 7H. The 3 pairs of lines are reversed so that TRANSMIT DATA is now driving what is received data for the terminal and RECEIVE DATA is receiving what is transmit data from the terminal, and similarly REQUEST TO SEND and CLEAR TO SEND are reversed and DATA SET READY and DATA TERMINAL READY are reversed.
Ground and +5 volts are available on the socket for providing permanent mark or space levels to any of the control lines if CLEAR TO SEND is not driven by an external source. It should be wired to pin 6 to provide a constant enable for the transmitter section of the USART.
Jumper socket BJ serves both to determine whether CARRIER DETECT is being originated or received by the SIO board. It is also used to jumper the control lines between channel A and channel B for applications where the control lines are desired to be passed through and data intercepted and handled. The four primary control lines for both channel A and channel B appear in this jumper socket, and can be jumper-wired straight across as desired.
It should be remembered that only one source should be driving an RS232 line at a time. If the control lines are jumpered straight across so that the modem and data terminal are driving the lines, then appropriate jumpers in the jumper socket locations A3 or B8 should be removed so that the SIO board will not be attempting to drive these lines at the same time. If it is desired to detect the DATA TERMINAL READY line, then a jumper needs to be placed as shown in FIG. 7M between pins 5 and 6 for channel A, or between pins 11 and 12 for channel B.
If it is desired to originate the CARRIER DETECT line, a jumper should be placed instead between pins 5 and 7 for channel A, for 10 and 12 for channel B.
Ground and +5 volts are available in this jumper socket for providing a permanent mark or space level to any of these control lines.
The interrupt line for channel A and channel B both appear on the interrupt select socket in position D3 (FIG. 7N). All 8 of the system priority interrupt lines on the back plane, also appear on the interrupt select socket. A jumper may be placed between the appropriate channel's interrupt line and any one of the priority interrupt system lines to provide an interrupt of the desired priority.
The jumper select socket in A1 provides facilities for originating and receiving clock signals for receive or transmit for use in the synchronous mode of communication. One-half of the socket controls lines for Channel A and the other half is dedicated to Channel B. Pins 1, 2, 3, 4, and 13, 14, 15 and 16 serve the channel A jumper functions. The remainder of the pins have the identical function for Channel B.
When it is desired to originate the clock signal the pins for that channel should be jumpered straight across, as shown in FIG. 7O, so that the clock signal from the SIO board is driven through converters to RS232 levels onto the DD and DB lines.
The inputs to the data clock receive circuits are tied to -12 volts to provide an inactive output to the OR-gate supplying the receive clock to the USART chip.
When it is desired instead to receive the clock from the RS232 cable, then these jumpers are removed and the RS232 lines DD and DB are jumpered to the input of the clock-receive circuits.
When this is done, the data rate select socket for the appropriate channel must be jumpered so that the clock line from this jumper select socket is held at ground or low in order to avoid interference between the onboard clock circuit and the incoming clock from the RS232 line.
The jumper socket in position B11 provides for selecting different baud rates for both Channel A and Channel B from the set of standard rates provided by the SIO board. The pin numbers and baud rates are indicated in FIG. 7L.
The clock lines for Channel A and Channel B are completely independent and may be jumpered to the same rate or different rates.
When the chip is being used in the synchronous mode, the chip is running at a 1X clock rate rather than 16 X rate as in asynchronous mode. Thus, the baud rates are 16 times as great for the same jumper location when used in the synchronous mode. The board address is selected by jumpers or a DIP switch in locations C7 and D6. There are two cases for which this board may be jumpered: 1) to respond to input/output instructions and 2) to respond to memory access instructions. The case of input/output instructions will be treated first. (See FIG. 7P)
In selection location D6 pins 8 and 9 must be jumpered together and pins 5 and 12 must be jumpered together. The user must jumper socket C7 so when the desired I/O Port Address appears on the Address lines, the inputs to the NAND gate from bits A4 through A7 are high. If, for instance, address bit 6 is desired to be a 0 when the board responds, then pins 4 and 13 would be jumpered together. If address bit A6 was desired to be a 1 then either pins 3 and 14 may be jumpered together or 3 and 13 may be jumpered together, since 13 and 14 are tied to the common address selection input.
It is suggested, however, that when jumpers are being used, pins 3 and 13 be connected together to provide an easy visual indication of whether the address bit is a 1 or a 0 since that will correspond to whether the jumpers are slanted or straight across the jumper socket. Pins 13 and 14 were tied together so that an 8 position DIP switch can be inserted in this location and used to select the address. Address bits 4, 5, and 7 are jumpered in a similar manner on position C7.
If it is desired to use the board in a memory-mapped I/O capacity, then in position D6 the jumpers between pins 8 and 9 and 5 and 12 must be removed and two jumpers inserted between pins 7 and 10 and between 6 and 11. The remaining jumpers for bits 4 through 7 function exactly the same and affect the lower eight bits of the memory address. The upper eight bits of the address will always be all ones, that is hex FE or octal 376.
When used as a memory-mapped I/O board, al instructions that normally affect the memory will operate on the I/O ports. For example, an increment memory instruction would read the data from the addressed input port, increment that data by one and output it on the same address output port.
To use the SIO Board in its simplest form, non-interrupted input/output instruction controlled, create jumpers as shown in FIG. 7Q.
The following comprises a sample sequence to set up SIO for teletype and echo from keyboard to printer:
Format used is 2 stop bits, no parity, and 7 data bits. Reset 8080 before running. Address and constants are in hexadecimal.
The PIC-8 Priority Interrupt-Programmable Clock Board (FIGS. 6A-E) provides the IMSAI 8080 Microcomputer System with an eight level Priority Interrupt capability and a software-controlled interval clock.
The Priority Interrupt system utilizes the Intel 8214 Priority interrupt control unit and monitors the 8 Priority Interrupt lines on the system back plane. The PIC-8 has the capability to serve either single or multiple interrupt requests. When enabled and receiving an interrupt request, the Pic-8 determines if the request priority is higher than the software-controlled current priority, and if necessary issues a restart instruction that directs the system to one of eight priority controlled restart locations. For multiple interrupt requests, the 8214 determines the highest priority request, and processes it normally. It should be noted that the system does not store inactive requests, and that a peripheral device must hold an interrupt request until it is serviced by the microprocessor.
The current priority status register may be software set to any value desired to prevent low priority interrupts from being generated until the priority status register is reset to a lower value. The status register may be set to 0 if it is desired for all levels of interrupt to always occur.
The PIC-8 board also includes a clock circuit which provides programmed control at intervals ranging from 0.1 millisecond to 1 second. The program can select from among 3 jumper selected interval rates, or it can turn all three off. The 3 rates are jumper-selectable to any of the following values: 0.1 ms, 0.2 ms, 1 ms, 2 ms, 10 ms, 100 ms. 200 ms, or 1000 ms. Additionally, one bit of the DATA OUTPUT port is connected to a transistor and jumper pads for a special-purpose programmer-controlled output. Room is provided on the circuit board for a small speaker or other user-supplied circuitry. Also provided are 5 16-pin IC hole patterns with power and ground decoupling for special purpose user circuits. These hole patterns are drilled to accept wire wrap sockets.
Program control of the PIC-8 board is done entirely through one output port location. The address of this output port is jumper-selected in socket positions E4 and E5, and forms the input to the 8 input NAND gate (741s30). The output of this address select is ANDed with the Processor Write Strobe and Phase II clock and provides an output strobe which is used to latch the lower 4 bits of output data into the 8214 priority interrupt chip, and the upper 4 bits into the 7475 bit latch.
When the 8214 is ENABLED and one of the priority request lines is low the 8214 sets the output of a 2 GATE Flip-Flop low to request an ineterrupt from the processor. When the processor acknowledges the interrupt the Flip-Flop reset and 3 buffer drivers of the 8T98 are enabled to put interrupt request address on bits 3, 4 and 5 of the DATA IN bus. The remaining bits of the DATA are not driven, and remain high via pullup resistors on the MPU Board. The byte thus formed on the DATA IN bus is a restart instruction with bits 3, 4, and 5 directing the processor to one of eight restart locators.
The PIC-8 board also includes a software controlled interval clock. The clock circuit takes the Phase II clock running at two megahertz and divides it by 200 using a divide-by-two (7474) followed by two divide-by-10 sections (7490) to provide the 0.1 millisecond intervals.
Four consecutive divide-by-10 7490's are then used to produce the other interval rates up to the longest rate of one second. Jumper selection is made from among these rates and ANDed with the output port bits 4, 5 and 6 and the output from the AND gate is used to drive the clock on the other half of the 7474 D type flip-flop. Ths section of the flip-flop is connected so that on successive clocks it will shift states and thus alternately request and remove the request for an interrupt.
When the processor system is running, and replying to the interrupts, shortly after the request is issued, the interrupt acknowledge line will become active in the low state and set this flip-flop to remove the interrupt request so that the next time the clock line rises, the flip flop is again reset to request another interrupt. The interrupt request from this circuit is jumper-connected to any one of the priority interrupt lines and is handled by the 8214 circuitry exactly the same as any other peripheral board requesting an interrupt through the back plane would be.
Output bit 7 is used to drive the base of the transistor through a 1K resistor for current limiting, and the user supplied circuit to be driven is connected between the positive voltage and the collector current limiting resistor. Should just a voltage level be desired, as an output from this circuit, a resistor from 220 ohms to 1K ohm can be inserted in the collector circuit in the holes provided and a jumper placed between pads A and C to connect the top of the resistor to +5 volts. The output may be taken from point B which will be low when the bit is written as a 1 and will be high when the bit is written as a 0.
For a high impedance load, voltage swing will be nearly a full 5 volts for the high level and 0.3 volts for the low level. If a direct TTL level output is desired, it can be obtained from solder pad E if the 1K resistor in the base lead is removed and a jumper placed in its location and the transistor removed so as not to provide undesired load for a high level output.
Request for an interrupt appears at the PIC-8 board in the form of one of the eight priority interrupt request lines being pulled to a logic 0 level. The 8214 chip will recognize that one or more interrupts are being requested and it will determine which multiple request has the highest priority.
The eight priority levels are numbered 0 through 7, with 7 being the highest priority. The priority level of the highest current interrupt request is then compared against the value stored in the current priority status register in bits 0, 1 and 2. If the currently-requested priority level is equal to or lower than the value stored in the current priority status register, no interrupt will be generated.
If the priority interrupt being requested is 0 and the current priority status register contains a 0, no interrupt will be generated. Thus, if a 5 were stored in the current priority status register, then only interrupt levels 6 and 7 would generate an interrupt. Interrupt levels 5 and lower would not be acted upon at this time.
If the priority interrupt being requested is 0, and the current priority status register contains a 0, no interrupt would be generated as the priority level is not greater than that stored in the current priority status register. If the current priority status register data bit 3 is written as a 1, the compare to the current priority status register is overridden, and the request for an interrupt priority 0 is acted upon and an interrupt to restart position 0 is generated.
If other priority level interrupts are requested during the time that data bit 3 has been written as a 1 in the current priority status level, then the highest priority interrupt requested will be acted upon.
At any time, if there is more than one priority level of interrupt being requested, only the highest priority level is acted upon, and any interrupt requests not serviced must be held present until the system can return to them.
After each interrupt has been generated, and the processor has responded to it, it is necessary that the current priority status register be restored to either the same or a different value; otherwise, no further interrupts will be generated.
When interrupts are initially enabled in a system, the current priority status register should also be intialized to insure that the interrupt generating system will respond to an interrupt.
It should be noted that the current priority status register inputs data bits 0, 1, and 2, are input in the complement form.
The program controlled clock's functions are selected by both user jumpers and software. Ater jumpers have been installed in the interval selection and priority select sockets, writing to the PIC-8's output port address can enable the clock circuitry. Data bits 4, 5, and 6 control the user-selected intervals.
In normal use, only one interval will be selected at a time; thus, only one of the three bits, 4, 5, and 6 in the output port will be 1 at a given time. If two or more of these bits are written 1 at the same time, then the different rates will interact and interrupts will not occur continuously at the highest rate, but will occur at the highest rate for only portions of the time and not at all during other portions of the time as determined by the specific rates selected. For example, if both the rates 1 millisecond and 1 second are selected at the same time, one millisecond interrupts will be received for 1/2 of one second and then no interrupts will be received for the second half of that second and this pattern will repeat every second.
Should an interval interrupt not be acted upon in the time remaining between it's occurrence and the occurrence of the following interval interrupt request, the interrupt request will be taken away at the following pulse, and the request will again be asserted on the second interval following the first. This pattern of requesting an interrupt every other interval will continue until the system is able to respond to the interrupts within the time period required.
Whenever a byte is output to select or change the selection of the interrupt interval, it must be remembered that the lower 4 bits of the same output byte affect the interrupt generating circuitry, and will set it so that it is ready to respond to the next interrupt. The desired value for the current priority status register, must be present in the output bytes lower 4 bits every time a bit is output for any purpose, whether it is to select or change the selection of the interrupt interval desired, or whether it is to change the current priority status register, or to output a bit 7 to the special purpose circuitry supplied by the user. Similarly, any time the output byte is used to set or change the current priority status level, bits 4, 5, and 6 must be also output according to the desired interrupt interval selected. Any bit which is written without changing does not cause any momentary glitches or other effects.
positions E4 and E5 contain the user-jumpered 16-pin address selection sockets. These jumpers allow the PIC-8 board to respond to any 1 of the 256 possible I/O port addresses.
As shown in FIG. 6F to enable the CRI board it is necessary to have all eight inputs to the 74LS30 (C5) high. The user should select the desired address, and then jumper the address selection sockets so that when that address appears on address lines A0 through A7, all the NAND inputs are high, and the board is then enabled.
Each socket contains values of 4 lines and their complements. Socket E5 controls lines A0 through A3. Socket E4 controls lines A4 through A7. If the user-selected address presents a 1 on an address line, that line sould be directly connected to the NAND input via a short wire jumper on the socket header. Conversely, if the user selected address presents a 0 on an address line, the inverted address line value should be connected to the NAND.
It is suggested that for lines jumpered to enable on a 1 value that the jumpers be placed diagonally across the socket (i.e., Pin 1 to Pin 15) and for lines jumpered for a 0 value, the jumper be placed straight across the header (i.e., Pin 2 to Pin 15). This convention allows easy visual determination of the selected address, for 1's appear as diagonals and 0' as horizontals. An example of a correctly jumpered socket pair for the address C4 hex or 304 octal is shown in FIG. 6F.
If desired, very frequent address chages may be easily implemented through the exchange of an 8 pole DIP switch for each socket.
All 8 of the NAND inputs should be jumpered to respond to either a 1 or a 0. While any input left unconnected will appear to act as a 1, open inputs are very susecptible to noise pulses.
In position D2, the jumper socket permits the selection of the priority level at which the interrupts generated by the interval clock circuit will occur. The interrupt request level from the interval clock circuit appears on pin 4 of the jumper socket, and the eight available priority levels inputs appear on pins 9 through 16 of the jumper socket. A jumper should be placed between in 4 and the pin corresponding to the priority level desired for the interval clock's interrupts (see FIG. 6G).
While 3 interrupt intervals may be program selected on the PIC-8 board, jumper selection from among the nine available interrupt intervals must be made in the jumper socket in position C4 to choose with three interrupt intervals the program is capable of selecting among. As indicated in FIG. 6H, Pins 12, 13 and 14 on the jumper socket are the three inputs to the interrupt generating circuitry from along which port bits 4, 5, and 6 are used to select one or more of the levels to be active. A high level on data bit 4 will select the input jumpered to pin 12. A 1 on bit 5 will select the rate jumpered to pin 13, and a 1 on data bit 6 will select the input interval jumpered to pin 14.
The nine available intervals appear on pins 1 through 9 of the jumper socket as indicated in FIG. 6H and the three desired intervals from among the set should be jumpered to pins 12, 13, and 14.
FIG. 6H shows an example of jumper wiring which will permit data bit 6 to select 0.2 millisecond intervals, data bit 5 to select 20 millisecond intervals, and data bit 4 to select one second intervals.
Bit 7 on the output port is available for special purpose uses as desired by the user. Again it must be remembered that every time bit 7 is out the remaining bits 0 through 6 must also be output according to the desired functions.
DMAB
As noted above, the DMAB provides a high speed data transfer path among the various processors of the system and to external host computers. With reference to FIG. 1, processor 16 is used to detect the requirement for DMA as initiated from the other occupants on the DMAB, i.e. the communications, DBMS and storage level processors, and the external computers 12, 12'. This is accomplished in a polling system in which the processor 16 sequentially reads a bit in the status register possessed by every occupant on the DMAB. The processor 16 then transfers from the memory of the initating member the pertinent information (starting addresses, block length, source and destination) to itself. Processor 16 next loads the starting address and block length into the respective registers of the source occupant and the destination occupant of th DMAB, after which a go signal is sent to both occupant involved in the transfer. The two participants then proceed to exchange data independently of processor 16. When the transfer is complete, processor 16 is notified by the receiver of the data and resumes polling. FIGS. 55-75 illustrate the system units, components and timing of the DMAB.
Processor 16 (FIGS. 55, 61, and 64) is driven by a PIO board. Processor 16 in turn drives the DMAB Bus 15 which in turn controls all other boards on the system. All port numbers assume that the PIO board is set up to respond to I/O ports 0, 1, 2 and 3.
Processor 16 is used to set up DMAB-S boards and the DMAB-11 boards, both of which are termed slave boards and are shown in FIGS. 65-74. The commands available are:
There is a handshaking sequence (controlled by software) for each command. The sequence for transfer to the slave is:
(1) Set up data lines and set up mode lines
(2) Raise MCR
(3) wait for MCA to come up
(4) Lower MCR (Note: MCA will then fall)
The sequence for transfers to the Master Controller (Processor 16) is:
(1) Set up Mode Line
(2) Raise MCR
(3) wait for MCA to come up
(4) Read data from Data Lines
(5) Lower MCR (Note: MCA will then fall)
The sequence for a GO command is:
(1) Set up Mode Lines
(2) Raise MCR
(3) wait for MCA to come up
(4) Lower MCR (Note: MCA will then fall)
To abort a GO command:
(1) Lower MCR (Note: MCA will then fall)
DMAB-S
The DMAB-S is a slave board that is under the control of the DMAB-MC Board. The slave board can either receive or transmit data on the DMAB Bus. The slave is set up by the Master Controller with a starting address and a word count. The only other thing of interest to the Programmer is the Status Register (which is readable by the Master Controller via a Read Status command or settable via a Write Status command) which is read or written via an input or output instruction issued by the microprocessor into which the slave board i is plugged. The specific I/O address of the Status Register is set by jumpers on the Slave Board.
DMAB-11
The DMAB-11 is an example of a mainframe interface (PDP 11 computer) and is similar to other slave boards.
(1) It provides 32 16-bit registers in the I/O address space of the PDP-11 (Jumperable to any location)
(2) These registers are read and written as normal I/O registers by the PDP-11
(3) these registers are read and written by the DMAB system by setting up a normal transfer from the PDP-11 memory to the controller's memory.
(4) The status register is different:
(a) The PDP-11 cannot read the status register if it is desir to read the status register content by the PDP-11. The contents must be transferred to one of the 32 16-bit registers via a normal transfer.
(b) There are more bits of status.
Status bit 0 is the same, transmits bits as a normal slave.
Status bit 1 is the same, receives bits as a normal slave.
Status bit 2 is set by the PDP-11 unibus line INITL.
Status bit 3 is set by the Master Controller and causes an interrupt on the PDP-11 (the interrupt vector is set by board jumpers).
Status bit 4 is a timeout bit that is set by the logic on the DMAB-board after the PDP-11 has not responded to the MSYN for approximately 20 microseconds.
Status bit 5 is a bit set by the PB unibus signal.
Status bit 6 is a bit that is set by the logic if a parity error is discovered during a DMAB transfer.
PROGRAMMING INSTRUCTIONS FOR DMAB BUS
Sequence necessary for causing a transfer from one slave unit to another:
1. Load address register on transmitting slave
2. Load word count on transmitting slave
3. Load address register on receiving slave
4. Loan word count on receiving slave
5. Load status register on transmitting slave
6. Load status register on receiving slave
7. Issue GO command
How to do individual steps:
Steps 1 and 3:
a. Issue enable slave command after placing slave code on data lines
b. Issue load A0, A1 and A2 commands after placing address data on data lines
c. Issues disable slave command after placing slave address on data lines.
Steps 2 and 4:
a. Issue enable slave command after placing slave code on data lines.
b. Issue WCNT 0 and WCNT 1 commands after placing word count data on data lines.
c. Issues disable slave command after placing slave address on data lines.
Steps 5 and 6:
a. Issue enable slave command after placing slave code on data lines.
b. Issue write status command after placing status data on data lines.
c. Issue disable slave command after placing slave address on data lines.
How slave notifies master of need to transfer data:
1. Processor places information necessary for transfer in specific area of memory (user option) and raises (via an I/O instruction) a status bit (on the slave board plugged in to that processor) (which one is a user option) indicating service is needed.
How the master knows when a slave needs to move data:
1. Polls slave units with a read status command looking for status bit indicating service request.
2. Master then (via an ordinary DMAB transfer) transfers the block of information into it's own memory (via it's own slave board), examines it and proceeds to set up the transfer.
Explanation of Individual Commands:
Enable slave: This command enables a slave board to receive additional command.
Disable slave: This command disables a slave so it will not respond to commands.
Load A0: Load low order 8 bits of the 24 bit address of the first byte of a transfer.
Load A1: Loads 2nd 8 bits of the address of the transfer.
Load A2: Loads 3rd 8 bits of the address of the transfer.
Wcnt0: loads the low order 8 bits of a 16 bit word count.
Wcnt1: loads the high order 8 bits of a 16 word count.
Write Status: Load status register of a slave board including a bit to say if the slave is sending or receiving on the next transfer.
Rcnt0: reads low order 8 bits of word count.
Rcnt1: reads high order 8 bits of word count.
Read status: Read status of status register (contents set by slave processor).
Go: causes any slave set up as a transmitter to start extracting words from memory and sending them out on the bus. Also causes any slave set up to receive to take data off the bus and store it in memory. Proceeds until the word count at receiver goes to zero.
System Operation
Communications Level
The communications level processors 10, 11 of the system are responsible for all tasks associated with handling the communications protocol required by the external devices. This includes checksumming messages, calculating and verifying message lengths, driving serial I/O lines, and handling error correction by retransmitting incorrectly-received messages. Each communications level processor is connected to a number of full-duplex serial I/O lines which in turn are connected to the computers which are making use of the system. For example, if two mainframes were using the system as a shared disk, each of the two communications level processors would drive two serial I/O lines, one to each mainframe. This would simulaneously insure both good throughput, high parallelism, and graceful degradation should one communications level processor go down.
The code of the communications level processor is driven by tables describing the serial I/O lines. These tables are called device status blocks, or DSB's. Each DSB is associated with a single serial I/O line, and drives both the transmitter and receiver of that line. The interrupt service routines in the communications level pack incoming characters into the receiver buffer, transmit characters from the transmitter buffer, and notify the non-interrupt code via status bytes when these operations are completed. The non-interrupt code examines the DSB's, looking for completed transmissions and receptions, and then taking action to pass messages onto the data base level or initiate a new transmission.
The DSB contains the following fields: A line identification, the mode the SIO board is operating in, the last command sent to the SIO board, the I/O ports needed to communicate with the SIO board, a link to the next DSB on the chain, a pointer into the receiver buffer, a count of characters received in the current message, a receiver status, a pointer into the transmit buffer, a transmitter status, a status to be placed in the transmitter status when transmission is complete, a time out used for waiting for achknowledgements, and receive and transmit buffers. The statuses of the DSB's receiver and transmitter status fields take on the following states: idle (waiting for a message), busy (in the process of transmitting or receiving a message), message present (message completely received or about to be transmitted), wait (transmitter waiting for an acknowledgement), again (transitter retransmitting due to no acknowledgement), and end (transmitter in the process of transmitting the last character).
The message format used by the communications level is specifically designed for computer-to-computer communications across asynchronous serial lines. It contains a number of delimiting control characters, a byte count, a checksum, and of course the text. The checksum and length fields are coded in a special format suitable for computer-to-computer communication: the binary number to be transmitted is separated into four-bit fields, and each four-bit field is arithmetically added to the ASCII character A, thus producing one of the characters A through P, corresponding to the hexadecimal digits O through F. A number of these four-bit encoded characters are combined to produce an 8-bit checksum or a 16-bit length field. This encoding scheme is basically hexadecimal numbers using a different mapping for the digits. The exact format of the message, including ASCII control characters, is as follows:
The checksum is simple a 2's complement sum of the characters with carries ignored.
The protocol for transmission and reception of messages is a simplification of the scheme used by the ARPA net. In this scheme, any message which does not contain the required ASCII control character, had a bad checksum, or has a bad byte count will be ignored by the receiving computer. The transmitting computer will associate a timer with each message, which will cause retransmission of the message if no acknowledgement is received within a given time. When the receiving processor successfully receives a correct message, it acknowledges this reception by transmitting a message back consisting of the normal message format with the text being the single character ACK. Note that in this protocol, if the acknowledgement is garbled a spurious second transmission will follow. This means that the receiving processor must be prepared to accept duplicate messages. In the intelligent disk system, the communications level processors do not make any checks for any duplicate messages, since duplicate GETSs and PUTs will only slightly increase the load on the disk, and will produce a duplicate reply that is indistinguishable from the duplicate reply generated by a garbled acknowledgement of the response to the user's request. However, the user processor must be prepared to accept duplicate replies to its disk requests and take appropriate action.
Although the communications level processor is provided with a PIC-8 board, (FIGS. 6A-E) this board is used only for collecting interrupt requests and passing them on to the MPU. The priority feature of the PIC-8 board is not used. Only one clock on the PIC-8 board is used; this is the 100 millisecond clock, and is used for timing out transmissions. On the SIO board, (FIGS. 7A-G) the individual 8251 interrupt control bits are also not used. This is because receiver interrupts must never be turned off, since it is never predictable when a user is going to transmit a message. However, due to the structure of the SIO board, it is occasionally necessary to turn off transmission interrupts when there is no message that may be transmitted. This is because when the transmitter is empty, the 8251 chip will continually interrupt the microprocessor, trying to get a character to transmit. To turn off the 8251 transmitter, it is necessary first to load a command byte which has the transmitter-enable bit turned off, and then load a dummy character into the transmit register. Furthermore, each time that a command byte is loaded while the transmitter is off, another dummy character must be loaded into the transmit register, so that the interrupts will stay off. To implement this, the interrupt code unconditionally loads a dummy character into the transmitter register anytime it gets a spurious interrupt, which is defined as any interrupt received while the transmitter is not in the busy state.
It will be noted that both interrupt and the non-interrupt code make changes to the transmitter and receiver status. This will never cause interference, however, because each transition from status X to status Y may be made only by the interrupt code or only by the non-interrupt code. Thus, if a receiver is idle, only the interrupt code may place it in the busy state. And if a receiver is in the message state, only the non-interrupt code may place it back into the idle state.
The main loop of the non-interrupt code of the communications level alternates between scanning the DSB's for incoming messages from the user and scanning the DBMS level mailboxes for responses from the disk system. Whenever a message from a user is found in a DSB, a mailbox to the DBMS level is required, the message text is copied into that mailbox, the message is acknowledged, the receiver is freed. Whenever a message is found in the mailbox from the DBMS level, it is placed into the appropriate transmitter buffer and returned to the user. The non-interrupt code during this phase also handles retransmission of non-acknowledged messages and acceptance of acknowledgement messages.
The interrupt code, when entered, scans through all of the DSB's processing them as required by the status read from their control registers. It is important to note that the interrupt code does not stop processing when it finds the DSB that requested the interrupt, since time can be saved by continuing if there is another DSB which also needs service. The interrupt code is divided into a receiver section and a transmitter section; each of these is executed only if the associated section of that Serial I/O line needs service. This is to say, the receiver section is only executed when the character appears on the Serial I/O line, and the transmitter section is only executed when one of the transmitter registers is empty. The exact processing of an incoming or outgoing character depends upon the character and the current status of the transmitter or receiver. Take special note of the fact that if the transmitter needs a dummy character to be loaded, this character will not be loaded until both transmitter registers are empty. This is necessary to prevent garbling of the last character of the transmission. As a side effect of this, during the last character of any transmission on any SIO line, interrupts will be locked on; the interrupt routine will be immediately reentered after returning to the main line code, and the non-interrupt code will come to a complete halt. While this might seem serious, a simple analysis of message lengths will show that this affects the non-interrupt code for only one character out of each message; if each message is merely 100 characters long, this means that the non-interrupt code will be held up only 1% of the time.
The clock interrupt service is entered every tenth of a second when the clock on the PIC-8 board picks. The length list of the DSB's is scanned looking for one or more which are in the wait state. If a DSB in the wait state is found which has a nonzero time-out, this time-out is decremented by one. If the time-out ever reaches 0, the DSB is placed in the transmit again state, so that the non-interrupt code will retransmit the outgoing non-acknowledged message.
One final note about two special cases: the first, when a mailbox can not be found to receive an incoming message, and the second, when the transmitter necessary to transmit an outgoing message from a mailbox is busy. In the first, or no mailboxes case, the incoming message is simply thrown away. While this is admittably undesirable, it is necessary so that the receiver buffer may be free in case an incoming acknowledgment is needed. In the second case, the mailbox is simply ignored, since it will be picked up at a latter time again and will eventually be transmitted when the transmitter is no longer busy.
DBMS LEVEL
The purpose of the DBMS level is to interface English-like text to commands to the storage level processors, 26, 27 and to take responses from the storage level processors and convert them back to a format suitable for communication with the outside world.
The DBMS level operates in two phases. The first phase accepts command strings from communications level, translates these command strings into storage requests and passes these storage requests to the storage level. The second phase (which is entered when there are no more commands to be processed in the first phase) accepts responses from the storage level, changes them into response strings, and passes them up to the communication level for transmission to the user.
The interface between the communications level and the DBMS level is very simple. The communications level passes the DBMS level a mailbox containing the text of the command with all serial control characters removed. The mailbox ID field, MID, contains the identification number of the SIO line which originated the request. This number must be returned to the communications level with the response in order that the response may be directed to the appropriate user.
The interface between the DBMS level and the storage level is slightly more complex. The mailbox ID is not used, but the mailbox text is divided into several fields. The first byte of the mailbox text is a control byte. The low order 7 bits of this byte specify various disk operations. Currently only two are defined: a read/write bit, bit 0, and an initialize bit, bit 1. The top bit of this control byte is set upon return by the storage level if an error occurred. The next two bytes contain a pointer to the communications level mailbox associated with this request.
The following five bytes contain a binary disk address: one byte for disk number, two bytes for track number, one byte for head number, and one byte for sector number. If the operation is some sort of a write, the data to be written immediately follows the sector number and is terminated by an ASCII ETX character. The response from the storage level contains the control and mailbox-pointer fields as passed to it, followed immediately by the data read from the disk, if any.
When the DBMS level processs a syntactically correct request from the communications level, it does not immediately release the mailbox in which the message arrived. Instead, it saves this mailbox for use in returning the eventual response to the communications level. This insures that there will always be an available mailbox for a response, preventing deadlock due to no mailboxes for a response because all mailboxes have requests in them. A pointer to this communications level mailbox is stored in the storage level mailbox. This allows the appropriate mailbox to be associated with the response from the storage level. Whichever DBMS level processor 21-24 processes the response from the storage level (which may not be the same processor that originated the request) will pick up this communications-level mailbox pointer and use that box to return a response. There is no possibility of two DBMS processors simultaneously attempting to use the same communications level mailbox to return a response because exclusive access is guaranteed by the exclusive access to the storage level mailbox containing the pointer.
There are two major subroutines in the data base level, DOCMD (FIG. 38) and DODSK (FIG. 39). DOCMD processes commands passed from the communications level; DODSK processes responses from the storage level. DODSK will be described first even though it follows second in the logical processing sequence. DODSK is entered with a pointer to a mailbox from the storage level containing a response to a previous request. The control word is examined first for the error bit. If the error bit is set, a message follows the mailbox pointer in the storage level mailbox. This error message is copied into the communication level mailbox with the ID field from the original command. The storage level box is then free and the communications level box is passed upwards to the communications processors 10 or 11.
If there were no errors, a successful request message is appended to the command ID, and any data read from the disk is copied into the communications level mailbox. Then the storage level box is freed and the communication level box is sent to the user.
Subroutine DOCMD passes the commands from the user and calls an appropriate processing routine to execute the command. These processing routines are entered with a jump via a table in subroutine DOCMD, the command table. This is a sequential table of variable-length entries, one for each command. Each entry consists of an ASCII prototype keyword string, an ASCII ETX character as a delimiter, and two bytes containing a pointer to the routine entered if the users keyword matches the prototype keyword. Most of the code of subroutine DOCMD itself is concerned with searching the command table for a match and entering the appropriate routine.
When the processing routine for a particular command is entered, registers D and E point to the blank following the command keyword, and the top three entries on the stack point to the beginning of the command string, the storage level mailbox acquired for processing the command, and the communications level mailbox containing the command. The processing routine is entered with a jump, and should exit with a return, which will return to the caller of DOCMD.
Since no data is provided by the user for GET (FIG. 40) or INITIALIZE the processing routines for these commands are relatively simple. All they do is translate the disk address into binary and pass the request on to the storage level. The PUT routine (FIG. 41), in addition, must copy the data provided by the user into the storage-level mailbox before passing the request on. Of course, all three of these processing routines must do extensive syntactical checking. If any errors are detected, the storage-level box is freed without being used and an error message is returned in the communications level mailbox.
Subroutine TRADD (FIG. 42) translates the hexadecimal disk address in the users request into binary addresses suitable for communicating with the storage level. This subroutine is also responsible for a large amount of the syntactical error checking, and if it detects any such errors it does not return to its caller (which should be a DOCMD processing routine); instead it returns to its caller's caller, i.e., the caller of DOCMD. This has the advantage of freeing the processing routine from most error handling. The actual processing of TRADD consists of successive calls to subroutines which find and convert hexadecimal numbers into binary, checking for errors at the same time. Note that the sector as given by the user actually represents both the head and a sector to the storage level. The translation between the two forms is done by looking up the user's value in a table, SECTB.
Subroutine COPID is responsible for finding the identification field of the user's command in the communications-level mailbox, copying it down to the beginning of that mailbox, and placing a comma after the ID. This prepares the communications-level mailbox to receive a response from the storage level. This response can be copied into the communication level mailbox immediately following the prepared ID.
The DBMS level does not have any local data to be initialized upon system power-up. However, the DBMS level's unique position with access to both shared memories causes it to be given the responsibility of initializing all shared data.
Configuration Chips
In the system, any processor which executes code that is dependent upon the particular configuration of the disk 28 or 28 acquires information about the configuration from a fixed area in ROM. Because the area in ROM is assigned to a separate ROM chip, the area is referred to as the configuration area or the configuration chip. When the configuration of the Intelligent Disk is changed, it is necessary only to replace the configuration chips; all other changes are taken care of automatically.
There are a number of configuration changes that may be made to the system. These include adding or removing lines to the communications level processors, adding or removing disk spindles, and adding or removing shared memory. The first two of these configuration changes require changes in the configuration chips; adding shared memory is automatically detected by the system and requires only the addition or removal of additional 4K shared memory boards at appropriate addresses.
If shared memory is to be added or deleted, it is best to make the same changes in both shared memories at the same time, since throughput is best when the shared memories are equal in size. The shared memories must always contain boards with addresses B000 for the communications to DBMS level shared memory, and F000 for the DBMS to storage level shared memory. The second board for each shared memory is placed just below the first board in the address sequence; i.e., A000 and E000. Successive 4K boards are installed at successively lower addresses. There is an absolute limit of four boards in each shared memory; this is software limit.
The communications level configuration chip controls two options: the debug option, and the list of I/O lines to be driven. The debug option is controlled by the first location of the configuration chip, at 300 hex. If this location is non zero, the message length and checksum characters on incoming messages must be present but are not verified. This allows a terminal keyboard to be substituted for the user computer for use in debugging the system using the control characters on the keyboard in appropriate sequences to generate the proper message format without calculating the length and checksum.
The rest of the communications level configuration chip, from location 301 hex onward, is devoted to the DSB initialization table. This table consists of a series of 5-byte entries terminated by a single zero byte. Each entry defines a single I/O line. The first byte of the entry is the terminal ID for this line. The next byte is the mode word to be used in initializing the Intel 8251 chip; described in the Intel 8080 manual.
The next byte is the command byte to be loaded into the 8251 chip after the mode byte is loaded. This byte is also described in the Intel manual. This byte should have the receiver interrupt control bit set on and the transmitter control bit set off. The next byte is the I/O port number to use to access the command register of the 8251 chip. The final byte of the entry is the port number to be used for accessing data to and from the 8251 chip.
The terminal ID in a DSB is used to insure that a message that originated on a particular line returns to that same line. If it is desired that a message only be able to return to the line that originated it, each DSB in the system must be given a unique ID, even if the DSBs are in different communications level processors. For instance, if there are two communications level processors, each driving two I/O lines, DSB IDs must be assigned 1, 2, 3, 4 to the four I/O lines in order to ensure that messages return to the originator. In some cases, it may not be desirable that messages return to the originating line. For instance, in the aforementioned system, assume that the first line from each communications level processor were connected to host A, while the second were connected to host B. In this case, if the load on one line to host A is heavy, it would be desirable for some of the load to be shifted to the other line to host A. This is achieved by assigned DSB IDs of 1 and 2 to the lines in each machine. A message coming from host A would receive a DSB of 1 and the reply to that message would return to host A over either of the lines connected to that host, depending on which was free. Note that acknowledgements still travel across the same line that the message being acknowledged travelled across.
SYSTEM INITIALIZATION
When the system is powered up, it is necessary for the communications tables in shared memory units 20 and 25 to be initialized. Since each shared memory is being accessed by several processors, the initialization must take special care to insure that two processors do not simultaneously attempt to initialize the same shared memory. To prevent this occurrence, all initialization of shared memory is done by a single DBMS level processor, designated the master processor. All other processors in the system will wait for the master processor to complete initiliazation before accessing shared memory. This is done by examining a preassigned and fixed location in shared memory which the master processor initially sets nonzero and clears upon the completion of initialization. This location is the last location in shared memory, and is referred to as the synchronization location. The immediately preceding two locations in shared memory, i.e., the second from last and next to last, contain a pointer to the linked list of mailboxes. These locations are copied by each processor into local RAM when the synchronization location is cleared.
Physically, there are two separate blocks of shared memory. The first, at locations 8000 to BFFF, is shared between the communications level and the DBMS level. The second block, located from C000 to FFFF, is shared between the DBMS level and the storage level. Each block of shared memory is composed of one to four 4K RAM boards. If fewer than four boards are used in a particular block, they are to be assigned the highest possible addresses in that block, i.e., if one board is being used in the communications-to-data base level shared memory block, it is to be assigned address B000. The initialization code in the master processor is written in such a manner that it dynamically determines how many 4K RAM boards are assigned to each shared memory block and initializes appropriately.
Subroutine BOXES (FIG. 43) is responsible for initializing a block of shared memory. On entry, register HL points to the highest RAM board in a block of shared memory, which is the only board guaranteed to be there. BOXES first scans downward from the location in HL until it has either scanned 16K of RAM or has found a 4K block which is not RAM. After determining the size of the shared RAM, as many mailboxes are created as will fit into the shared RAM, the address of the first mailbox in the list is stored in the top of shared RAM, and the synchronization location is cleared. Subroutine BOXES is called twice, one to initialize communications-to-DBMS level shared, memory, and once to initialize DMBS to storage level shared memory.
In the DBMS level processor, the configuration chip at 300 hx uses only two locations. The first is the master flag. For initialization purposes, exactly one of the data base level processors in any given system should have the master flag non zero and all other data base level processors should have the master flag, 0. Furthermore, the processor which has the master flag non zero should also be the highest priority processor accessing each shared memory. This processor will initialize the shared memories, insuring that the initialization is done before the other processors in the system being to access shared memory. The second location in the DBMS level configuration chip, location 301 hex, is the disk ID number of the largest numbered disk in the system. In other words, this location contains one less than the number of spindles in the system. For example, in a 4 spindle system, this location would contain the value 3. This location must be the same for all DBMS level processors. It is used in error checking to prevent the user from attempting to access a nonexistent spindle.
STORAGE LEVEL
Each disk controller 30, 31 consists of two circuit boards, TIFA and TIFB and provides a control and data interface between the 8080 microcomputer and the disk drive.
TIFA provides the controlled backplane interface connection which consists of 16 address lines, 8 input data lines, 8 output data lines, 6 timing and control lines, and 4 interrupt lines. The controller backplane interface is listed in Table 1.
The controller is interfaced to the disk through two fifty conductor flat cables. The port connection on TIFA provides the RADIAL cable connection to the disk, and the port connection on TIFB provides the BUSSED cable connection to the disk. The two flat cables are connected at the disk end to a printed circuit board which provides mating connectors for the disk drive connectors. The cable specifications are given in Tables 2 and 3.
The controller +5VDC is provided by a regulator located in TIFB and the controller -5VDC is provided by a dropping resistor and zener diode located on TIFA.
As shown in FIG. 48, the disk controller consists of the following general logic units:
1. Two eight bit bidirectional data paths.
2. Address decoding logic.
3. Two programmable interfaces.
4. Interrupt logic.
5. 1-1/4K by 8 random access memory.
6. Cyclic redundancy code (CRC) logic.
7. Data transfer control logic.
The two eight bit bidirectional data paths are located on TIFA and provide processor access to the two programmable interface modules.
The address decoding logic is located on TIFA and consist of two 1 of 8 binary decoders, a 16-pin address pallet, and an eight input NAND gae. The outputs of the decoding logic are used to select, each of the five memory address ranges, each of the two programmable interface units, and four controller functions used during disk data transfers.
The two programmable interface units are located on TIFB and provide three eight bit output latches and three eight bit input data paths. The output latches are used to drive the disk BUS/TAG lines, and latch control information used by the disk controller. The three input date paths provide disk and controller status information.
The interrupt logic is located on TIFB and consists of three flip-flops and associated gating. The flop-flops are set directly by index and sector pulses from the disk drive and are reset by the processor under program control. The three flip-flop interrupt lines are routed to the backplane through TIFA. The fourth interrupt line (ATTENTION) is received and inverted to TIFB and routed to the backplane through TIFA.
The 1-1/4K by weight random access memory is located on TIFA and consists of ten 256 by 4 static MOS RAM chips with 450 nanosecond access time. The memory is used to buffer the disk data during read and write operations and therefore, can be accessed by both the processor and the controller data transfer logic.
The CRC logic is located on TIFB and consists of three eight bit shift registers, three hex latches, and associated control and exclusive OR gating. The logic is used to generate and compare a 32 bit cyclic redundancy check code during disk write and read operations.
The data transfer control logic is located on both TIFA and TIFB and consists of the following logic units:
1. bit counter
2. delay counter
3. memory address counter
4. stop address latch and comparator
5. data shift register and latch
6. control flop-flops and gating
The bit counter is used to generate a load and count pulse for every eight data clock pulses. The load pulses are used to latch each eight bit byte of serial data during read operations, and load the shift register with eight bits of data during write operations. The count pulses are used to decrement the memory address counter.
The delay counter is used to time synchronize disk read and write operations to sector pulses. The read delay value is intended to guarantee the start of read transfers within a zero data field.
The memory address counter is loadable by the processor and controls the start point and accessing of the disk controller 1-1/4K resident memory during during disk data transfers.
The stop address latch is loadable by the processor and determines the stop point of the disk data transfer within the bottom 256 bytes. The output of the stop latch is compared to the lower eight bits of the memory address counter and generates a stop signal, which terminates the data transfer.
The data shift register and latch are used to buffer eight bits of data during disk read operations, and provide a parallel to serial data path during disk write operations.
The control flip-flops and gating are used to enable gating the read and write bus lines after the delay count, and enable starting the decrement of the memory address counter after the sync byte of data.
Disk Drive Control and Status
Disk drive control and status information is passed to or from the processor backplane through two 8216 (four bit bi-directional bus drivers), IC's C4 and D4 located on TIFA. Disk control bits are latched into the port C outputs of the two 8255 (programmable peripheral interface), IC's A5 and A6 located on TIFB, and disk status information is read in through Port A of 8255 A5. (FIG. 49)
To latch disk control information, a memory write instruction must be executed with the memory address being that of the selected 8255 port C. Backplane address lines are decoded by the 8205 (one of 8 decoder) IC B3 located on TIFA and either chip select PSO or PSI is generated. The processor output information is latched into the output of the selected 8255 on the falling edge of the processor write signal PWR. The disk cable signal (SEQUENCE, SELECT, BUS, TAG) are driven by open collector drivers IC's A3, B3, C3, D3, A4, B4 and C4, located on TIFB. With the exception of BUS 2 and BUS 3, which have special gating for read/write operations, the inputs to the cable drivers are taken directly from the port C outputs of IC A5 and A6.
Disk Controller Control and Status
Control bits used by the disk controller logic are set through the same procedure as setting the disk drive control bits, that is, by performing a memory write operation to the appropriate memory address with the correct bit pattern to enable the desired function. The control bits used by the controller are latched into port A output and port C output (bit 7) of IC A6 on TIFB. These controller control bits are used high true, low true, as levels and as pulses.
An example of a low true pulse output bit is signal CLR INDI, which is used to clear the index flip-flop. Normally the bit is in the high state in the output latch. After an index interrupter occurs a memory write to port A of IC A6 should be executed with CLRINDI bit off. This latches the bit low and clears flip-flop INDI. A second memory write operation should be executed with this bit on. This latches the bit high and removes the clear from flip-flop INDI.
Controller status information, like disk status information is gated to the backplane through the two 8216's C4 and D4. The controller status lines are gated to the 8216's from either port B of IC A6 or port B of IC A5 during a memory read operation from either of the two controller status addresses.
Disk Controller Interrupts
The disk controller can generate four interrupts; sector interrupt (SECTI), index interrupt (INDI), overrun interrupt (OVERRUNI), and attention interrupt (ATTENTIONI). These are low true signals driven to the processor backplane and are received from the backplane by the PIC-8 board.
SECTI is generated from one Q output of flip-flop A7. This flip-flop is clocked to the set state on the front edge of the disk index pulse and cleared under program control by the generation of signal CLRINDI.
OVRUNI is generated from the Q output of flip-flop A9 on TIFB. The flip-flop is clocked to the reset state on the front edge of either a disk sector pulse or index pulse occurring with either flip-flop SECTI or INDI in the set state. This indicates the passing of a sector without servicing a sector of index interrupt.
ATTENTIONI is a signal received directly from the disk drive, and indicates a seek operation has been completed. The signal will become true at the completion of a first seek rezero, seek, seek incomplete, or when an emergency retract occurs. The signal will be reset by issuing a disk read command.
Processor Memory Access
The processor access path to the disk controller memory is shown in FIG. 50. Backplane address lines A8, A9 an A10 are decoded by the one of eight decoder IC F3 located at TIFA and five chip select signals BADDENAI through BADDENA5 are generated. These are low true signals. BADDENA1 selects the bottom 256 bytes of memory and BADDENA5 selects the top 256 bytes.
Address lines A8, A9 and A10 are gated through tri-state hex buffers IC F4 and this gating creates an AND/OR function which enables the use of the one of eight decoder for both processor and controller memory access. The enable term for processor access is signal A. This is a low true signal and is generated from the AND of ENA DISKBFR and BOARD ENA. ENA DISKBFR (enable disk buffer) is a controller control bit and must be set (high) for the processor to access the controller memory. BOARD ENA (board enable) is generated from the output of the address pallet and is the AND of backplane signals A15, pallet A14 through ALL, SOUT and SINP.
BOARD ENA true indicates that the top five bits of the backplane address decode as the controller address range, the processor is not doing a device input or output.
Signal A is also used to enable the gating of the processor address lines (A0 through A7) and the processor write signal PWR to the controller memory chips. The gating for these lines are tri-state hex buffers IC's F4, F5 and C3 located on TIFA. These gates create an AND OR function with the controller address counter, which addresses the memory during disk data transfers.
The processor data path to the memory chips is through IC's C5 and D5. The chip select signal for these gates is signal A, and the part enable signal is the processor backplane memory read signal MEMR. During a processor read, the eight memory data lines are gated from the memory chips to the backplane, and during a processor write, the eight processor data output lines (D00 through D07) are gated from the backplane to the memory chips.
The memory chips have common input/output data pins, and during read the outputs are enabled and during write the outputs are disabled. During processor reads, the outputs are enabled by a low true signal OD (output disabled) generated at gate E6 on TIFB. The signal is the AND of MEMR (memory read) and signal B high. B is the complement of A, which is low true, and therefore OD low is the AND of processor memory read and signal A true.
Controller Memory Access
During disk data transfers, memory access control is as shown in FIG. 51. The top three bits of the address counter, IC D3 on TIFA, are gated into the one or eight decoder F3 by Signal B, and generate the memory chip selects. The lower eight memory address lines BA0 BA7 are generated by the lower eight bits of the address counter IC's C1 and D1, and these lines are enabled to the memory chips by signal B.
Memory read/write enable signal BWRD is generated at IC E2 pin 3 on TIFB and is high during disk writes, which are memory reads. During disk reads, BWRD is generated from the output of the bit counter IC C9 on TIFB, and provides low true memory write pulses.
During disk writes, memory chip outputs are enabled by signal OD (low true). This signal is generated from the AND of BUS2WR (write line to disk drive) and signal A high. A is the complement of B, which is low true and therefore OD low, during disk writes, is the AND of the disk write line and signal true.
During disk reads, the memory chip outputs are disabled and signal OD is high. The serial read data is clocked into shift register E3 and TIFA, and every eight bit clock times is parallel loaded into latch E2 with signal LOAD READ BFR. The outputs of latch E2 are three state and are enabled to the memory chips by the AND of ENA DISKBFR (low) and INHIBIT WRT (high). ENA DISKBFR is a controller control bit and must be reset (low) for disk read and write operations. INHIBIT WRT is generated at IC C7 on TIFB and is the BUS 3RD read line to the disk drive.
During disk writes, the outputs of the memory chips are enabled, OD (low) and the write data, memory read data, is parallel loaded into shift register E3 by signal LOAD SR, and serially clocked out with clock pulses from the disk.
LOAD SR is generated from the AND of BUS 2 I/OP and the decoding of the lower three bits of the bit counter. This pulse is used during a disk write operation to latch the eight memory data bits into shift register E3. The shift register serial output (write data) is clocked, high order data bit first, with DATA CLOCK pulses received from the disk. The WRITE DATA is driven to the disk drive by differential driver AL located on TIFA.
BA COUNT is generated from the AND of the start count flip-flop E10, the decoded three low order bits of the bit counter, and the DATA CLOCK. BA COUNT is used to decrement the address counter IC's C1, D1, and D3. When the lower eight bits of the address counter are equal to the eight bit value loaded into the STOP ADDRESS latch, signal BASTOP (low true) is generated. This signal disables the BUS 2 WR signal to the disk, disables START CNT (start count), and generates signal STOP CNT (stop count.)
STOP CNT is the K term of flip-flop E10, and the flop-flop is clocked to the reset state on the next falling edge of signal DATA CLOCK. The flip-flop (E10) reset, enables the clear term to the bit counter and stops the generation of signals LOAD SR and BA COUNT.
Signal BA STOP is a controller input status bit and should be read to determine the completion of the write operation. Upon detection of this bit, the controller latch bits BUS 7 (head select), BUS 2 (write), E BUS 2 (enable bus 2) and CONTROL TAG should be reset.
DATA DISK TRANSFER
Write Sequence
Prior to a disk write, a programming sequence must have been executed to place the hardware in the correct state. That is, the following operations must have been completed. First, the disk controller resident memory must be loaded with the data to be written on the disk. The data must be in the correct format; zero preamble field, data field, CRC bytes and zero postamble field.
Second, a seek operation to the correct cylinder muwt have been completed. Third, the disk head address register must be set to the correct value. This could be accomplished by either a set heat command or multiple head advance commands. Fourth, the controller address counter must be loaded with the start value (high address) for memory access. Fifth, the stop address value must be loaded into the controller. This determines the write stop point within the lower 256 bytes of the controller memory area. Sixth, index and sector interrupts must be serviced and a count kept to determine the approaching sector number.
When the listed sequence has been completed, and the sector counter has been incremented to a value of one less than the sector number to be written, a disk write sequence may be initiated. This is done by loading a value into the controller delay counter, and then setting the head select bit (Bus 7) in the controller output latch (8255 IC A5). After the completion of these initial operations, the control tag, Bus 2 (write), and E Bus 2 (Enable bus 2) bits may be set in output latch A6.
Flip-flop SECT I is set on the front edge of the next sector pulse (pulse proceeding sector to be written). The Q output of this flip-flop clocks the flip-flop A9 of TIFB to the set state. The output of A9 ANDed with DATA clock decrements the delay counter. The counter counts down through zero to FF. This generates signal DELAY UP (low true). The AND of DELAY UP, BUS 2 I/OP, and STOP CNT (false) generates signal BUS 2 WR, which drives the write line to the disk starting a write data transfer.
BUS 2 WR also generates signal START CNT (Start count,) which is the J term of flip-flop E10 on TIFB, and enables the setting of the flip-flop on the falling edge of the next DATA CLOCK. The Q output of this flip-flop is used to disable the clear line to the bit counter IC C9, and therefore enables the generation of signals LOAD SR 8IC E9) and BA COUNT (IC E6).
Read Sequence
Prior to a disk read, as prior to a disk write, a programming sequence must be completed to place the hardware in the correct operational state. With the exception of the need to preload the controller memory buffer, the sequence to be completed prior to a read is the same as that for a write.
After the hardware setup sequence has been completed and the sector counter has been decremented to a value of one less than the sector to be written, a disk read operation may be initiated. This is done by loading a value into that controller delay counter, and then setting the head select bit (BUS 7) in the controller output latch (8255 ICA5). Note that the delay value loaded for a disk read should be greater than the value used for a disk write to insure that startin of the read operation within a zero data field.
Like the write operation, a disk read sequence is initiated by the detection of the sector pulse preceding the sector to be read. This enables the delay counter to be clocked by the disk data clock down through zero to FF, and generate signal DELAY UP (low true). The AND of DELAY UP, BUS 3 I/OP, and STOP CNT (false) generates signal BUS 2 RD, which drives the read line to the disk drive starting a read data transfer. Serial data a clock pulses are received with differential line receiver IC B1 located on TIFA. The data is clocked into shift register E3 on TIFA on the positive edges of data clock. The data is received high order bit first, and is shifted right to left, through the shift register. Upon the detection of a data bit in the next to high order bit position of the shift register, signal SYNC BIT is generated. The AND of SYNC BIT and BUS 3RD generates sigal START CNT, which is the J term of flip-flop E10 on TIFB. Flip-flop E10 is set on the falling edge of the next DATA CLOCK pulse, and the Q output of the flip-flop disables the clear to the bit counter and enables the generator of signal BA COUNT.
As in a disk write operation signal BA count is used to decrement the address counter, and signal BA STOP (low true) is generated when the lower eight bits of the address counter match the value loaded into the StOP ADDRESS latch. BA STOP disables the BUS 3RD signal to the disk and generates signal STOP CNT (stop count).
Signal STOP CNT is the K input to flip-flop E10, and the flip-flop is clocked to the reset state on the falling edge of the next DATA CLOCK. E10 reset disables the generation of more BA COUNT pulses.
Signal LOAD READ BFR (load read buffer) is generated from the ANd of BUS 3 I/OP, the decoding of the lower three bits of the bit counter and signal DATA CLOCK. This signal (LOAD READ BFT) is used during read data transfer, to parallel load eight bits of data into latch E2 on TIFA. The output lines of latch E2 are enabled to the controller memory chips by signal ENADISKBFR.
Memory write strobes are generated during disk reads from the AND of signal BUs #RD and the pin 5 output of flip-flop E10 on TIFB. The J, K and clock inputs to the flip-flop are taken from the two low order bits of the bit counter, and this circuitry generates a pulse equal to four data clock periods. The pulse begins on a bit count value of three and includes a bit counts of four, five and six.
Upon the detection of the input status signal BA STOP, a read operation should be terminated, by resetting the output latch bits BUS 7 (head select), BUS 3 (read), and CONTROL TAG.
CYCLIC REDUNDANCY CHECK CODE (CRC)
The CRC logic (FIG. 52) generates a 32 bit check code which is attached to the write data, during write operations, and is used during read operations to detect and recover errors.
The circuitry implements the division of the disk serial data by the fixed polynominal X.sup.32 + X.sup.23 + X.sup.21 + X.sup.11 + X.sup.2 + X.sup.0 and the generation of a 32 bit remainder. The remainder can be used to detect a wide class of errors and can be used to recover up to an elevent bit error burst.
Prior to a disk write, the 32 bit check code must be generated and appended to the write data located in the controller memory buffer. This is accomplished by performing a disk write with the write line to the disk off and then reading the 32 bit check code from the logic and then storing the four bytes of check code the CRC logic should be placed in FULL, CIRCULAR mode. This is accomplished by setting these bits in the controller output latch A6 located on TIFB. With these control bits set, a disk write operation should be completed with the E BUS 2 (enable bus 2) bit left off, preventing the write bus line from being driven to the disk. The serial disk write data is exclusive ORed with the high order bit (Bit 31) of shift register F6 and the output of this gate is exclusive ORed with bits 22, 20, 10 and 1. This gating implements the division of the data stream by the desired fixed polynominal. The logic is clocked by signal SRCLOCK which is generated from the disk DATA CLOCK.
When the write operation is completed, without the write line enabled, the 32 bit remainder is left in the logic with the high order byte in shift register E3 on TIFA. This byte is read into the processor with a memory read from port B of ICA6 on TIFB. The byte should then be appended to the write data by storing it in the controller memory buffer in the first location following the data block. The second remainder byte is read from the logic by resetting the CRC circular bit, shifting the register eight times, and performing a read operation from port B of IC A6. The second byte should be appended to the data block in the second memory location following the data. Shifting of the register is accomplished by setting and resetting control bit SSCRC in latch A6 eight consecutive times.
The third and fourth remainder bytes should be read from the logic and stored into the buffer area by repeating the procedure described for the second byte.
After the memory has been set up with the CRC bytes, a disk write operation may be performed with the E BUS 2 bit set, enabling the disk write line.
Prior to a read operation, the CRC shift register must be cleared. This is accomplished by setting and then resetting CLEAR CRC bit in latch A6. During a read operation the CRC logic should be enabled in CIRCULAR and FULL mode. This is accomplished by setting these bits in output latch A6 prior to the read.
As with the write data, the serial data read from the disk is clocked by the disk DATA CLOCK and exclusive ORed with the high order bit of the CRC shift register (Bit 31). The output of this gate is exclusive ORed with CRC bits 22, 20, 10 and 1. This gating implements the division of the serial read data by the desired polynomial and generates a 32 bit remainder. The last four bytes of the read data are the CRC bytes stored on the disk during a write and the division of these bytes by th fixed polynominal should result in a zero remainder. Therefore, the CRC logic should be check after a read for 32 bits of 0. This is accomplished by following the procedure described on the generation of the CRC for a write operation.
If after a disk read, the CRC registers do not contain zero a retry procedure should be implemented.
DISK MEMORY ORGANIZATION
The external processor views the disk controller as a 2K block of memory and a series of 4 interrupts. The 2K block of memory is jumper-selectable for any 2K boundary in the range 8000 (32 .sub.10 K) to FFFF .sub.16 (65.sub.10 K).
The memory is partitioned into two segments. The first 1.25K bytes are allocated as the disk buffer area and corresponds directly with onboard memory. The remaining 0.75K of memory can be viewed as pseudomemory. The first 256 bytes are not used and the remaining 512 bytes are used as the address space for the memory-mapped 1/0. When information is read or written to these locations, it is not passed through memory but goes directly through to the controller logic. The only other path of communication between the controller and the outside are the 4 priority interrupt lines which the disk controller can raise.
INTERRUPTS
The disk controller has four interrupts it can raise: ATTENTION, SECTOR MARK, INDEX MARK, and OVERRUN. These lines are levels and stay present until they are reset by the programmer.
ATTENTION
This line is raised everytime the disk drive raises its attention flag. The disk will set its attention at the completion of any of the following operations:
1. First Seek: This is the initial seek at power-up.
2. Rezero: This is a command that performs the following operations:
a. Reposition the heads to cylinder 0
b. Reset seek-incomplete
c. Reset illegal-cylinder-address
d. Reset offset-heads
e. Set the head address register=0
3. Seek or Seek Incomplete: Therefore, any attempt to see whether or not successful with raise ATTENTION.
4. emergency Retract: This can occur on loss of line voltage or accidential opening of the disk enclosure at speed.
To reset ATTENTION, a read command must be sent to the drive. This is done by turning the Read Command bit on the bus on and then toggling the control Tag Line.
Usually a wait of some magnitude is associated with ATTENTION. Such events as first seek may take many seconds while a seek takes on the order of ms. In a multiprocessing environment, a wait on a seek is a good time for a task switch. The ATTENTION interrupt can then be used to "wake-up" the dormant disk handling process. With a dedicated processor like an 8080, a Halt or Jump self-wait may be appropriate. When the interrupt handler returns control will pass to the next statement following the wait. Suggested handling of an ATTENTION interrupt is as follows:
SECTOR MARK
This interrupt line is used if the disk drive unit has fixed length sectoring enabled. The disk drive is enabled by jumpering its Logic III board sockets A & 6B.
The disk drive electronics are also jumpered for the number of sector pulses per revolution. Each sector pulse generates an interrupt. These interrupts are used to keep track of the sector positions when the drive is in the fixed length sector mode.
Sector marks occur asynchronously with other processing activity. Unlike the ATTENTION interrupt, which the main line code expects, the SECTOR MARK interrupt is handled out of line. The interrupt is handled by updating the current sector to reflect the disk's current state.
The SECTOR MARK interrupt is cleared by toggling the CLR SEC INT control line from 0 to 1 and back to 0 again.
Structured Flowchart of Sector Interrupt Handler
INDEX MARK
This interrupt occurs at the start of each revolution. It enables the program to know at once during the revolution the absolute position of the disk. This allows the relative sector count to be reset if it loses track of where it is. Since the INDEX MARK interrupt occurs only 4.+-.1ms before the first sector, there will always be a sector interrupt pending at the completion of INDEX MARK handling. It is important to ensure that the INDEX MARK interrupt is of a higher priority than the SECTOR MARK interrupt.
A possible method of handling INDEX MARK interrupts is as follows:
OVERRUN
This interrupt occurs when a sector or interrupt mark is missed. It is raised when the following condition is true:
(SECTOR.sub.C + INDEX.sub.x) .multidot. (SECTOR .sub.D + INDEX.sub.D)
where
Sector.sub. c = the interrupt level raised by the controller processor on sector interrupts
Index.sub.c = the interrupt level raised by the controller for the processor on index interrupts
Sector.sub.d = the pulse sent from the disk drive to the controller to indicate a sector interrupt
Index.sub.d = the pulse sent from the disk drive to the controller to indicate an index interrupt
Note that OVERRUN interrupts will occur if the INDEX MARK or SECTOR MARK lines are not cleared. OVERRUN can be cleared by CLR SEC INT.
OVERRUN can be handled in a number of ways. The most general and safest is to assume the sector count is lost and resynchronize to the next index pulse. If the amount of time spent between interrupt services is known, a priori, the sector count can then be modified to bring it into proper accord. The latter algorithm is extremely hard to implement properly due to the fact that the controller must run with the processors interrupts enabled and should be avoided unless the time loss of 1 revolution (16.7ms) is highly critical. The general flowchart as follows: ##STR4##
CONTROL SIGNALS
This section contains lists and explanations of all signals that travel between the processor and the controller. As stated before, all these signals are transmitted and received via memory-mapped I/O. However, due to the fact that not all of the address bits are decoded, there is not a one to one correspondence between the memory location being mapped and the disk control functions, i.e., the same control function can be obtained by addressing different RAM locations. The memory space associated with the control functions resides totally within the disk controllers's address space. The disk controller's I/O mapping addresses all are of the form:
lJJJ Jlll XXXF FFF.sub.x F.sub.y
where
l - indicates bit always expected to be set
j - bits set via address jumpers
X - bits that are not decoded
F - bits that uniquely specify the control word that is requested.
Note: in DCW 10, DCW 11, DCW 12, DCW 13 bits F.sub.x and F.sub.y are NOT decoded
Each word so defined will be called a disk control word (DCW). It should be noted that the DCW's will form 8 blocks of 31.sub.10 words (lF.sub.16) each referred to as DCWB (DCW Block; see Figure 54). Each DCWB is equivalent to any other DCWB and can be used interchangeably.
Each DCW is broken down and described in detail below.
All but the first 2 conditions can be reset by a Device Check Reset command. The first 2 conditions are only reset by a Re-zero command.
DCW2 and Bits 0 and 1 of DCW6 make up the 10 bit bus. The meaning of each bit depends on the tag line that is raised in conjunction with it. There are 3 tag lines: Set-Cyl-Tag, Set-Head-Tag and Set-Control-Tag, which are controlled by bits 5-3 of DCW6 respectively. The bus is used in the following manner:
1. First the bus is loaded with data. The bus cannot be loaded until the drive has been selected for at least 200 ns.
2. Raise the appropriate tag line a minimum of 200 ns after the bus has been loaded.
3. Lower the tag line a minimum of 800 ns after it has been raised
4. Clear the bus
This determines the port assignment and functions for the 8255 Programmable Peripheral Interface. The setting specified above is necessary for proper operation of the controller. Both mode control words must be set before any other attempt to access the controller. For more specific information on the 8255 consult the Intel documentation provided. Note that bit 4 is a `1` in DCW3 and `0` in DCW7, i.e., DCW3=92.sub.16 and DCW7=82.sub.16.
This 8 bit word acts as a CRC register. It is loaded by toggling the Sngl Stp CRC Clk bit of DCW6 while the CRC logic is in the circular mode. ##STR12##
This counter initiates a delay before a read or write operation. This counter is turned on with the sector pulse that initiates the read or write operation. The I/O operation is held up until the delay counter counts down through 0, and then I/O operation is allowed to proceed. Typical values are 0 for writes and 24 for reads. ##STR13##
The stop counter allows the controller to complete its scan through the buffer on an I/O operation up to 255 bytes from the end of the buffer. This is necessary on read operations to prevent resyncing. Resyncing can arise when the read procedes past the trailing zero pad area of the sector into some undefined region of the on board buffer. Any "1" bit found in this area can cause the read logic to think the sync byte of the next sector has arrived. Subsequent reads will thereby be incorrectly synced and data recovery will be impossible.
PROGRAMMING
There are four major programming operations involved in controlling the disk, they are:
1. Power-up
2. Seek
3. Read
4. Write
Before delving into the aforementioned operations, it is useful to explain the error detection and recovery features of the controller.
The controller performs error detection via the CRC generator. The CRC is a 32 bit quantity which is accessed 8 bits at a time (MSB first) through DCW 5. Before actually writing a sector to the disk, the sectors CRC must be generated. This is done by performing all the steps of a disk write, but without the heads selected.
This drives the sector through the CRC generator. When this "face write" is completed, the code must single step the CRC logic 8 times to obtain the next significant byte of the CRC. This byte is then written into the sector by the program. The three remaining bytes of the CRC are to be extracted stored in the same manner. Once the CRC is safely stored away within the sector to be written, a normal write can be performed. The CRC generation flow chart is shown below.
The checking of the CRC on input is a much simpler task. A normal read is performed during which the CRC logic generates a CRC for the incoming data. This is then compared to the CRC currently written on the sector. If the two CRC's match then the 32 bit CRC value generated as an end result, will be zero.
On those cases in which the CRC returned during a read is not zero, error recovery comes into play. To recover marginal data two techniques are available. First, the read strobe can be advanced or retarded, and secondly the heads can be slightly offset in or out. By adjusting these two parameters nine different starting sector positions can be accessed. ##STR14##
POWER UP
The power up sequence is a relatively straight forward task. First the controller must initialize through the proper setting of its 8255's. Then the disk drive itself is powered up and brought online. The flow chart is as follows: ##STR15##
SEEKS
A seek is the act of positioning the heads at a specified cylinder. The disk drive contains a difference register which it uses to compute the relative address of the next cylinder requested. This relieves the programmer from having to keep track of current head positions. Basically the seek sequence consists of:
a. Selecting the drive.
b. Making sure the drive is in a seekable state, i.e., not busy or offset.
c. Loading the heads.
d. Issuing a cylinder address and seeking.
e. Checking to see if the seek came off as planned.
The details are given in a structure flow chart below.
However, the bus layout requires additional consideration.
The bus as defined above (DCW2, DCW6, Bus Definition) gives the appearance of a 10 bit field with bus 9 being the leftmost bit, and bus 0 being the right most bit. However, the drive's electronics expects Bus 9 to hold the least significant bit of any head or cylinder address. This imposes the restrictions of having to invert the addresses from their normal arithmetic form and to insure that these inverted addresses are left justified on the bus. ##STR16##
SECTORING
Before describing the I/O operations read and write, a few words should be said on sectorings and sector format.
Two types of sectoring are available: address mark sectoring and electronic sectoring. In address mark sectoring each sector is preceded by an address mark. A given sector is found by first positioning the heads to the specified track, then a read command is issued. This command activates the address mark detection circuitry. These circuits scan the disk for the next address mark. When the address is found it generates a 17 ns low going pulse which must be detected by the software. The software then drops the address mark bit and lets the read proceed. The software must then read the sector header and decide whether or not the sector found is the desired sector. If the sector gotten is the one desired, then the read continues. Otherwise, the address mark command is raised again and the scan of the track continues.
When writing a sector the sector must be proceded by an address mark. Address marks are written by raising address mark bit Bus 4 while a write command is active. Address marks have the advantage of being able to handle variable length sectors and of possibly being slightly more efficient in the use of disk space, (i.e., they have no internal fragmentation but external fragmentation still is present). However, these advantages are offset by the added complexity in finding specified sectors and by latency problems when the average sector length is short.
In electronic sectoring a fixed number of sector pulses are issued per revolution (jumper selectable by the user) and an index pulse occurs once per revolution. By simply counting the sector pulses and resetting the sector count each index pulse, the rotational position of the disk is always known. When a read or write command is issued, it is not acted upon until the next sector pulse. The idea being that the software find the sector pulse before the one required, thereby causing the required sector pulse to initiate the I/O operation.
READ
Reading can be broken into two major components, the physical disk read and the error check. The Physical disk read consists of the bit manipulation necessary to load the proper DCWs and the atual read opration. After the sector is read it is error checked in two ways. First, the CRC is checked. If the CRC is valid then the second ID field is checked. If both are valid, then the read completes normally. Otherwise, the software should attempt to recover the data by advancing and retarding the read strobe and also by offsetting the heads forward and backward before flagging a fatal error. The flow chart is as follows: ##STR17##
Writing
The write operation can be divided into two functional parts. Firstly, there is the generation of a CRC code for the sector to be written. This process was outlined in detail above. Secondly, is the setting up and performance of actual physical disk write. Additionally a read back write check to ensure data integrity is strongly recommended. Unless time constraints are extremely critical, a read back write should not be bypassed. The structured flow chart is as follows: ##STR18##
Decision Constructs ##STR19## The Disk Driver Firmware can be partitioned into four functional blocks.
1. Interrupt Handlers
2. Disk Driver Resident Monitor DDLRM
3. high Level Routines
a. Read (HLRD)
b. Write (HLWRT)
c. Initiative (INHT)
4. low-Level Routines
a. Communication Routines i.e. mailbox manipulation
b. I/O support routines
c. General unitity routines like more data and memory.
The following discussion will only involve the first three groups. The Low Level routines are either discussed in detail elsewhere or are of a trivial nature and not of general interest
Interrupt Handlers
In addition to the four interrupts generated by the Disk Controller, there is an additional interrupt called POWER-UP. This interrupt handler does the following tasks:
1. Waits for the master processor to initiate shared memory.
2. Performs a disk power up sequence.
3. Sizes the controllers local memory.
4. Sets up the Disk Driver's stack.
5. Transfers control to DDLRM (Disk Driver Level resident monitor)
Disk Driver Level Resident Monitor
DDLRM is the traffic controller of the Disk Driver level. It scans the mailbox queues for any messages. If a message is found, then it verifies that it is a message to him. If it is he processes it by invoking the proper high level routine to service the request. Otherwise he returns the mailbox to the queues and exits. The interrupt handlers and their associated 8080 vectored interrupt lines are:
1. PUIH - Power Up Interrupt Handler invoke via a RST 0 console restart not tied to vector or interrupt lines.
2. OIH - Overrun Interrupt Handler VI6.
3. imih - index Mark Interrupt Handler, V15
4. smih - sector Mark Interrupt Handler, V14
5. atnih - attention Interrupt Handler VI1
High Level Read HLVRD
This routine performs the high level read functions. It first extracts and verifies the cylinder and head address information from the mailbox. It then passes this information to the low level seek routine.
If the seek has successfully completed, then HLVRD will extract the sector address from the mailbox and perform the actual read.
At successful completion control is passed to DDLRM; otherwise an error message is formatted and sent to the DBMS level followed by a return to DDLRM.
High Level Write Routine HLVWT
This routine provides the high level write function. First it extracts and error checks the cylinder and head address passed to it in the mailbox. If these are not valid, further processing is aborted.
Otherwise a seek is attempted. Upon successful completion of the week, the sector address is extracted and error checked. If valid, then a write is attempted. After each write, a read back write check is performed to insure data integrity.
Systems Software
The systems software resident at the communications, DBMS and storage levels is set forth in detail below. FIGS. 31-37; and FIGS. 38-45 are flow charts for various routines at the commuications and DBMS level, respectively. FIG. 46 is a flow chart of the mailbox routine which is common to all three processor levels.
The communications level routines and subroutines are as follows:
Line handler
level exec
strcv
chkms
chksm
encod
isack
sndms
sndmi
xmton
usart interrupt service
clock interrupt service
initialization
input and output routines
the DBMS level routines and subroutines are as follows:
Get/put
dodsk
docmd
put
get
head/sector xlation table
copid
cmdtb
indsk
debug
move
copy
tradd
error processing
initialization
routines
boxes
error messages
syntax scanner
skcom
nytch
hexno
the storage level routines and subroutines are as follows:
Error recovery
error messages
error recovery routines
abort error handlers
read/write
overrun interrupt handler
index mark interrupt handler
sector mark interrupt handler
attn interrupt handler
hlvrd interrupt handler
hlvrd
hlvwt
gchfm
gsafm
loadb
seek
write
read
sbbsr
isrs
ret
dcr
gibs
iogo
rdwrt
lcrcr
scrcc
sizem
shftl
clrin
lhadr
samsg
general purpose
pwr up/interrupt handler
move
fill
the mailbox routines commn to all three levels are as follows:
Sret
grab
gboxt
gboxb
rcvt
rcvb
rignr
the detailed software steps are as follows: ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11##
Information storage facilities fabricated in accordance with the teachings of the invention are extremely flexible and can be adapted to an extremely wide variety of user requirements. For example, if more storage is required, additional data storage devices and storage level processors can be added. If a more complex data base management service is required, additional processors are added at the DBMS level. Similarly, if additional communications capability with external devices is required, additional processors may be added at the communications level. When used in conjunction with one or more host computers, the invention eliminates the requirement for repeated high speed data transfers between the storage facility and the host computers. Thus, each host computer is freed to perform more sophisticated processing functions and thus the computer time is used in a much more effective and efficient manner. Further, the invention provides a cost effectiveness hitherto unavailable in mass information storage facilities with an actual cost saving of several orders of magnitude.
By removing the data base management work load from the host computer, the invention increases system through put and available CPU processing power. Further, the invention reduces software development costs by eliminating the necessity of providing host processor software to handle record formatting, indexing, and buffering. In addition, the invention reduces memory requirements of the host processor by eliminating memory allocations for disk and record buffers in both systems and applications programs. Lastly, the invention premits multiple processors and/or intelligent terminals to access the same disc and is fully capable of communicating with intelligent terminals directly via standard communications lines using both synchronous and asynchronous communications techniques.
While the above provides a full and complete disclosure of the preferred embodiments of the invention, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the invention. For example, while the preferred embodiment has been shown as having two processors at the communications and storage levels, and four processors at the DBMS level, the actual number of processors employed at each level is a matter of system configuration design and largely dependent upon the particular requirements of a given application. Moreover, other data storage devices than disk installations may be employed for data storage, as desired. Therefore the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the appended claims.
Claims
What is claimed is:
1. A multi-level information storage facility for storing data base information in digital form and for enabling symbolic access to such information in response to information request signals from an external processing device, said facility comprising: a communications level processor means having an input/output port means for receiving said information request signals from said external processing device, said communications level processor means including means for initiating internal processing of said request signals and means for generating acknowledgment signals for transmission to said external processing device via said input/output port means; an intermediate level processor means for providing intermediate level processing of said request signals; first shared memory means coupled to said communications level and said intermediate level processor means for enabling data communication therebetween, said first shared memory means including a first cache memory device for storing initiating request signals generated by said communications level processor means and for storing resultant task signals generated by said intermediate level processor means; said intermediate level processor means including seek means for interrogating said first cache memory device in a predetermined sequence for said initiating request signals, means for generating intermediate level instruction signals in response to the detection of said initiating request signals, and means for storing said resultant task signals in said first cache memory device; storage level processor means having an input/output port means adapted to be coupled to a data storage device for controlling operation thereof; and second shared memory means coupled to said intermediate level and said storage level processor means for enabling data communication therebetween, said second shared memory means including a second cache memory device for storing said intermediate level instruction signals from said intermediate level processor means and for storing data received from said storage level processor means; said storage level processor means including means for interrogating said second cache memory device for said intermediate level instruction signals, means for generating storage level instruction signals in response to the detection of said intermediate level instruction signals for controlling storage and retrieval of portions of said data base information from said storage device, and means for storing said data received from said storage device in said second cache memory device.
2. The combination of claim 1 wherein said communications level processor means includes a plurality of processor units each having input/output port means adapted to be coupled to a plurality of external processing devices.
3. The combination of claim 1 wherein said intermediate level processor means comprises a plurality of processor units coupled to said first shared memory means in parallel for data communication with said first processor means.
4. The combination of claim 1 wherein said storage level processor means includes a plurality of processor units each having input/output port means adapted to be coupled to a separate data storage device for controlling operation thereof.
5. The combination of claim 1 wherein said data storage device comprises a disk storage unit.
6. The combination of claim 1 further including a direct memory access bus coupled to said communications level, intermediate level and storage level processor means and adapted to be coupled to said external processing device for providing a high speed data transfer therebetween.
7. The combination of claim 6 wherein said direct memory access bus includes additional processor means for controlling the operation thereof.
8. The combination of claim 1 wherein said first and second cache memory devices each comprises an expandable cache memory.
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