Selective Calling Receiver

The present invention relates to a selective calling receiver and more particularly to a receiver having a sound circuit which generates an audible calling sound in response to a calling message and a display circuit for visually displaying the message received.

Conventionally, selective calling receivers have used an analogue signal as the selective signal. However, the use of digital signals as the selective signal has many functional advantages. In this case, the selective calling receiver includes a sound circuit which generates an audible sound as a calling signal and a visual display circuit which displays the message visually.

Liquid crystals, light emitting diodes (LED) etc., may be used as the display element of the visual display circuit. Liquid crystals have the disadvantage that their useful life is only about a year whereupon they must be replaced. Hence, light emitting diodes are frequently used. However, when using light emitting diodes, it is necessary to provide a control circuit for energizing the diodes only when the message is to be read in order to avoid power dissipation and short battery life. This control circuit is different from the control circuit which resets the sound circuit so as to stop the calling sound. Accordingly, it is a defect of selective calling receivers that use an LED display that they have many operating sections and that the operation of the LED display is difficult.

The method of resetting the sound circuit with a timer in order to simplify the operation has the disadvantage that the calling sound continues to be generated after it has attracted the attention of the recipient. This is particularly objectionable if the person receiving the call is in a meeting.

Selective calling receivers have accordingly heretofore had functional disadvantages as well as manufacturing disadvantages by reason of the number of parts required for the receiver and the labor involved in assemblying the parts.

It is accordingly a primary object of the present invention to provide a low cost selective calling receiver requiring a relatively small number of parts and yet providing excellent operating characteristics. In accordance with the invention, the selective calling receiver comprises a resettable sound circuit for generating an audible calling sound in response to a calling message, a display circuit for visually displaying a message and a control circuit for resetting the sound circuit so as to discontinue the calling sound and for simultaneously activating the display circuit so as to display the message.

The nature, objects and advantages of the invention will be more fully understood from the following description in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a preferred embodiment of the selective calling receiver in accordance with the present invention, and

FIG. 2 is a time chart explaining the action of the selective calling receiver of FIG. 1.

The embodiment of the invention illustrated in FIG. 1 comprises a sound circuit 1, a visual display circuit 17 and a control circuit 12.

The sound circuit 1 comprises an R-S flip-flop 2 composed of two NAND circuits 3 and 4, a known astable multi-vibrator 5 composed of a NAND circuit 6, inverter 7, resistor 8 and capacitor 9, a buffer amplifier 10 and a speaker 11. One input terminal of the NAND circuit 3 is the set terminal S of the R-S flip-flop 2 and receiver the calling signal having a negative logic and derived from the receiving section which is not shown in the drawings. One input terminal of the other NAND circuit 4 is the reset terminal R of the R-S flip-flop 2 and receives a control signal of negative logic level derived from the control circuit 12. The other input of the NAND circuit 3 is connected to the output of NAND circuit 4 and the other input of NAND circuit 4 is connected to the output of NAND circuit 3. The output of NAND circuit 3 is the output of the R-S flip-flop 2 and is connected to one input of the NAND circuit 6 of the astable multivibrator 5. The output of the NAND circuit 6 is connected through the inverter 7 to the buffer amplifier 10 of the speaker 11. The other input of the NAND circuit 6 is connected through the resistor 8 to the output of the NAND circuit 6 and is connected through capacitor 9 to the output side of the inverter 7.

The control circuit 12 comprises a manual switch 13, one terminal 13a of which is connected to ground corresponding to the logic level "0" while the other terminal 13b is connected to the reset terminal R of the R-S flip-flop 2 and through a resistor 14 to a terminal 15 corresponding to the logic level "1". Thus, the control circuit 12 produces a control signal of logic level "1" when the manual switch 13 is open and a control signal of logic level "0" when the switch 13 is manually closed.

The control signal provided by the control circuit 12 is thus fed to the reset terminal R of the R-S flip-flop 2 and is also fed through an inverter 16 to one input terminal of each of the NAND circuits A.sub.1 -A.sub.n which drive the display elements D.sub.1 -D.sub.n of the display circuit 17.

The display circuit 17 comprises a register 19 which stores the message fed to input terminal 18. The message is the coded calling content transmitted from the transmitter which is not shown in the drawing. The register 19 has output terminals Q.sub.11 -Q.sub.14 . . . Q.sub.n1 -Q.sub.n4 which provides BCD coded signals to the input terminals of corresponding transmission gates TG.sub.11 -TG.sub.14 . . . TG.sub.n1 -TG.sub.n4.

The output terminals of transmission gates TG.sub.11. . . TG.sub.n1 are connected in common, the output terminals of TG.sub.12. . . TG.sub.n2 are connected in common, the output terminals of TG.sub.13. . . TG.sub.n3 are connected in common, etc., and these common output terminals are respectively connected to input terminals of a decoder and driver 20.

The seven segment signal outputs of the decoder and driver 20 are connected through resistors 21.sub.a -21.sub.g respectively to the anodes of the LED display elements of each of the display units D.sub.1 -D.sub.n composing the digital display device D. The cathodes of the LED display elements of the display unit D.sub.1 are connected in common to the collector of a driving transistor Tr.sub.1. In like manner, the cathodes of the LED display elements comprising the display element D.sub.n are connected in common to the collector of a driving transistor Tr.sub.n. The emitters of transistors Tr.sub.1 and Tr.sub.n are connected to ground.

The output signal of the NAND circuit A.sub.1 is fed to one of the control terminals of each of the transmission gates TG.sub.11 -TG.sub.14 and is also fed through an inverter B.sub.1 to the other control terminals of transmission gates TG.sub.11 -TG.sub.14. The output signal of the NAND circuit A.sub.n is fed to one of the control terminals of each of the transmission gates TG.sub.n1 -TG.sub.n4 and is fed through an inverter B.sub.n to the other control terminals of transmission gates TG.sub.n1 -TG.sub.n4.

The output signal of the NAND circuit A.sub.1 is fed to the base terminal of the driving transistor Tr.sub.1 through an inverter C.sub.1 and the output signal of the NAND circuit A.sub.n is fed to the base terminal of the driving transistor Tr.sub.n through the inverter C.sub.n.

Driving pulses P.sub.1 -P.sub.n which differ from one another in phase and which are produced by a driving pulse generator not shown in the drawing are applied to input terminals a.sub.1 -a.sub.n of the NAND circuits A.sub.1 -A.sub.n periodically.

The action of the selective calling receiver in accordance with the invention will now be described with reference to the time chart shown in FIG. 2. FIG. 2 shows the wave shapes of input signals and output signals of respective circuit components which are designated by the same reference numerals as in FIG. 1.

In the normal state in which the switch 13 of the control circuit 12 is open and the selective calling receiver is not called by the selective calling transmitter, the set terminal S and the reset terminal R of the R-S flip-flop 2 are at the logic level "1". As this time, the output signal of the NAND circuit 3 is in the state of logic level "0". The astable multivibrator 5 is maintained in a nonactive state since the NAND circuit 6 of the multivibrator receives the logic "0" output signal of the NAND circuit 3.

The output signals of the NAND circuits A.sub.1 -A.sub.n of which the input terminals receive the output signal of the control circuit 12 through the inverter 16 are maintained at the logic level "1" since the output signal of the control circuit 12 is in the state of logic level "1" as the switch 13 is open.

The transmission gates TG.sub.11 -TG.sub.14 and TG.sub.n1 -TG.sub.n4 are in the off state because of the output signals of the NAND circuits A.sub.1 -A.sub.n. The driving transistors Tr.sub.1 -Tr.sub.n of the display device D are in the off state since the base terminals of the transistors are at a low electric potential by reason of the output signals of NAND circuits A.sub.1 -A.sub.n transmitted through the inverters C.sub.1 -C.sub.n. Accordingly, the display apparatus D of the display circuit 17 is maintained in a nonactive state.

When the selective calling receiver receives a message and selective calling signal from the transmitter (not shown) at the time t.sub.1 in FIG. 2, the message is stored in the register 19 and at the same time, the set terminal S of the flip-flop 2 receives a signal of the logic level "0". In response to this signal of the logic level "0", the output signal of the NAND circuit 3 in the R-S flip-flop 2 is inverted from the logic level "0" to the logic level "1". The astable multivibrator 5 is thereby activated and oscillates at a period corresponding to the time constant determined by the resistance of the resistor 8 and the capacitance of the capacitor 9 whereby the multivibrator 5 produces an oscillating signal as shown in FIG. 2. The buffer 10 amplifier this oscillating signal in current whereby the speaker 11 is driven to produce an audible signal. Thus, the second circuit 1 is actuated by the selective calling signal.

When the operator who has heard the audible signal produced by the sound circuit 1 actuates the manual switch 13 of the control circuit 12 at the time t.sub.2, the reset terminal R of the flip-flop 2 receives the control signal of the logic level "0" so that the output signal of the R-S flip-flop 2 is inverted. Therefore, the output signal of the NAND circuit 3 becomes logic level "0" whereby actuation of the astable multivibrator 5 is stopped.

On the other hand, since the switch 13 is now in ON position, the output signal of the control circuit 12 becomes logic level "0" and accordingly the output signal of the inverter 16 becomes logic level "1". The NAND circuits A.sub.1 -A.sub.n are thereby activated so as to produce driving pulses P.sub.1 -P.sub.n as the output signals thereof respectively. Accordingly, transmission gates TG.sub.11 -TG.sub.14 are periodically switched ON and OFF in synchronization with the period of the driving pulse P.sub.1. The transmission gates TG.sub.n1 -TG.sub.n4 are similarly switched ON and OFF in synchronization with the period of the driving pulse P.sub.n. The driving pulses P.sub.1 -P.sub.n are respectively different in phase so that transmission gates TG.sub.n1 -TG.sub.n4 are in the OFF state when transmission gates TG.sub.11 -TG.sub.14 are in the ON state.

The output signals of the register 19 are fed to the decoder and driver 20 in a time sharing manner by reason of operation of the transmission gates TG.sub.11 -TG.sub.14 . . . TG.sub.n1 -TG.sub.n4 as described. FIG. 2 shows the wave shape of the output signals of TG.sub.n, TG.sub.12, TG.sub.n1 and TG.sub.n2 in the state in which the output signals of the terminals Q.sub.11, Q.sub.n1 and Q.sub.n2 of the register 19 are in the state of logic level "1" and the output signal of the terminal Q.sub.12 is in the state of logic level "0".

The driving transistors Tr.sub.1 -Tr.sub.n are switched ON and OFF periodically in response to the output signals synchronized with the driving pulses P.sub.1 -P.sub.n derived from the output terminals of the NAND circuits A.sub.1 -A.sub.n. Accordingly, the display device D is driven in a dynamic state in the period of the driving pulses P.sub.1 -P.sub.n and visually displays the stored contents of the register 19.

At the time t.sub.3, when the switch 13 is switched to the OFF state, the output signal of the control circuit 12 changes from logic level "0" to logic level "1". At this time the display circuit 17 ceases to operate since the NAND circuits A.sub.1 -A.sub.n inhibit passage of the driving pulses P.sub.1 -P.sub.n.

Also, the input of the resetting terminal R changes from the logic level "0" to the logic level "1". In this case, the output state of the R-S flip-flop 2 does not change and hence the sound circuit 1 is maintained in an nonactive condition. As mentioned above, the sound circuit 1 is reset and at the same time the display circuit 17 is set by the operation of the switch 13. Accordingly, the selective calling receiver in accordance with this invention eliminates the complicated operation required by the multifunction of the selective calling receiver. Also, the selective calling receiver in accordance with the invention can be manufactured at low cast because of the small number of components.

It will be obvious to those skilled in the art that many modifications and variations of the circuitry described above may be made. Hence, the invention is in no way limited to the preferred embodiment illustrated in the drawings and herein particularly described.

As mentioned above, the selective calling receiver in accordance with the invention has such circuit structure that the sound circuit is reset and at the same time the display circuit is set by the operation of a single switch. Thus, the switch performs both the operation of displaying the received message and of stopping the audible calling signal so that operation of the receiver is easy.