Polyphonic Tone Synthesizer

1. Field of the Invention

The present invention relates to a polyphonic musical instrument wherein tones are produced by computing a master data set, transferring the data to buffer memories, and converting buffer memory contents to musical sounds.

2. Description of the Prior Art

The advantages of digital waveshape generation in an electronic musical instrument are outlined in U.S. Pat. No. 3,515,792 and U.S. Pat. No. 3,809,786. Such advantages include

A. realistic simulation of organ tones and other musical sounds such as piano, flute, bells, plucked strings;

B. production of the same waveshape, and hence tonal quality, regardless of which note or octave is being played;

C. simplified implementation of both foundation and mutation stops;

D. controlled selection of the attack and release characteristics of the produced musical notes;

E. all electronic operation; and

F. ease of construction using batch fabricated, digital microelectronic techniques.

In the organ described in U.S. Pat. No. 3,515,792, musical notes are produced by storing a digital representation of a waveshape characteristic, e.g. of an organ pipe tone, and repetitively reading out this stored waveshape at a selectable clock rate determining the fundamental frequency of the produced note. Stored in the waveshape memory are the actual amplitude values at a plurality of sample points. A frequency synthesizer produces a clock signal at a rate determined by the note selected on the organ keyboard or pedals. The stored amplitudes or amplitude increments are read out of the memory repetitively at the selected clock rate (which differs for each note) to generate the selected musical tone. Attack and decay is provided by programmed division, or division and subtraction, of the read out amplitude or increment values.

In the organ described in U.S. Pat. No. 3,809,786, musical notes are produced by computing the amplitudes at successive sample points of a complex waveshape and converting these amplitudes to notes as the computations are carried out. A discrete Fourier algorithm is implemented to compute each amplitude from a stored set of harmonic coefficients C.sub.n and a selected frequency number R, generally a non-integer, establishing the waveshape period. The computations, preferably digital, occur at regular time intervals t independent of the waveshape period. At each interval t the number R is added to the contents of a harmonic interval adder to specify the waveshape sample point qR, where q = 1,2,3, . . . For each point qR, W individual harmonic component values C.sub.n sin(.pi.nqR/W) are calculated, where n = 1,2,3, . . . ,W. These values are algebraically summed to obtain the instantaneous waveshape amplitude, which is supplied to a digital-to-analog converter and a sound system for reproduction of the generated musical note. Attack, decay and other note amplitude modulation effects are obtained by programmatically scaling the harmonic coefficients. In a polyphonic musical instrument system, time sharing and multiplexing is used to calculate separately the sample point amplitudes for each selected note, these amplitudes being combined by summation to produce the desired ensemble of musical sound.

The DIGITAL ORGAN described in U.S. Pat. No. 3,515,792 is not readily adaptable to modern musical instruments of the synthesizer variety wherein the tonal characteristics of a note must be capable of smooth continuous time variations. The waveshape stored in memory is a rigid representation of a prespecified tonal structure. Expensive digital filters are required to modify the harmonic structure of the stored waveshapes. Another serious drawback inherent in the use of stored waveshapes is the need for high system logic clock frequencies in a time-shared implementation of a polyphonic system. Tone synthesizers require tones corresponding to about 32 harmonics. At C.sub.7, the 32'nd harmonic yields a frequency of 2093.times.32=67Khz; far above the audible range. The effective single channel clock frequency required to read such a waveshape at C.sub.7 is 2.times.67=134Khz. A time shared 12 note polyphonic system that operates by multiplexing a single waveshape memory would require a minimum system logic clock of 1.6Mhz.

The COMPUTER ORGAN described in U.S. Pat. No. 3,809,786 overcomes many of the modern tonal musical problems caused by the inflexible waveshape in memory characteristics of the Digital Organ. The Computer Organ has a very severe requirement for fast system logic clocks. For a single channel generating a 32nd harmonic tone at C.sub.7, the system logic clock must operate at a frequency of 4.29Mhz. A timed shared 12 note polyphonic system using a single computation channel requires a minimum system logic clock of 51.43Mhz. If harmonic limiting is used with the Computor Organ as described in U.S. Pat. No. 3,809,789, then for a maximum frequency of 20.9Khz (tenth harmonic of C.sub.7), a single channel system requires a clock at 1.34Mhz and a 12 note polyphonic system requires a minimum system logic clock of 16.1Mhz. Further reduction of the system clock frequency can be accomplished by using additional circuitry as described in U.S. Pat. No. 3,809,788.

An object of the present invention is to provide a polyphonic electronic musical instrument wherein time varying waveshape synthesis is accomplished in a manner totally different from that known in the prior art, yet exhibiting all the above listed advantages of digital waveshape generation while using clock speeds compatible with economical batch fabricated digital microelectronic devices.

Other objects and features of the invention will become apparent in conjunction with the following descriptions and drawings.

The foregoing objective is achieved by providing a polyphonic electronic musical instrument wherein a computation cycle and a data transfer cycle are repetitively and independently implemented to provide data which is converted to musical notes. During the computation cycle a master data set is created by implementing a discrete Fourier algorithm using a stored set of harmonic coefficients which characterize the basic resultant musical tone. The computations are carried out at a fast rate nonsynchronous with any musical frequency. Provision is made for time varying the amplitudes of the computational orthogonal functions so that the musical effect of sliding formant filters is generated. Preferably, the harmonic coefficients and the orthogonal functions are stored in digital form, and the computations are carried out digitally. At the end of the computation cycle a master data set has been created and is temporarily stored in a data register.

Following a computation cycle, a loading cycle is initiated which transfers the master data set to a collection of read-write memories. The transfer for each memory is initiated by detection of a synchronizing bit and is timed by a clock which is asynchronous with the main system logic clock and has a frequency of Pf, where f is the frequency of a particular note assigned to a memory and P is two times the maximum number of harmonics in the musical waveshape. The transfer cycle is completed when all of the memories have been loaded, at which time a new computation cycle is initiated. Tone generation continues uninterrupted during computation and load cycles.

A time shared digital-to-analog converter transforms the output data from the read-write memories to analog voltages assigned to individual tone channels. The digital-to-analog converter is time sequenced with each memory output data conversion to provide attack, decay, sustain, release, and other amplitude modulation effects.

A detailed description of the invention will be made with reference to the accompanying drawings wherein like numerals designate like components in the several figures.

FIG. 1 is a block diagram which illustrates the computation cycle and load cycle of the present invention.

FIG. 2 shows typical musical waveshapes generated by the musical instrument of FIG. 1.

FIG. 3 is a block diagram illustrating a harmonic combination subcycle of a computation cycle.

FIG. 4a illustrates the frequency-amplitude response of a conventional analog low-pass filter.

FIG. 4b illustrates the frequency-amplitude response of a conventional analog high-pass filter.

FIG. 4c illustrates the harmonic number-amplitude relation for an effective low-pass formant filter.

FIG.4d illustrates the harmonic number-amplitude relation for an effective high-pass formant filter.

FIG. 5 is a block diagram showing means for obtaining sliding formant filters.

FIG. 6 is a block diagram of a polyphonic tone synthesizer showing means for harmonic limiting during computation cycle. FIG. 7 is a block diagram of polyphonic tone synthesizer illustrating transfer from asynchronous to synchronous clocks and time shared digital-to-analog conversion.

FIG. 7a is a diagram of timing sequence for time shared digital-to-analog conversion.

FIG. 8 is a block diagram showing means for division couplers.

FIG. 9 is a block diagram illustrating synchronizing bit detection and attack/release counters.

FIG. 10 is a logic diagram showing operation of synchronizing bit detector and note select control signal.

FIG. 11 is a block diagram of polyphonic tone synthesizer using Walsh functions.

FIG. 12 is a block diagram of polyphonic tone synthesizer in accordance with present invention.

The following detailed description is of the best presently contemplated modes of carrying out the invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention since the scope of the invention is best defined by the appended claims.

Structural and operational characteristics attributed to forms of the invention first described shall also be attributed to forms later described, unless such characteristics are obviously inapplicable or unless specific exception is made.

The polyphonic tone synthesizer 10 of FIG. 1 operates to produce via a sound system 11 a musical note selected by actuating a switch associated with instrument keyboard switches 12. FIG. 2 illustrates typical musical waveshapes supplied to the sound system 11 via a line 13 when the instrument keyboard switch associated with the musical note C.sub.7, C.sub.6 or G.music-sharp..sub.5 respectively is actuated. As described below, each such waveshape is generated by first computing a master data set. The master data set is then transformed to the time domain (data amplitudes become a function of time) and finally is stretched in time so that its fundamental period (i.e. first harmonic period) corresponds to the actuated switch on the instrument keyboard 12.

It is well known that a musical sound characteristic of a particular instrument includes sinusoidal components of the fundamental and other generally harmonically related frequencies. The relative amplitudes of these components determine the tonal quality of the sound independent of the relative phase of the individual components.

A musical signal reproduced by a sound system 11 having an amplifier and speaker generally consists of an analog voltage having a waveshape (i.e. voltage as a function of time) which is a superposition or composite of the harmonic components of the corresponding sound. Such a complex waveshape may be described mathematically in terms of its harmonic components by the wellknown Fourier series equation for a periodic waveshape. The circuitry of 10 of FIG. 1 operates by first synthesizing a master data set computed by the following discrete Fourier series ##EQU1## where N = 1,2, . . . ,2W is the number of a master data set word, q = 1,2, . . . ,M is the harmonic number, M = W is the number of harmonics used to synthesize the master data set, c.sub.q are the harmonic coefficients for tone No. 1, and d.sub.q are the harmonic coefficients for tone No. 2. q is sometimes called the order of the harmonic component. While the invention is illustrated for combination of two tones or "stops," the extension to any plurality of tones should be apparent to those skilled in the art. The number of harmonics, M, is a design choice, however the use of 32 harmonics (M = 32) is satisfactory for synthesizing the "bright" tonal sounds of a musical tone synthesizer. M can be a number less than or equal to W .multidot. W=N/2 is the maximum number of harmonics possible for a master data set having N words.

After the master data set has been computed, the circuitry 10 of FIG. 1 operates by stretching such data to correspond to musical notes actuated on the instrument keyboard switches 12.

Whenever a switch is actuated on the instrument keyboard switches 12, its actuation is detected by the note detect and assignor 14. The detection of an actuated key causes the assigning of a temporary memory in 14 containing data that identifies which particular key switch has been actuated. The note detect and assignor 14 transmits via line 59 to executive control 16 the information that a key has been detected as having been actuated on the instrument keyboard switches 12.

Circuitry suitable to implement the note detect and assignor are known in the art and one such system is described in U.S. Pat. No. 3,610,799 entitled Multiplexing System for Selection of Notes and Voices in an Electronic Musical Instrument.

The logic timing for the circuitry of FIG. 1 is controlled by the master clock 15. One such control line 17 is shown leading to executive control 16. A fairly wide range of frequencies can be used for the master clock 15; however advantageously a design choice is 1.1352Mhz.

The executive control 16 transmits control signals to several of the logic blocks to synchronously time various logic functions. Line 18 is one such line which transmits logic control signals from executive control 16 to note detector and assignor 14. The operation of system 10 is described for binary numbers and negative values are obtained by conventional "2's complement".

The computation cycle is defined as a repetitive event whose function is to compute Equation 1. At the beginning of the computation cycle the word counter 19, the harmonic counter 20, and the adder-accumulator 21 are all initialized to their initial state. That is, each device is set so that it has a value of 1. Table I lists the contents of the system logic blocks that are used during the computation function. At time t.sub.1 corresponding to the first bit time of the computation cycle the word counter 19 content is the number one. The harmonic counter 20 also has the number one. The number in 20 is transmitted via gate 22 to the adder-accumulator at time t.sub.1. The memory address decoder 23 receives the number from the adder-accumulator 21 and causes the value sin 2.pi.(1.times.1)/W to be read out from the sinusoid table 24. For brevity, Table I uses the notation

and the sine table address is abbreviated using the symbolic notation

The memory address decoder 25 receives the number contained in word counter 19 to select either harmonic coefficient memory 26 or harmonic coefficient memory 27. The selection is accomplished by a modulo 32 counter connected to a bistable gate so either one or the other harmonic coefficient memories is addressed. In addition to selecting a harmonic coefficient memory, memory address decoder 25 also addresses the appropriate harmonic number corresponding to each bit time in the computation cycle as indicated in Table I.

where

t: bit time in computation cycle

N: content of word counter 19

q: harmonic number; content of harmonic counter 20

Nq: content of adder-accumulator 21

Sa: sine table address

Hc: harmonic coefficient input to multiplier 28

Add: input to adder 33

Mr: current word address for input to main register

Mrc: content of main register at address MR

(n.times.q): .pi.Nq/W

At time t.sub.1, memory address decoder 25 causes the harmonic coefficient c.sub.1 to be read from harmonic coefficient memory 26. The input signals to the multiplier 28 are c.sub.1 on line 29 and S.sub.1 on line 30. Therefore, the output of the multiplier is the numerical value c.sub.1 S.sub.1.

The functions of the complementer 31 and the phaser 32 will be described below after the other principle actions have been described for the computation cycle. Until these two functions are described, the operation will be explained under the assumption that the complementer 31 does not complement any of the input numbers so that positive and negative numbers are transferred from complementer 31 to adder 33 with no change of algebraic sign.

Main register 34 is a read-write set of registers which advantageously may comprise an end-around shift register. The contents of the main register 34 are initialized to a zero value at the start of the computation cycle. At time t.sub.1, the value c.sub.1 S.sub.1 is placed into word address 1 of the main register.

At the second bit time t.sub.2, word counter 19 is incremented to the value 2. The harmonic counter is maintained at the value of 1 and will retain this value during the first 32 bit times of the computation cycle. The adder-accumulator 21 receives the current value of q from harmonic counter 20 at each bit time. Therefore at time t.sub.2, adder-accumulator has the value Nq=2. The value S.sub.2 corresponding to the address (2.times.1) is transferred from sinusoid table 24 to multiplier 28. Also at time t.sub.2, the harmonic coefficient C.sub.1 is read from harmonic coefficient memory 26. The output signal from the multiplier is the value c.sub.1 S.sub.2 which is added to the initial zero value of word No. 2 in main register 34 so that the net result is that the value c.sub.1 S.sub.2 is placed into the word position at time t.sub.2.

The first subroutine of the computation cycle is iterated for 32 bit times. At the end of the first subroutine, the contents of main register 34 are the first 32 values indicated in Table I under the column heading MRC (main register content).

Time t.sub.33 initiates the second subroutine of the computation cycle. At time t.sub.33, word counter 19 returns to its initial value of one because this device is a counter (modulo W), and W has been selected to have the value 32. The recycling of word counter 19 is detected by memory address decoder 25. This detection causes the memory address decoder to address harmonic coefficient memory 27 for the next successive 32 bit times in the computation cycle. The recycling of the word counter 19 is also detected by adder-accumulator 21 to cause it to return to a zero value. Therefore at time t.sub.33, adder-accumulator 21 receives the current value of one from harmonic counter 20. This value in turn causes value S.sub.1 to appear on line 30. Simultaneously the harmonic coefficient d.sub.1 appears on line 29. After multiplication, the value d.sub.1 S.sub.1 is added to the first word in main register 34 to produce the current value c.sub.1 S.sub.1 +d.sub.1 S.sub.1 as shown in the last column in Table I for bit time t.sub.33.

The second subroutine of the computation cycle is iterated for 32 bit times. At the end of the second subroutine computation cycle the contents of the main register are indicated in Table I under the entries for bit times t.sub.33 to t.sub.64.

Time t.sub.65 initiates the third subroutine of the computation cycle. At time t.sub.65, word counter 19 once again returns to its initial value of one. The recycling of word counter 19 is detected by memory address decoder 25 which in turn causes it to address harmonic coefficient memory 26 for 32 successive bit times. At bit time t.sub.65, harmonic counter 20 is advanced to the value q=2. It will retain this value for 64 successive bit times causing the harmonic coefficient c.sub.2 to be addressed 32 consecutive times followed by addressing d.sub.2 for the subsequent 32 consecutive bit times. At time t.sub.65, adder-accumulator 21 receives the current value q=2 from harmonic counter 20. The value c.sub.2 S.sub.2 will be added to the contents of word No. 1 in main register 34, which at this time will contain the value c.sub.1 S.sub.1 +c.sub.2 S.sub.2 +d.sub.1 S.sub.1. The third subroutine of the computor cycle is iterated 32 bit times. At the end of the third subroutine, the contents of main register 34 are indicated in Table I for bit times t.sub.65 to t.sub.96.

The fourth subroutine is similar to the third subroutine with the harmonic coefficient d.sub.2 replacing c.sub.2 that was used in the third subroutine. Thus, at bit time t.sub.97 the contents of word No. 1 in main register 34 is the value

the computation cycle proceeds with the various subroutines until the last 64 bit times have been completed for the value q=32 contained in harmonic counter 20. At the end of the computation cycle the values in each of the address numbers of main register 34 are the values given by Equation 1 where the subscript N=1,2, . . . ,32 corresponds to the main register address numbers.

It is not necessary to have 64 word numbers in main register 34 as indicated by Equation 1. Only one-half of these values need to be evaluated during the computation cycle because the remaining values can be immediately obtained by using the well-known odd symmetric characteristic property of the trigonometric sine function. Thus, the remaining values are obtained by the odd symmetric relation

the computation cycle requires a total of 32.times.U.times.32 bit times, where U is the number of harmonic coefficient sets that are used to synthesize the data for a complex musical tone. For the illustrative system of FIG. 1, U=2. The computation time interval is equal to a bit time. The sinusoid table 24 may comprise a read only memory storing values sin(.pi./16).theta., for .theta.=1,2, . . . ,64. It is advantageous to implement multiplier 28 so that both the multiplier and the multiplicand are always positive numbers. Therefore, the preferred implementation is to have the sinusoid table only store the positive values for .theta.=1,2, . . . ,32. When 33.ltoreq..theta..ltoreq.64, a "1" signal is sent to phaser 32 to denote that the sinusoid value read at that corresponding bit time has a negative value. If 0.ltoreq..theta..ltoreq.32, a "0" signal is sent. In addition to its task of permitting multiplier 28 to function with only positive input values, phaser 32 also performs the important task of minimizing the maximum value of the master data set. It is known that the ear is insensitive to the relative phase of the individual harmonics, in a musical tone. Therefore, the phase, or algebraic sign, of any of the individual harmonic components can be inverted in Equation 1 without changing the resultant sound generated by the polyphonic tone synthesizer 10 of FIG. 1. A table of 32 values of 1 and 0 are stored in phaser 32. These are addressed by the corresponding value of q for each specific bit time in the computation cycle to create a phase control signal. While there is no unique optimum set of phase coefficients that will minimize the peak amplitude value for all possible complex musical waveshapes, the following set of values have been experimentally verified to produce satisfactory results

Phaser 32 combines the q-addressed stored phase data with the quadrant data received from memory address decoder 23 in an exclusive-or gate to generate a control signal that is sent to complementer 31. In this fashion the positive product from multiplier 28 is either sent unmodified through complementer 31 to adder 33, or the product is effectively inverted in algebraic sign by a signal that causes the input value to be complemented by complementer 31. The term "complement" is used for the conventional binary process of 2's complement.

An alternative to storing the phase values in a table is to use wired digital logic to generate such values for each input value of the harmonic number q.

At the completion of the computation cycle, executive control 16 initiates the start of the data transfer cycle. During the data transfer cycle, the contents of main register 34 are transferred in a carefully controlled manner to note shift registers 35 and 36. While the description of the data transfer cycle is illustrated for two note shift registers, the extension to any multiplicity is apparent.

Each note shift register has its own separate bit position for a synchronizing bit. This bit position is always a "1" for a single word and is "0" for all other words. The synchronizing bit is used by various logic blocks to detect the initial phase state of the end-around note shift registers as described below. More generally the synchronizing may consist of a synchronizing time data word.

When a first key has first been actuated on the instrument keyboard switches 12, a note clock 37 is assigned by note detect and assignor 14. A preferred implementation is to use a VCO (Voltage Controlled Oscillator) for note clocks 37 and 38. For this embodiment of the invention, the note clocks are not locked with master clock 15 and are running asynchronously. Not detect and assignor 14 when it detects the closure of a keyboard switch transfers a control voltage, or detection signal, to each note clock which causes these clocks to operate at a rate of 64 times the fundamental frequency corresponding to the keys actuated on the instrument keyboard.

Note clocks 37 and 38 cause their respective note shift registers 35 and 36 to transfer data end-around at their individual clock rates. When the word containing the synchronizing bit is read from note shift register 35, its presence is detected by synchronizing bit detector 39. When a synchronizing bit is detected, a phase time is initiated and a phase time signal is sent to note select 40 which identifies the particular note shift register and serves to initiate the first subcycle of the data transfer cycle. One the first subcycle has been initiated, it cannot be terminated by the detection of another synchronizing bit by synchronizing bit detector 39; for example from note shift register 36.

At the start of the first subcycle of the data transfer cycle, note select 40 uses the information received via line 41 to cause the output signal on line 43 from clock select 42 to change from master clock 15 to the clock rate generated by note clock 37. The word contents of main register 34 are then transferred sequentially to complement 44. During data transfer from main register 34, adder 33 merely transfers data from one end of the register to the other without modifying the data. The first 32 words read from main register 34 are transferred unmodified by complementer 44 to note select 40. After the first 32 words are read from the master data set, main register 34 is reversed in direction for the second subcycle of the load cycle so that the remaining 32 words are read in the reversed word order 32,31,30, . . . ,1. The second time the contents of the main register are read during the second half of the load cycle, complementer 44 operates to transfer the complement (negative values) of each input data word. Note select 40 sends the data to load select 45. The load select logic blocks 45 and 46 either operate to load their associated note shift registers or to permit them to operate in an end-around mode when the corresponding data transfer subcycle has been completed. An up-down counter is advantageously used to control bi-directional reading of main register 34.

After note register 35 has been loaded with data transferred from the main register at the clock rate determined by note clock 37, the first subcycle of the data transfer cycle is completed. The second subcycle is initiated the next time that a synchronizing bit is detected by synchronizing bit detector 39 from the data being read from note shift register 36. The operation of the second subcycle is analogous to the first subcycle with note clock 38 now used for timing the transfer of data from main register 34.

At the conclusion of the data transfer cycle, executive control 16 may initiate a new computation cycle. While such new computation cycle is underway, data is being read independently from both note shift registers 35 and 36 under control of their individual note clocks 37 and 38. By the described means, the master data set computed and temporarily stored in main register 34, has now been stretched to correspond to a musical waveform at note frequencies corresponding to switches actuated on the keyboard.

The output data from each note shift register 35 and 36 is converted to an analog voltage by means of digital-to-analog converters 47 and 48. Typical musical waveshapes appearing on lines 49 and 50 are shown in FIG. 2. The musical waveshapes are amplified in amplifiers 51 and 52 and the desired attack/release envelope waveshapes are applied by means of the attack/release generators 53 and 54. The two signals from the two amplifiers are combined in the sum 55 and the resultant composite signal is sent to the sound system 11.

Any of the wide variety of known means for implementing attack/release envelope generators can be used for attack/release generators 53 and 54. A suitable means is described in U.S. Pat. No. 3,610,805 entitled Attack and Decay System for a Digital Electronic Organ.

The computation cycle and the data transfer cycle are independent of each other but are programmed to operate sequentially. During a computation cycle, the output musical tones are continuously generated and are not interrupted. Moreover, during the data transfer cycle, the individual tones are not interrupted so that the musical tones do not have any discontinuities if the harmonic coefficients have not been changed. If a control is opened such as either switch 56 or 57, the tone quality will change at the completion of next subsequent computation cycle and data transfer cycle. Switches 56 and 57 are commonly called "stops" or tone switches.

An alternative system for synthesizing the master data set is shown in FIG. 3. A harmonic combination cycle is added before the start of each computation cycle. The harmonic combination cycle is initiated by executive control 16. The cycle is started by initiating word counter 19 and harmonic counter 20 each to a value of one. Adder-accumulator 21 receives a signal on line 65 from executive control 16. This signal remains constant during the entire harmonic combination cycle and causes adder-accumulator 23 to have a constant value of 32. Memory address decoder 23, therefore, will address the value S.sub.16 from sinusoid table 24 at each bit time of the harmonic combination cycle. S.sub.16 will generally be equal to one, or very nearly so depending upon the numerical accuracy of sinusoid table 24.

At the start of the harmonic combination cycle, the entire contents of harmonic register 60 are initialized to a zero value by a control signal generated and sent from executive control 16. During the harmonic combination cycle, phaser 32 receives a constant signal via line 66 from the executive control 16. The signal on line 66 causes the phaser to output the value "0" at each bit time. Thus, at each bit time complementer 31 will not complement any of the numerical values it receives from multiplier 28.

The harmonic combination cycle starts at the first bit time h.sub.1. At time h.sub.1, word counter 19 has the value 1 which causes memory address decoder 25 to address harmonic coefficient memory 26. Since harmonic counter 20 has the value 1 at time h.sub.1, the harmonic coefficient c.sub.1 will be read from harmonic coefficient memory 26 and sent to data select 64 if tone switch 56 is in the closed position. During the harmonic combination cycle, data select 64 allows data received on line 67 to be transferred to multiplier 28 and at the same time inhibits the transfer of data on line 68.

The input data to multiplier 28 at time h.sub.1 is c.sub.1 and S.sub.16. During the harmonic combination cycle gate 62 inhibits any data from main register 34 from reaching adder 33, while gate 61 allows the data read from harmonic register 60 to reach adder 33. Therefore, at the first bit time h.sub.1, the output of adder 33 will be the sum of 0c.sub.1 S.sub.16. Since S.sub.16 is either equal to one, or very nearly so, the sum is very nearly c.sub.1. Load select 63 allows the output from adder 33 to be loaded into a word position in harmonic register 60. Harmonic register 60 is a read-write set of registers which advantageously may comprise an end-around shift register.

For the first 32 bit times of the harmonic combination cycle, word counter 19 and harmonic counter 20 consecutively are incremented and have the values 1,2, . . . ,32. In this fashion, the contents of harmonic coefficient memory 26 are caused to be transferred to harmonic register 60.

The second subcycle of the harmonic combination cycle is initiated at time h.sub.33 corresponding to bit time 33. At time h.sub.33, word counter 19 is reset automatically to the value 1 because it is a counter modulo 32. Thus at time h.sub.33, memory address decoder 25 detects the reset of word counter 19 and accordingly causes harmonic coefficient memory 27 to be addressed during the consecutive 32 bit times of the second subcycle of the harmonic combination cycle.

At time h.sub.33, the harmonic coefficient d.sub.1 will be transferred to multiplier 28 if switch 57 is closed. The two inputs to adder 33 will be c.sub.1 (already transferred to harmonic register 60 during the first subcycle) and d.sub.1. The value c.sub.1 +d.sub.1 will then be transferred to harmonic register 60 through the control of load select 63. This combination process is iterated during the 32 bit times of the second subcycle of the harmonic combination cycle. The cycle concludes at time h.sub.64 with the contents of harmonic register 60 being the sum of the harmonic coefficients contained in harmonic coefficient memories 26 and 27. Either, or both, sets of coefficients may be combined in harmonic register 60 depending upon the state of tone switches 56 and 57.

The modification of the harmonic combination cycle for any plurality of harmonic coefficient memories should be apparent to those skilled in the art. The harmonic combination cycle requires 32g bit times, where g is the number of harmonic coefficient memories.

When the harmonic combination cycle has been completed, executive control 16 starts a computation cycle. In addition to all the initialization signals previously described for the computation cycle, certain other signals are required when a harmonic combination cycle precedes the computation cycle with the system shown in FIG. 3. During the computation cycle, memory address decoder 23 and phaser 32 are commanded to their normal operation as previously described for the computation cycle. Data select 64 is now commanded by executive control 16 to transfer data received on line 68 to multiplier 28. Gate 61 is also commanded to inhibit data that would be sent to adder 33 from harmonic register 60 while gate 62 is commanded to transfer data to adder 23 as read from main register 34. Load select 63 is commanded by executive control 16 to transfer data from adder 33 to main register 34. These controls place the system shown in FIG. 3 into the same configuration for the computation cycle as shown in FIG. 1 and previously described with the exception that the data contained in harmonic register 60 is substituted as the input to multiplier 28 in place of the data read directly from harmonic coefficient memories 26 and 27.

The computation cycle for the system shown in FIG. 3 requires 32 .times. 32 = 1024 bit times and is independent of the plurality of harmonic coefficient memories. The harmonic combination time interval required for a harmonic combination cycle is 32 times the number of stops measured in time intervals of a bit time.

An apparent modification in the use of a harmonic combination cycle in conjunction with a computation cycle is after the first such harmonic combination cycle to omit such cycle before a computation cycle unless a change has been detected in the state of tone switches 56 and 57. The elimination of redundant computation cycles is advantageous when it is desirable to keep the computation cycle time as fast as possible consistent with the timing logic of the remainder of the polyphonic tone synthesizer system.

FIG. 4a illustrates a conventional straight line approximation for the amplitude-frequency response of a low-pass filter having a slope of -12db per octave and a cut-off frequency f.sub.u defined by the -3db point. A sliding formant filter is a filter such that the cut-off frequency moves from f.sub.u to another frequency f.sub.u ' in some prescribed manner. The change in the cut-off frequency may be made variable by means of a manually operated control or it may be varied automatically as a predetermined function of time. Experimentally, suitable time functions have been found to include a cut-off frequency change linear with time between predetermined limits as well as to cause the change to be proportional to the attack/release envelope shape of the generated tones. FIG. 4b illustrates a conventional straight line approximation for a high-pass filter having a slope of 12db per octave and a cut-off frequency f.sub.L defined by the -3db point. A sliding formant filter of the high pass type is one in which the cut-off frequency f.sub.L moves to f.sub.L ' in some prescribed manner. Sliding formant filters can be either of the low-pass type, the high-pass type, or a combination of both.

FIG. 4c illustrates an effective low-pass filter obtained by attenuating the harmonic coefficients. Curve 1 illustrates a cut-off starting at harmonic number 8 while curve 2 illustrates a cut-off starting at harmonic number 16. FIG. 4d illustrates an effective high-pass filter with curve 3 illustrating a cut-off at harmonic number 8 and curve 4 illustrating a cut-off at harmonic number 17.

FIG. 5 shows the insertion of a subsystem into system 10 of FIG. 1 to provide a means for implementing an effective sliding formant filter in the polyphonic tone synthesizer. The input to comparator 72 via line 71 is the current value q of the harmonic number in the computation cycle. A value q.sub.c is an input to comparator 72 via line 74. q.sub.c is the harmonic number that determines the effective cut-off for the effective low-pass filter. Formant clock 70 provides some prescribed timing means for providing a time varying value u as an input to comparator 72. Comparator 72 at each bit time of the computation cycle compares the value of q+u to the value of q.sub.c. If q+u is less than or equal to q.sub.c, comparator 72 transmits the value Q'=1 via line 75 to formant coefficient memory 73. If comparator 72 makes a comparison at some bit time and finds that q+u is greater than the value of q.sub.c, the value Q'= q+u-q.sub.c is transmitted as an address to formant coefficient memory 73. An attenuation factor, or formant coefficient, G is addressed from formant coefficient memory 73 in accordance with the input value of Q'. Formant multiplier 74 multiplies the current value addressed from sinusoid table 24 with the value G addressed from formant coefficient memory 73. The product generated by formant multiplier 74 is transmitted via line 30 to multiplier 28.

The output signal value u from formant clock 70 can be either increasing or decreasing as a function of time. Table II lists suitable values for formant coefficient memory 73. The gain factors G are stored and addressed by the listed values of Q'. The columns labeled db are the equivalent attenuation values in decibels corresponding to the gain factors G. Advantageously formant coefficient memory 73 may comprise a read only memory storing values of Q'.

The T-control signal transmitted via line 76 as an input to comparator 72 determines if the synthetic sliding formant filter is to function in the low-pass or high-pass mode. If T-control is a "1," then the effective sliding formant filter functions as previously described are in the low-pass mode. If T-control is "0," then the effective sliding formant filter functions as described in the following paragraph in the high-pass mode.

When the T-control signal is "0," comparator 72 at each bit time of the computation cycle compares the value of q+u to the value of q.sub.c. If q+u is greater than or equal to the value of q.sub.c, comparator 72 transmits the value Q'=1 via line 75 to formant coefficient memory 73. If comparator 72 makes a comparison at some bit time and finds that q+u is less than the value of q.sub.c, the value Q'=q.sub.c -(q+u) is transmitted to formant coefficient memory 73.

It is an apparent modification to use two comparators so that a combination of effective sliding formant filters can be implemented simultaneously wherein each such comparator is dedicated to a high-pass and to a low-pass mode. A single comparator can also be implemented to simultaneously perform the value comparisons for the high-pass and low-pass modes. Other values of Q' can readily be programmed into formant memory 73 to provide other filter shapes than the simple low-pass and high-pass filter shapes.

Instead of using a table of formant coefficients it is an obvious modification to use circuitry of calculating suitable values in response to the output signal from a comparator. For example, values of G in Table II were computed from the relation

The polyphonic tone synthesizer 10 shown in FIG. 1 was previously described for synthesizing tones having 32 harmonics. This number of harmonics leads to a maximum frequency of 2093 .times. 32 = 66.976Khz when the top musical key C.sub.7 is actuated on the instrument keyboard. The human ear cannot detect the presence of such a high frequency. It is desirable to limit the highest generated overtone frequency to a value which is consistent with the human hearing ability so that certain system simplifications can be incorporated as described below.

Table III lists the maximum overtone frequency corresponding to given harmonics for the keyboard range. The MAX. FREQ. listed in column 4 was calculated using the restriction that no overtone frequency is to exceed 15Khz. Column 3 lists the maximum harmonic number for each note that is consistent with the specified maximum of 15Khz. All notes from C.sub.2 to A.music-sharp.4 remain within the maximum for the full content of 32 harmonics. Above A.music-sharp.4, the harmonic content must be restricted as shown to remain within the maximum frequency. In column 6 is shown the maximum frequencies corresponding to using 21 harmonics in the octave range C.sub.5 to B.sub.5 and using 10 harmonics in the extended octave range C.sub.6 to C.sub.7.

FIG. 6 shows a subsystem combined with system 10 of FIG. 1 which implements a harmonic limiting function as illustrated by the entries in columns 5 and 6 of Table III. The output signal from complementer 31 is transmitted via line 88 to adder 33. Adder 33 in conjunction with main register #1 34 operates in a manner previously described with reference to FIG. 1. For values of the harmonic number q less than 11, gate 85 causes main register #3 86 to load the same data as that being loaded into main register #1 34. However, for values of q greater than 10, gate 85 inhibits the data received on line 83 from adder 33 from reaching main register #3 86. For these values of q, gate 85 causes the contents of main register #3 86 to shift end-around with no change. Gate 84 in conjunction with main register #2 operates analogous to the combination of gate 85 and main register #3. The difference being that gate 84 inhibits data received on line 83 for values of harmonic number q that exceed 21.

The three main registers 34, 89, and 86 are each timed by a common clock signal received via line 43 from clock select 42. The output signals from main registers 34, 85, 86 are transmitted to data select 87. Executive control 16 causes data select 87 to transfer data from a main shift register corresponding to the note assigned to a particular note shift register. Thus, if a note shift register has been assigned a note clock corresponding to a keyboard switch actuated in the range C.sub.2 to B.sub.4, the transfer is made from main register #1 34 to the note shift register. If a note shift register has been assigned a note clock corresponding to a keyboard switch actuated in the range C.sub.5 to B.sub.5, then the transfer is made from main register #2 89 to the note shift register. Similarly, notes in the range C.sub.6 to C.sub.7 cause a data transfer to be made from main shift register #3 86 to the assigned note shift register.

Harmonic limiting in the polyphonic tone synthesizer can readily be extended to any plurality of octave or note range divisions as represented by the plurality of main registers and gates. The plurality of such registers does not effect the number of bit times in the computation cycle which remains at the same value required for a system utilizing only a single main register without harmonic limiting.

FIG. 7 shows an alternative output subsystem for the polyphonic tone synthesizer system 10 as shown in FIG. 1 and previously described. It is an objective of the subsystem shown in FIG. 7 to employ time sharing of common circuit elements to materially reduce the proliferation of repeated similar circuit elements as the plurality of note shift registers is increased. While FIG. 7 illustrates a time shared output subsystem for three note shift registers corresponding to three simultaneously played notes on the keyboard, the extension to any plurality of note generators is apparent. The operation of FIG. 7 is described for a condition following any loading cycle after the initial such cycle. Each note shift register 35, 36, and 93 operates in a conventional end-around mode under control of their respective individual note clocks 37, 38, and 91. These clocks are usually asynchronous with respect to master clock 15. As a data word is shifted to the output of a note shift register it is transferred end-around to its input through its associated load select circuit. Simultaneously, each output data word is transferred to buffer register 94, 95, 96 associated with a note shift register 35, 36, 93. The executive control 16 causes a data word in each of the buffer registers to be transferred sequentially to data select 97. The timing sequence of data transfer from buffer registers 94, 95, 96 to data select 97 is shown in FIG. 7a. The sampling rate for data transfer from any buffer register should be at a frequency f .times. 2 .times. s, where f is the maximum frequency and s is a safety factor to minimize the possibility of aliasing of frequencies. The maximum value shown in Table III using harmonic limiting is 20.930Khz which with a safety factor of 2.sup.1.37/12 = 1.0823 indicates a satisfactory sampling timing rate of 46.03Khz for an individual channel.

The data chosen at any sampling time is converted to an analog signal by means of digital-to-analog converter 98. The resulting voltage is directed by data select 99 to one of the sample and hold 100, 101, 102, there being such a device corresponding to each of the note shift registers. The analog signal is maintained at its present amplitude during the time between which an individual buffer register is again caused to transfer its current contents under command from executive control 16. The output signals from all sample and hold circuits are added together in sum 55 and then sent to sound system 11.

Executive control 16 maintains instantaneous information concerning the status of a note's envelope. Thus executive control 16 commands a word to be read from attack/release memory 103 at each data select time which is appropriate to the instantaneous envelope status of the note assigned that particular data select time. The digital words addressed from attack/release memory are converted into analog voltages by means of digital-to-analog converter 104. These analog voltages are applied to digital-to-analog converter 98 so that they control the maximum conversion voltage that can be generated at the current data select time.

An obvious modification to those skilled in the art is to replace the digital attack/release sybsystem consisting of attack/release memory 103 and digital-to-analog converter 104 by a conventional analog envelope generating circuit suitable for a tone synthesizer which generates amplitude control signals.

FIG. 8 shows a subsystem used in combination with system 10 to provide individual master data sets for a polyphonic tone synthesizer consisting of a plurality of keyboards. Each set of keyboard switches is assigned its own individual tonal sounds, or equivalently each set is assigned its own group of harmonic coefficient memories. It is common terminology to refer to an instrument keyboard and its associated tone generating subsystem as a "division" of the instrument. The subsystem illustrated in FIG. 8 and described below, is for an instrument having an upper, lower and pedal keyboard such as an electronic organ.

The computation cycle for the subsystem shown in FIG. 8 is composed of three major subcycles, each corresponding to the computation of a master data set for each of the three instrument divisions. For explanatory purposes the computing subcycles are called upper, pedal, and lower cycles. During the upper cycle, memory address decoder 25 addresses the contents of upper harmonic coefficient memory 111. If switch 110 is closed, the upper harmonic coefficients are transferred to upper gain multiplier 112. The upper gain multiplier 112 multiplies, or scales, the upper harmonics by a number, usually less than or equal to one. The scale control signal is obtained via line 113. In such fashion the harmonic coefficients magnitudes are adjusted by the player to his individual taste at any time during his performance on the instrument. The output signal from upper gain multiplier 112 is then transmitted as an input signal to multiplier 28. All the logic blocks preceding multiplier 28 perform as described previously with respect to system 10 shown in FIG. 1. Complementer 31 and adder 33 also perform as previously described.

During the upper cycle, upper gate 115 permits a transfer of its input signals while pedal gate 231 and lower gate 117 inhibit their input signals from a transfer of data. Also during the upper cycle, register select gate 114 operates to transfer to adder 33 only data read from upper main register 116. Thus, during the upper cycle, adder 33, upper gate 115, upper main register 116 and register select gate 114 act in combination as an end-around shift register for sequentially adding numbers to the contents of upper main register 116.

The pedal cycle operates in a manner analogous to the upper cycle. During the pedal cycle, pedal harmonic coefficients are read from pedal harmonic coefficient memory 118. The coefficients are modified by pedal gain multiplier 120 from line 125 is switch 119 is closed. Upper gate 115 and lower gate 117 inhibit their input data while pedal gate 231 transfers its input data to pedal main register 121. Register select gate 114 only transfers data from pedal main register while inhibiting data received from the other main registers. Therefore, during the upper cycle the pedal main register is loaded as an end-around combination with adder 33.

The lower cycle operates in a manner analogous to the upper cycle and acts to load lower main register 122.

During the subcycles of the computation cycle, division couplers can be implemented. The division couplers are controlled by switches 128 and 129, called coupler switches. If switch 129 is closed, then the contents of lower main register 122 will be effectively added to the contents of upper main register 116 to accomplish what is called a lower-to-upper division coupler. Thus, keys actuated on the upper division will sound a combination of both the current upper division sound and the current lower division sound. During the lower cycle, closing switch 129 causes upper gate 115 to transfer its input data. Thus, upper main register 116 will be loaded with the identical data loaded into lower main register 122. During the upper cycle, all gates 117, 231, 115 operate in their normal manner. The result is that at the end of the upper cycle, the upper main register contains data which is the sum of that which would be computed from an upper cycle and is added to data word for word with that which was generated during the lower cycle.

Switch 128, when closed, commands a lower-to-pedal division coupler. During the lower cycle, closing switch 128 causes pedal gate 231 to transfer its input data so that pedal main register 121 contains the same data loaded into lower register 122. During pedal cycle, the contents of pedal main register 118 will become the sum of the data in the lower main register and the data normally assigned to pedal main register 118.

While FIG. 8 shows a single main register for each of three instrument divisions, it is an obvious modification to replace each, or any, of these main registers by a multiplicity of registers as shown in FIG. 6 and described previously so that harmonic limiting can be implemented simultaneously with division couplers. It is also an apparent modification that each, or any, of the harmonic coefficient memories shown in FIG. 8 can be replaced by a harmonic register subsystem of the type shown in FIG. 3 and described previously.

FIG. 9 shows some of the details of synchronization bit detector 39 for system 10 shown in FIG. 1, and described previously. Particularly, FIG. 9 shows the manner in which the synchronizing bits from the note shift registers are detected, data converted from asynchronous clocks to common synchronism with master clock 15, and used to control an attack/release memory 103 of the type shown in FIG. 7 and described previously. The operation of the logic blocks shown in FIG. 9 are described for a time following the first load cycle. As described with reference to FIG. 1, the least significant bit of each note register is reserved for a synchronizing bit. Although previously system 10 had been described for note registers having only a single 1 in the least significant bit for the 64 words, an extra 1 bit is now inserted in this bit position for word 33. Thus, a synchronizing bit is circulating for the start of each period of the synthesized tone as well as at each half period. The start bit is used to initiate a loading cycle to maintain waveshape integrity and in conjunction with the half cycle bit is used to furnish timing information for controlling an attack/release envelope generator of the type shown in FIG. 7.

When either a start bit or a half-cycle bit is detected at the time a word is read from note shift register #1 35, this bit is retained in temporary storage by catch 130. An edge detector 131 generates a pulse signal each time that a latch contained within catch 130 is set. The edge detector output signal is sent via line 132 to reset 133. Simultaneously, the same signal is sent to increment an attack/release counter 134. At the initiation of an attack for a note, note detect and assignor 14 (FIG. 1) sends a signal on line 135 to reset attack/release counter 134. When note detect and assignor 14 detects that the corresponding keyboard switch has been released (opened), attack/release counter is again reset so that it counts half-cycles for the release envelope control function. Logic blocks 36, 136, 137, 138, and 139 in FIG. 9 operate in an analogous manner as described for corresponding logic blocks 35, 130, 131, 133, and 134.

FIG. 10 shows the implementation of FIG. 9 at the logic gate level. Note register 35 of FIG. 9 has been replaced for explanatory reasons by an equivalent 64-one bit word synchronize bit register 150. Each start bit and half-cycle bit read from synchronize bit register 150 is sent via line 151 to toggle flip-flop 152. The combination of a bit delay 153, invertor 154, and AND gate 55 function as an edge detector to output a pulse on line 156 each time that flip-flop 152 is reset. Therefore, the pulse on line 156 signals the start of a cycle for the note shift register corresponding to synchronize bit register 150. The signal on line 156 is used by Synch. bit detector 39 shown in FIG. 1. The combination of AND gate 157, NAND gates 158 and 159 with invertor 160 operates as signal latch. The latch is set at any time such that a start bit or half-cycle bit appears on the output of synchronize bit register 150 and a pulse occurs on line 140 from master clock 15. This latch is reset when the output from the synchronize bit register 150 is 0. The combination of bit delay 160, invertor 161, and AND gate 162 functions as an edge detector to generate a pulse each time that a signal appears on line 163 from the latch. The edge detected signal is used to increment attack/release counter 134.

An obvious modification of system 10 shown in FIG. 1, is to replace the sine functions stored in sinusoid table 24 by cosine functions. When such a substitution is made the master data function is generated by the discrete Fourier series ##EQU2## where the parameters have the same range as listed in connection with Equation 1. Since, the cosine trigonometric function has even symmetry with respect to the half-cycle point, complementer 44 of FIG. 1 can be eliminated from system 10.

It is well-known in mathematical art that for a period of a waveshape, such as that used in musical sounds, that generalized harmonic series can be used to represent the waveshape. Such generalized harmonic series include but are not limited to the Fourier series of the types shown in Equation 1 and Equation 5. The generalized harmonic series is written in the form ##EQU3## where .phi..sub.q (n) denotes any of the family of orthogonal functions or orthogonal polynomials. By analogy with conventional Fourier series, the coefficients a.sub.n are called generalized Fourier harmonic coefficients. Frequently Equation 6 is called a discrete generalized Fourier transform. The orthogonal polynomials include Legendre, Gengenbauer, Jacobi, and Hemite polynomials. The orthogonal functions include Walsh, Bessel, and trigonometric. For purposes of language used in claims, the term orthogonal function is used generically to include both orthogonal functions and orthogonal polynomials.

A generic polyphonic tone synthesizer, of which 10 of FIG. 1 is included, can be implemented for any of the orthogonal functions or polynomials by replacing sinusoid table 24 by tables of the values of such orthogonal functions or polynomials. Depending upon the symmetry of the selected functions or polynomials, complementer 31 will be used if an odd symmetry occurs with respect to the mid point or it is eliminated if there is even symmetry. If the selected function or polynomial does not have either even or odd symmetry, complementer 31 is eliminated and main register 34 is expanded to 64 words. For this situation the computation cycle is expanded to intervals of N=1, . . . ,64 in an obvious extension as described with respect to FIG. 1. Moreover, during the load cycle, main register 34 is read in only one direction to transfer its 64 data words.

The Walsh functions have an attractive characteristic for digital systems in that the amplitudes have only 1 or 0 as possible values. The Walsh function, Wal, can be decomposed into a Sal and Cal function. The Sal function is roughly similar to the trigonometric sine function and like its counterpart has an odd symmetry with respect to its midpoint. The Cal function is roughly similar to the trigonometric cosine function and also has an even symmetry with respect to its midpoint. FIG. 11 shows the portion of system 10 of FIG. 1 that has been modified for operation with Sal functions.

Table IV lists the Sal functions Sal.sub.q (N) for values of the "sequency" (analogous to conventional frequency) q from 1 to 16 and values of N from 1 to 32. The entries for N greater than 32 are obtained by using the odd symmetry property

for N in the range of 33 to 64. Table IV is restricted to q less than 17 for brevity, although the operation of the subsystem shown in FIG. 11 is described for q having values from 1 to 32.

Table V lists both the conventional Fourier coefficients (trigonometric functions) and the Sal-Walsh coefficients for a waveshape consisting of a single sinusoid and a waveshape which is a sinusoid having one half the period of the first sinusoid.

In FIG. 11, the operation of logic blocks 16, 19, 20, 22, 23, 25, 33, 34, and 44 are the same as described previously for system 10 shown in FIG. 1. The Walsh SAL Table 180 replaces sinusoid table 24 of FIG. 1 and is addressed in the same fashion during a computation cycle. Memory address decoder 25 causes Walsh coefficients to be read from Walsh coefficient memories 181 and 182 at the appropriate time during a computation function. Instead of multiplier 28, the Walsh function system utilizes a complementer 183. Since, at every bit time the sal function is either a 1 or 0, the required effective multiplication consists of either transferring a Walsh coefficient unchanged if a 1 has been addressed from the Walsh SAL table 180, or by complementing the Walsh coefficient if a 0 has been addressed from this table.

It is apparent that the various subsystems already described in combination with system 10 as shown in FIG. 1 are equally applicable to system 10 wherein the sinusoid table is replaced by a table of generalized harmonic functions such as the Walsh-Sal functions and the harmonic coefficient memories are replaced by generalized harmonic coefficient memories.

FIG. 12 shows the principle system logic blocks for a polyphonic synthesizer containing the basic system 10 in conjunction with formant filters, harmonic register, harmonic limiting and time-shared output data channels. Function Table 201 is a table of generalized harmonic functions.

While a digital mechanization has been described, this is not necessary; all the system functions could be carried out in analog form. The various shift registers being substituted by analog units such as "bucket brigade" charge-coupled devices.

The invention is not limited to the use of asynchronous clocks for the note clocks, it is an apparent modification to use clocks derived synchronously from master clock 15.