Charge Coupled Device Memory System With Burst Mode

This invention relates broadly to computer memory systems and more particularly to such systems organized from circular shift registers which require periodic refreshing.

The advantages obtainable by organizing memory systems comprising loops of charge storage elements, for example, charge coupled devices or MOS devices, are well-known. Basically, high packing densities and rapid access are obtainable. While these advantages appear, several complications arise when one attempts to organize a memory system from charge storage shift register loops.

These complications arise from two competing concerns. First, it is necessary to intermittently refresh the contents of the charge storage elements. Such refresh is accomplished by circulating the shift register contents. Each such shift results in power dissipation in the memory system. Therefore, it is desirable to keep such circulation to a minimum. On the other hand, it is desirable to have immediate access to the data stored in the circular shift registers whenever the associated computer system demands access. A conflict may arise because the computer system may demand access to data stored in shift registers which are currently being circulated for refresh purposes. Thus, there exists a critical problem in synchronizing and coordinating the refresh and access operations in order to provide maximum flexibility, minimum power dissipation and errorfree operation.

It is therefore an object of the invention to provide an improved computer memory system.

It is another object of the invention to provide a computer memory system of circulating charge storage shift registers having means for orderly accessing and refreshing the shift registers while providing a minimum of interference between the refresh and access operations.

It is an additional object of the invention to provide such a computer memory system in which the instantaneous power dissipation is minimal.

It is yet another object of the invention to allow access to such a memory system in either block or random modes.

These and other objects and advantages of the invention, which will later become apparent, are obtained by employing what may be characterized as a burst mode of operation. In the burst mode of operation, sections of an array of charge storage shift registers are successively refreshed by bursts of clock pulses. Therefore, at any one time, only a small number of the registers in a large memory array are being refreshed. Thus, most of the registers are available for access and instantaneous power dissipation is kept at a minimum. When access is desired to a register currently being refreshed, the access is delayed by control means. When a refresh operation is dictated on a register currently being accessed, the access operation itself is allowed to refresh the particular registers involved.

Further control may be provided according to the invention to access either entire blocks of data words or individual words stored in the charge storage shift register sections. Word access is accomplished by counting clock pulses used to circulate the particular memory section storing the word and comparing the count to a word address. Block access is accomplished by delivering a burst of clock pulses to read or write all of the words in a particular memory section.

The particular implementation of the invention and concomitant advantages will become apparent after consultation of the detailed description of the preferred embodiment of the invention, read in conjunction with the drawings of which:

FIG. 1 is a generalized block form of the scheme of the preferred embodiment of the invention.

FIG. 2 is a schematic diagram of the circulating shift register memory array of FIG. 1.

FIG. 3 is a schematic circuit diagram of logic associated with the shift registers of FIG. 2 for refresh and access operations.

FIG. 4 is a schematic diagram of circuitry providing burst mode refresh of the memory bank of the preferred embodiment of the invention.

FIGS. 5A, 5B and 5C are timing diagrams showing the relation of system control signals to system clock signals applied to the shift register memory array of the preferred embodiment of the invention.

FIG. 6 is a logic diagram of the memory section comparator of FIG. 4.

FIG. 7 is a logic diagram of the refresh counter and burst clock of FIG. 4.

FIG. 8 is a schematic and logic diagram more particularly illustrating the read/write circuitry associated with the shift register array of the preferred embodiment of the invention.

FIG. 9 is a schematic diagram of circuitry facilitating random and block access to the shift register memory of the preferred embodiment.

The general scheme of the memory system of the preferred embodiment of the invention is shown in FIG. 1. As there illustrated, the memory system includes a shift register array 21 and associated clock and gating circuitry 20. The clock and gating circuitry 20 is controlled by read/write circuitry 17, and refresh circuitry 19. The refresh circuitry 19 periodically refreshes the shift register contents in the array 21 with bursts of clock pulses derived from a memory clock 15. If an associated computer system requests access (reading or writing of data) by supplying a request to a memory section comparator 13 and a series of address bits to an incoming address register 11, the memory section comparator 13 supplies control signals to the refresh circuitry 19. In turn, the refresh circuitry 19 may inhibit or otherwise control the refresh operation. The incoming address register 11 supplies address signals to the read/write circuitry 17, which, together with read/write, random mode, and block mode signals, control the accessing of data in the shift register array 21 in coordination with the refresh circuitry 19.

The shift register array 21 is shown in more detail in FIG. 2. The storage portion of the array 21 is made up of a rectangular array of L x K circular shift registers 23, each of which contains N bits. Each section or row in this array, for example sections S.sub.1 composed of registers (1, 1); (1, 2). . . (1, K), comprises a data block storage area for storing in parallel N words of K bits each. Each register 23 in any particular section is supplied by the same set of clock and control lines 25, 27, 29. All of the circular shift registers 23 are supplied with an output line leading to the data OUT register 33 and with read and write control signals R, W. In the preferred embodiment, the circular shift registers are of the two phase charge coupled device (CCD) type.

The control line 29 and clock lines 25, 27 emanate from a gating logic unit 37 shown in FIG. 3. A similar unit 37 is associated with each row 1, 2 . . . L of the memory array 21. Two AND gates 45, 41 and an OR gate 49 receive an input from the first output line of a read/write decoder 111 shown in FIG. 9. The two AND gates 41, 45 receive second inputs from the read/write clock control lines F.sub.WR, .phi..sbsb.1 and F.sub.WR, .phi..sbsb.2.

Thus, when the read/write decoder 111 selects section 1, clock signals .phi..sub.1 and .phi..sub.2 are gated through the AND gates 41, 45; a NOR gate 51; and an OR gate 53 to drive the circular shift registers 23 of the first section of the memory array 21. Gate 51 should be a NOR gate to preserve the proper .phi..sub.1 signal level, as shown in FIG. 5. In the preferred embodiment, a high level signal applied to .phi..sub.1 during non-access and non-refresh states corresponds to the potential required for creating the deep depletion well under .phi..sub.1 electrodes of a two phase CCD shift register for charge holding. Additionally, the output signal from the read/write decoder 111 is gated through the OR gate 49 to provide a control signal CE to the shift registers 23 in the first section of the memory array 21.

Similarly, a line from a refresh decoder 72 (FIG. 4) is supplied as an input to each of three AND gates 47, 43, and 39. Two of these AND gates 43, 47 receive second inputs from a refresh clock 74 (FIG. 4) on lines F.sub.R, .sub..phi..sbsb.2 respectively. The other AND gate 39 is supplied with a control signal C as its second input. Thus, if the refresh decoder 72 selects the first section S.sub.1 of registers (1, 1); (1, 2); . . . (1, K), clock signals are gated through the AND gates 43, 47 and the NOR and OR gates 51, 53 to clock the circular shift registers 23 of the first section of the memory array 21. In the event that a control signal C is also supplied to the AND gate 39, the control signal CE is supplied via the OR gate 49 to all of the registers 23 in the first section S.sub.1 of the memory array 21. The particular utility of the above-described circuitry will become more apparent as successive figures and features of the invention are discussed.

The refresh circuitry 19 is shown in more detail in FIG. 4. This circuitry includes a refresh address counter 70, a refresh decoder 72 and a refresh burst clock and drivers unit 74.

In general, the shift register semi-conductor memory array 21 is refreshed periodically by applying a set of burst clock pulses to successive shift registers sections S.sub.1, S.sub.2 . . . S.sub.L. For the memory shown in FIG. 2 there are L shift register sections. The refresh address counter 70 is chosen to be an l bit counter where 2.sup.l equals L. This counter 70 is utilized to produce an l bit address for driving the refresh decoder 72. The standard decoder 72 decodes the l bit address into a single signal supplied on one of its output lines 1 through L to a gating logic unit 37 of FIG. 3. This signal then activates the AND gates 43, 47 as described above to permit clock signals to be supplied to the shift registers 23 of the particular memory section S.sub.1, S.sub.2 . . . S.sub.L selected.

The clock pulses necessary to clock the memory section selected by the refresh decoder 72 are supplied by the refresh burst clock 74. In the preferred embodiment of the invention two clock phases .phi..sub.1 and .phi..sub.2 are employed (See FIG. 5). This method of clocking CCD shift registers is well-known in the art.

Thus, as the refresh address counter 70 is stepped by the memory clock 15 its l bit address is successively incremented. Each time this address changes, a new output line 1 through L of the refresh decoder 72 is enabled, and a burst of N clock cycles is supplied to the refresh clock control lines F.sub.R, .phi..sbsb.1 and F.sub.R, .phi..sbsb.2 (FIG. 3). The result is that the particular memory array section S.sub.1, S.sub.2 . . . S.sub.L represented by the output of the counter 70 is supplied with clock pulses which circulate and thereby refresh the contents of the circular shift registers 23 in the selected section S.sub.1, S.sub.2 . . . S.sub.L. When the counter 70 reaches maximum count, it resets and begins a new count so that the shift register sections S.sub.1, S.sub.2 . . . S.sub.L are continuously circulated in succession.

The memory section comparator 13 serves to coordinate the operation of the refresh circuitry 19 with read/write operations instituted by the read/write circuitry 17. The memory comparator 13 is supplied with the l bit address produced by the refresh address counter 70 each time it steps to a new bit address. Additionally, the memory section comparator 13 is supplied with an incoming request signal I.sub.R indicating that the associated computer system wishes access, and also with an l bit memory section address supplied simultaneously with the incoming request by the incoming address register 76 of FIG. 9.

The l bit memory section comparator 13 compares the l bit incoming section address with the l bit address of the present memory section that is being refreshed. It produces three output control signals denoted C, C and C', depending on the results of the comparison and the status of the incoming request and count change signals I.sub.R and C.sub.R. In the case that a memory section to which access is requested is different from that being presently refreshed the control signal values are C = 0, C = 1 and C'= 0. No conflicts occur, and the memory section comparator 13 does not interfere with either refresh or access operations. However, there are two cases in which the memory section comparator 13 will so interfere.

In the first case, an incoming request may be directed to a shift register section S.sub.1, S.sub.2 . . . S.sub.L that is presently being refreshed. In this case the output C of the comparator 13 becomes equal to one, and the output C becomes equal to zero. In the preferred embodiment of the invention, these signals indicate to the computing system: 1) that block writing is not allowed and 2) that if a data block is read from the memory system the word order in the block will be skewed. If data readout from the memory is skewed, it may be realigned externally in the main memory, if so desired, by the help of a skew address which may be developed as hereafter detailed. By not allowing writing of a block of K words in the middle of a refresh period, one avoids the problem of synchronizing the block after the write operation. Since, in most computing systems, block writing is not a frequent operation and can be postponed until the refresh is finished, it may be more desirable to disallow block writing as is done in the preferred embodiment of the invention.

In the second case, a refresh request may be made to a memory section S.sub.1, S.sub.2 . . . S.sub.L which is being presently accessed. In that case, refresh is not necessary since the memory section will be refreshed by the access. Therefore, the refresh to that particular section is suppressed. This suppression is accomplished by the control line C' from the memory section comparator 13, which in such a case inhibits the refresh clock 74 and the refresh decoder 72. The decoder 72 may be simply inhibited by AND-ing each of its outputs with the inverted value of C'. Whenever the control signal C' equals 1, the control signal C is forced to zero.

A memory section comparator circuit 13 for producing the above signals C, C, C' is shown in more detail in FIG. 6. It includes a multi-bit comparator 81 which receives and compares the memory section address bits a.sub.1, a.sub.2 . . . al with the count bits c.sub.1, c.sub.2 . . . cl outputted by the refresh address counter 70. In case the section address and refresh address counter count are identical, the comparator 81 outputs a positive level to the inputs of two AND gates 85, 87. The second input of the AND gate 85 is supplied by the F output of a flip-flop 83, and the second input of the AND gate 87 is supplied with the F output of the flip-flop 83. The flip-flop output F is set high by an incoming request signal I.sub.R and reset low by the count change signal C.sub.R. The output F maintains the inverse of the value of the output F. The output of the AND gate 85 constitutes the control signal C, which is inverted by an inverter 89 to provide the control signal C. The output of the AND gate 87 is the control signal C'.

Assuming that the section address and refresh counter output do not match, the output of both AND gates 85, 87 is low and hence C = 0, C = 1 and C' = 0. If a new matching address is then presented, along with an incoming request signal I.sub.R, both inputs to the AND gate 85 are high and C = 1 while C = 0. If, on the other hand, the counter output shifts to an address currently being accessed, the output of the comparator 81 changes to a high level and the flip-flop 83 is reset by the count change signal C.sub.R. Hence, the output of the AND gate 87 goes high, and the output of the AND gate 85 goes low. C' is then high, C is low and C is high.

The refresh burst clock 74 and refresh address counter 70 are shown in more detail in FIG. 7. The refresh counter 70 is driven by clock pulses separated by a duration larger than the duration of the N bit burst delivered to circulate the shift registers 23 in any particular memory section S.sub.1, S.sub.2 . . . S.sub.L. Whenever the count of the basic counter 70 changes, the count change control signal C.sub.R is produced. Hence, C.sub.R may be derived from the input to the refresh counter 70 if the refresh counter 70 is a simple ripple counter. The count change control signal C.sub.R is transmitted to the input of a flip-flop 97, whose output F.sub.1 is connected to a first AND gate 99. A second input of the AND gate 99 is supplied with a clock signal from the memory refresh clock 15. When the output F.sub.1 of the flip-flop 97 is set high by the count change signal C.sub.R, the refresh clock is gated through the output of the AND gate 99 and an AND gate 95 to an N-bit counter 101 and a phased clock driver 103. After a burst of N pulses the counter 101 resets the flip-flop 97.

The refresh clock 74 and refresh address counter circuitry then function as follows. As long as the control signal C' is low, the count change signal C.sub.R will set the flip-flop 97 and gate a burst of N clock pulses through the AND gates 99, 95 each time the count of the refresh counter 70 changes. However, if the control signal C' produced by the memory section comparator 13 goes high because the counter 70 indicates a refresh operation is to be performed on a shift register section S.sub.1, S.sub.2 . . . S.sub.L currently being accessed, no clock pulses are gated through the AND gate 95. The phased clock driver 103 simply serves to produce properly phased clock signals (FIG. 5) for driving the CCD shift registers, as well-known in the art. Thus, as long as C' remains low, the memory sections S.sub.1, S.sub.2 . . . S.sub.L are successively refreshed by bursts of clock pulses.

The scheme and apparatus for conducting refresh operations has now been detailed. The control of read/write access operations will now be more fully explained. At this point, it is useful to explore the shift register input-output circuitry in somewhat more detail.

A particular column of shift registers 23 is shown in detail in FIG. 8 to illustrate the logic used for controlling input and output to each register 23. Each column 1, 2 . . . K may be so organized to provide parallel access to each of the N, K-bit words stored in each memory section S.sub.1, S.sub.2 . . . S.sub.L.

Input to a register loop 23 is controlled by an input AND gate 57, which receives an input of the first bit K.sub.1 of a word to be inputted from the data-in register 31. The input AND gate 57 receives additional inputs of the control signal CE and the write control signal W. Data is permitted to circulate by the refresh AND gate 61, which allows recirculation unless a write operation is underway, in which case the input W supplied by an inverter 62 is low.

Data read-out is enabled by an output AND gate 59 when it is supplied with the control signal CE and a read signal R. The output of the output AND gate 59 is subjected to further control by a second output AND gate 67. This AND gate 67 enables single word read-out when a random access is indicated by control signals RA and CB, supplied as later detailed. The signals RA and CB are supplied to an AND gate 63, which outputs to an OR gate 65. A second input of the OR gate 65 is supplied with the inverse RA of the random access signal RA. Thus, when block access is desired, the inverse of the random access signal RA is high, and data outputted from the first output AND gate 59 will be outputted through the second output AND gate 67 into the data out register 33. However, if random access is desired and the random access signal RA is high, a word will only be outputted to the data out register 33 if a signal C.sub.B is received by the AND gate 63. The manner of production of the control signal C.sub.B will become apparent in the subsequent discussion.

To provide the proper control for accessing a particular memory section S.sub.1 . . . S.sub.L, a read/write decoder 111 and an AND gate 121 and OR gate 123 are used (FIG. 9). The read/write decoder 111 is supplied with an l bit memory section address, which it converts into an output signal on one of the output lines 1 . . . L. The operation of the decoder 111 is controlled by the control signal C, as is the read/write burst clock and driver unit 112. Thus, the read/write decoder 111 and the read/write clock circuitry 112 are inhibited when the memory section address presented to the decoder 111 and to the memory section comparator 13 identifies a memory section which is currently being refreshed by the refresh circuitry 19. The read/write clock 112 and decoder 111 may be inhibited by circuitry similar to that already discussed with respect to the refresh decoder and refresh clock circuitry.

As before noted with reference to FIG. 3, the read/write clock 112 drives the clock lines F.sub.WR, .sub..phi..sbsb.1, and F.sub.WR, .phi..sbsb.2. The operation of the gating logic units 37 is such that clock pulses cannot be gated out on the lines 25, 27 to clock a particular memory section S.sub.1 . . . S.sub.L unless a positive signal is received from the read/write decoder 111. When such a signal is received a burst of N clock pulses is delivered to the lines of the shift registers 23 in the particularly selected memory section to completely circulate an entire block of N words. The control signal CE produced by the gating logic unit 37 cooperates in the outputting of a block of selected words by providing a high input signal to the input and output AND gates 57, 59 (FIG. 8) associated with each of the shift registers 23 in a selected shift register section S.sub.1 . . . S.sub.L.

For these input and output gates 57, 59 to allow access to the data words, it is also necessary that they be supplied with read and write signals R, W. In the preferred embodiment of the invention, if block reading is desired, a read signal R is applied directly to the output AND gates 59 of all the sections S.sub.1 . . . S.sub.L of shift registers 23. The particular section from which data is read out is selected by the signal CE. Thus, block reading is done regardless of whether a particular shift register row is being refreshed. Block writing is performed in a somewhat different manner in the preferred embodiment of the invention.

An AND gate 121 and an OR gate 123 cooperate to synchronize the writing of data by controlling production of the write signal W. The AND gate 121 is supplied with the control signal C, which is high whenever the read/write decoder 111 and the read/write clocking circuitry 112 are enabled, i.e., as long as access is not desired to a shift register section S.sub.1 . . . S.sub.L currently being refreshed. During a write-block access operation, the AND gate 121 is further supplied with a write signal W and a block access mode signal BAM as second and third inputs. When the write signal W, the block access mode signal BAM and the control signal C are high, a write signal W is gated via the OR gate 123 to each of the input AND gates 57 associated with the circular shift register 23. Thus, the input AND gates 57, which receive both a control signal CE and a write signal W are enabled to input data. It should be apparent that reading could be similarly synchronized if desired.

If it is desired to access an individual K-bit word stored among a block of N words in a particular memory section S.sub.1 . . . S.sub.L, additional circuitry is employed including a read/write address counter 113 a refresh status counter 115, refresh/read/write address gates 117, a read/write address comparator 119 and a skew address latch 78. If a word is to be accessed, the random access mode signal RA supplied to the read/write address comparator 119 by the associated computer system is high and the block access mode signal BAM supplied to the AND gate 121 is low. Hence, a write signal W cannot be produced by the AND gate 121, but rather can only be produced by an output from an AND gate 125.

Initially, in an individual word access, an l bit memory section address and an n bit word address are supplied to the incoming address register 76. The l bit sectional address is decoded to enable a particular memory section S.sub.1 . . . S.sub.L as described in the preceding paragraphs. The word address is held in the read/write address comparator 119. This word address is compared to the outputs of the refresh/read/write address gates 117. These outputs are supplied by either the read/write address counter 113 or the refresh status counter 115, depending on the value of the control signals C and C.

Assuming C equals 1, the read/write clock circuitry 112 is circulating a particular memory section as dictated by the read/write decoder 111. The read/write address counter 113 counts the clock pulses delivered by the read/write clock 112 and delivers this count to the address gates 117 for comparison with the word address in the comparator 119. When the contents of the read/write address counter 113 equal the word address, the read/write address comparator 119 outputs the match control signal C.sub.B to the AND gate 125 and to the AND gate 63 of FIG. 8.

If it is desired to write a word into the particular word address, a write signal W is also supplied to the AND gate 125. The signal W is gated through to all the shift registers upon occurrence of the match control signal C.sub.B to write a word into the particular word position 1 . . N represented by the n-bit word address.

If it is desired to read the particular word represented by the n bit word address, the AND gates 63, 67, 59 of FIG. 8 are enabled by the signals CB, RA, and R, as previously discussed. Of course, the match control signal CB lasts for only one clock pulse since the next clock pulse changes the count of the read/write address counter 113 and hence the contents of the address gates 117. Thus, only the particular word indicated by the word address bits will be inputted or outputted from the selected memory section S.sub.1, S.sub.2 . . . S.sub.L.

If, on the other hand, the access indicated is to a word in a memory section S.sub.1 . . . S.sub.L currently being refreshed, the control signal C = 0 inhibits the read/write address counter 113, and the control signal C = 1, activates the refresh status counter 115. The content of the address gates 117 is then the count of the refresh status counter 115, which counts the number of clock pulses delivered by the refresh clock 74. Thus, the indicated word may be read out during refresh if it is circulated past the output AND gates 59 such that the output of the counter 115 equals the word address in the read/write comparator 119.

As above indicated, if writing is desired with respect to a memory section S.sub.1 . . . S.sub.L which is currently being refreshed, such access is inhibited by the control signal C inputted to the AND gate 121. However, if skewed reading out of data from a particular memory section S.sub.1, S.sub.2 . . . S.sub.L is requested, it is implemented by use of an n-bit skew address latch 78, which receives an input from the incoming request signal I.sub.R, the control signal C and the output of the refresh status counter 115. When a block access read operation is requested on a memory section under refresh the readout of data will be immediately started. When the control signal C becomes equal to "1" upon such a request, it activates the skew address latch 78. The latch 78 then stores an n bit representation of the number of refresh pulses delivered while data is being read out. When the control signal C goes low, the read/write clock 112 completes the readout. The control signal C may be immediately forced to zero after N refresh clock pulses by supplying the output of the counter 101 of FIG. 7 to the C.sub.R input of the flip-flop 83 of FIG. 6. The information in the skew address latch 78 may be then used to realign the skewed data read out from the particular accessed section S.sub.1, S.sub.2 . . . S.sub.L, for example by rotating the data words with a proper number of clock pulses, the number being derived from the skew latch information. The actual implementation of a skew address latch according to the requirements here disclosed is well within the capability of one of ordinary skill in the art enabled by this disclosure.

If immediate write-in of data is also desired, the input C to the AND gate 121 may be completely eliminated. The proper sequencing of data may then be provided by presenting the memory with a block of data already ordered to compensate for the skew which would occur upon writing.

Thus, in the preferred embodiment of the invention, block writing and reading can be started immediately upon request provided skewed block data is accepted for external realignment. Such a capability is a very important consideration if the memory is to be used as an auxiliary memory. In the case of immediate access, the block access time is very small. If skewed block transfer is not desirable, then the average block access time during a refresh is N/2 x cycle time. In all cases when a particular memory section is not refreshed, the block access time is only a few hundred nanoseconds because the beginning of the block is immediately available. The skewed block transfer provision insures that the memory always gives immediate response to any block transfer request.

The memory organization of the preferred embodiment of the invention may be applied to any dynamic semiconductor shift register components like MOS or charge coupled devices. Different portions of the driving, decoding and clock circuits may be integrated into the memory devices themselves. Similarly, one or more of the shift register loops may be designed into single integrated circuits. Such a chip organization is very attractive from a power dissipation point of view since only one or two shift registers out of the total will be moving at any time. Thus, many modifications and changes in the preferred embodiment of the invention as specifically described may be made without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described.