System for Collecting Data From Meters Placed at Remote Places

The present invention relates to a data collection system for automatically reading electric, water or gas meters in remote places to collect data as to electric, water or gas quantities consumed for a predetermined period.

A prior art system which is related to the present invention will be described with reference to FIG. 1. A central or data collection station has a circuit 1 for controlling relays for selecting counters. For instance, a control signal is transmitted through counter-selection lines C.sub.R1 and C.sub.R2 to energize a coil of a relay R.sub.1 to close a contact R.sub.1b. Thereafter, a counter-reading control circuit 2 is operated to impress a predetermined voltage on a transmission line L.sub.1 so that a current flows through the line L.sub.1, a least-significant-digit contact A.sub.11 of a counter M.sub.1, a counter resister R.sub.1, the relay contact R.sub.1b, a common transmission line L.sub.0 and a detecting resistor R.sub.D. Counter resistors R.sub.0 through R.sub.9 of the counter M.sub.1 have different values so that a value of the current flowing through the above circuit changes depending upon the position of the counter contact A.sub.11 and is detected in terms of a voltage drop across the detecting resistor R.sub.D by a voltage detecting circuit 3. In this case, the least-significant-digit of the counter M.sub.1 is 1. In like manner, the control circuit 2 impresses a predetermined voltage on a transmission line L.sub.2 to read the next least-significant digit or second digit. Since a second-digit contact A.sub.21 is connected to a resistor R.sub.0, the second digit is 0. In like manner, the third digit and the fourth digit or most significant digit may be read out and displayed by a display device 4. In this case, reading of the counter M.sub.1 results 0901.

In the prior art system of the type described, each of a plurality of transmission lines has stray capacitance so that when the control circuit 2 impresses a predetermined voltage on, for instance, the transmission line L.sub.1, the latter is charged to stray capacitance C.sub.1 within a relatively very short time as the transmission line L.sub.1 has a relatively small resistance. After this stray capacitance C.sub.1 has been charged, the common transmission line L.sub.0 is charged through the counter resistor R.sub.1 to a stray capacitance C.sub.0. In general, the counter resistors R.sub.0 through R.sub.9 have high values ranging from 1K ohms to 10K ohms. Because the common transmission line L.sub.0 is charged through one of these high resistance it takes a considerably long time before a voltage drop corresponding to that across the counter resistor R.sub.1 is derived across the detecting resistor R.sub.D. As a result, the control circuit 2 must be operated with a relatively long switching time sufficient to permit the charging of the common transmission line L.sub.0 to C.sub.0 so that high-speed data collection cannot be accomplished.

In view of the above, one of the objects of the present invention is to provide a data collection system which may eliminate the above problem so that the data collection speed may be substantially increased.

Another object of the present invention is to provide a data collection system which includes a very simple circuit which may permit the charging of the common transmission line to its stray capacitance within a very short time so that the reading time may be considerably reduced and erroneous reading may be eliminated.

FIG. 1; 1a; b is a circuit diagram of a prior art data collection system;

FIG. 2; 2a; b is a circuit diagram of a first embodiment of the present invention;

FIG. 3 shows electric waveforms used for the explanation of the mode of operation of the first embodiment;

FIG. 4; 4a; b is a circuit diagram of a second embodiment of the present invention;

FIGS. 5 and 6 show electric wave forms used for the explanation of the mode of operation of the second embodiment; and

FIG. 7; 7a; b is a circuit diagram of a third embodiment of the present invention.

Same reference numerals are used to designate similar parts throughout the figures.

First Embodiment, Figs. 2 and 3

As shown in FIG. 2, in each terminal station a series circuit consisting of a voltage control element such as a zener diode Z.sub.D1 and a resistor R.sub.011 is interconnected between the data transmission line L.sub.1 and the counter contact R.sub.1b. The resistor R.sub.011 has a value sufficiently smaller than those of the counter resistors R.sub.0 through R.sub.9, but it may be eliminated when the transmission line L.sub.1 has a sufficiently high resistance.

Next with further reference to FIG. 3, the mode of operation of the first embodiment will be described. At time t.sub.1 the relay control circuit 1 energizes the relay coil R.sub.1 to close the relay contact R.sub.1b (See FIG. 3-a) as with the prior art system shown in FIG. 1. Next as shown at FIG. 3-b, the control circuit 2 selects the transmission line L.sub.1 and impresses on it a voltage high enough to enable zener diode Z.sub.D1 to conduct. Because this voltage is high and the zener diode Z.sub.D1 exhibits a relatively small resistance, the common data transmission line L.sub.0 may be immediately charged to the stray capacitance C.sub.0. Because the data transmission line L.sub.1 has a relatively very small resistance, the charging time thereof to the stray capacitance C.sub.1 presents no problem at all. Next at t.sub.2 the control circuit 2 impresses on the data transmission line L.sub.1 a detecting voltage which is constant and lower than a zener or breakdown voltage of the zener diode Z.sub. D1 (See FIG. 3-c). Then, because the data transmission lines L.sub.0 and L.sub.1 have been already charged, a voltage drop corresponding to the voltage drop across the counter resistor R.sub.1 immediately appears across the detecting resistor R.sub.D, is detected by the voltage detecting circuit 3 and is displayed by or stored in the display or memory device 4. In like manner, the control circuit 2 sequentially selects and impresses a predetermined voltage on the data transmission lines L.sub.2, L.sub.3 and L.sub.4, so that the second digit, the third digit and the most significant digit may be sequentially read out at a relatively very small interval (See FIGS. 3-d, -e and -f) because the common data transmission line L.sub.0 has been already charged to its stray capacitance C.sub.0 through the zener diode Z.sub.D1. Depending upon the position of the counter contact the stray capacitance must be recharged by the defecting voltage, but a time required for recharging the stray capacitance of the common data transmission line L.sub.0 is negligible because the stray capacitance has been already charged.

After all of the digits of the representation of the counter M.sub.1, the relay control circuit 1 de-energizes the coil R.sub.1 and then energizes a coil R.sub.2 of a relay in the next terminal station at t.sub.6, and the data reading control circuit 2 impresses a relatively high voltage on the data transmission line L.sub.1 (See FIG. 3-h) to charge the common data transmission line L.sub.0 to its stray capacitance C.sub.0. Thereafter, the representation of the counter M.sub.2 is read out by digit in the same manner as described above.

Second Embodiment, FIGS. 4, 5 and 6

In the second embodiment shown in FIG. 4, in each terminal station in addition to the data transmission line L.sub.1, other data transmission lines L.sub.2, L.sub.3 and L.sub.4 are connected through zener diodes Z.sub.D2, Z.sub.D3 and Z.sub.D4, respectively, and resistors R.sub.021, R.sub.031 and R.sub.041, respectively, to the counter contact R.sub.1b, so that a relatively high-level voltage is impressed on each data transmission line prior to the reading of each digit and consequently a reading speed may be considerably increased.

In operation, the relay control circuit 1 energizes the relay coil R.sub.1 of the first terminal station (See FIG. 5-a), and then the data-reading control circuit 2 impresses a gate voltage G.sub.1 to a gate of a transistor Tr.sub.1 of the data transmission line L.sub.1 to enable it to conduct (See FIG. 5-b). Simultaneously, a switch SW.sub.1 is closed to impress a high-level voltage to a circuit consisting of the data transmission line L.sub.1, the zener diode Z.sub.D11, the resistor R.sub.011, the counter contact R.sub.1b and the common data transmission line L.sub.0 so that the data transmission line L.sub.1 and the common data transmission line L.sub.0 are charged to their respective stray capacitance C.sub.1 and C.sub.0. Next a switch SW.sub.2 is closed simultaneous with the opening of the switch SW.sub.1 so that a predetermined low-level voltage is impressed on the transmission line L.sub.1. A voltage across the detecting resistor R.sub.D, which is representative of the voltage across the counter resistor R.sub.1 is derived by a sampling puls SP.sub.1 and stored in a memory 5. Thereafter, the data-reading control circuit 2 closes the gate of the transistor Tr.sub.1 while impressing a gate voltage G.sub.2 to a gate of a transistor Tr.sub.2 to enable it to conduct (See FIG. 5-c). Next the switch SW.sub.1 is closed to impress a high-level voltage on a circuit consisting of the data transmission line L.sub.2, the zener diode Z.sub.D21, the resistor R.sub.021, the counter contact R.sub.1b and the common data transmission line L.sub.0 so that the data transmission line L.sub.2 and the common data transmission line L.sub.0 are charged to their respective stray capacitance C.sub.2 and C.sub.0. Thereafter, the switch SW.sub.1 is opened while the switch SW.sub.2 is closed to impress a low-level voltage on the data transmission line L.sub.2 so that a voltage across the defecting resistor R.sub.D, which is representative of a voltage across the counter resistor R.sub.0 is derived by the sampling puls SP.sub.2 and stored in the memory 5. In like manner, the third digit and the fourth or most significant digit are read out and stored, and the relay control circuit 1 de-energizes the relay coil R.sub.1 while energizing the relay coil R.sub.2 of the next terminal station. In this way, respective terminal stations are sampled sequentially.

Next the reason why high-speed reading is possible in the second embodiment shown in FIG. 4 will be described in detail. Because of the low resistance L.sub.r1, L.sub.r2, L.sub.r3 and L.sub.r4 of the data transmission lines itself, even with a low-level voltage the stray capacitance C.sub.1, C.sub.2, C.sub.3 and C.sub.4 of the data transmission lines may be charged within a relatively short time to their respective stray capacitance but it is clear that when a high-level voltage is impressed as described previously, they may be charged more rapidly. However, this is not the main object of the second embodiment. The main object is to recharge, prior to each reading or sampling of digits, the common data transmission line L.sub.0 having a relatively long time constant which is determined by the stray capacitance C.sub.0 and the value of one of the counter resistors R.sub.0 through R.sub.9 each having a high value.

The mode of operation of the second embodiment will be described in more detail with further reference to FIG. 6. As described previously, when the switch SW.sub.1 is closed, a highlevel voltage V.sub.1 (See FIG. 6-b) is supplied to the stray capacitance C.sub.0 of the common data transmission line L.sub.0 through the transistor Tr.sub.1, the data transmission line L.sub.1, the zener diode Z.sub.D11 and the relay contact R.sub.1b so that the stray capacitance C.sub.0 is charged to V.sub.0 (See FIG. 6-a). Therefore, at this instant the voltage across the detecting resistor R.sub.D is equal to V.sub.0. When the switch SW.sub.1 is opened, the charge stored in the stray capacitance C.sub.0 is rapidly discharged through R.sub.D simultaneously with the opening of the switch SW.sub.1 so that a low-level voltage V.sub.2 (See FIG. 6-c) is supplied through the counter resistor R.sub.1 so that the discharge of the stray capacitance C.sub.0 is prevented and a current having a magnitude dependent upon the value of the counter resistor R.sub.1 flows through the detecting resistor R.sub.D so that a voltage v.sub.1 corresponding to the value of the counter resistor R.sub.1 appears across the detecting resistor R.sub.D. This voltage v.sub.1 is sampled (See FIG. 6-e) by the sampling pulse SP.sub.1 (See FIG. 6-d) and stored in the memory 5. Thus, the first or least significant digit "1" of the data represented by the counter M.sub.1 is stored.

Next the gate of the transistor Tr.sub.1 is closed while the gate of the transistor Tr.sub.2 is opened and the switch SW.sub.1 is closed to supply the high-level voltage V.sub.1 to a circuit consisting of the data transmission line L.sub.2, the zener diode Z.sub.D21 and the common data transmission line L.sub.0 so that the stray capacitance is immediately recharged to V.sub.0 from v.sub.1. Thereafter, the switch SW.sub.1 is opened while the switch SW.sub.2 is closed so that the low-level voltage V.sub.2 is impressed through the counter resistor R.sub.0 to the detecting resistor R.sub.D and consequently a voltage v.sub.2 corresponding to the resistance of the counter resistor R.sub.0 ; that is , the second digit is derived across the detecting resistor R.sub.D. The second digit, which is "0" in this embodiment, is sampled by a sampling pulse SP.sub.2 and stored. In like manner, voltages v.sub.3 and v.sub.4 representing the third and fourth digits, respectively, or the values of the counter resistors R.sub.9 and R.sub.0 may be derived and stored.

When the high-level voltage V.sub.1 were not used, as with the case of the first embodiment shown in FIG. 2, for recharging the common data transmission line L.sub.0 to the stray capacitance C.sub.0 prior to each reading from the second digit, it would take a considerably long time to charge from v.sub.2, which is a relatively low voltage, to the high voltage v.sub.3 when a digit represented by the counter resistor R.sub.9 having a relatively high resistance is to be read out after a digit represented by the counter resistor R.sub.0 having a relatively low resistance. As a result, the reading speed is decreased. In each digit reading, there is a chance that after a digit has been read out through the counter resistor R.sub.0 having the lowest resistance, a digit must be read out through the counter resistor R.sub.9 having the highest resistance. Therefore, the whole read time is further delayed. In this respect, the second embodiment shown in FIG. 4 has a distinct advantage over the first embodiment shown in FIG. 2 in that reading speed is far faster.

Third Embodiment, FIG. 7

The third embodiment shown in FIG. 7 is substantially similar in construction to the second embodiment shown in FIG. 4 except that the transmission lines L.sub.1, L.sub.2, L.sub.3 and L.sub.4 are connected through the zener diodes and resistors to the common data transmission line L.sub.0 at the ends of the data transmission lines instead of being connected through each terminal station. Therefore, the capital cost may be considerably reduced because of the elimination of the zener diodes in each terminal station. Furthermore, the mode of operation is substantially similar to that of the second embodiment so that high-speed reading may be assured.

So far delay in reading due to the stray capacitance of the common data transmission line L.sub.0 has been described, but the counter-selection signal transmission lines C.sub.rl through C.sub.rm have also stray capacitance C.sub.5 through C.sub.m+4 so that delay in reading occurs because of delay in response of counter selection relays R.sub.1 through R.sub.n. To overcome this problem, a zener diode is connected in parallel with each relay coil as shown in FIGS. 2, 4 and 7, and is impressed with a relatively high-level voltage by the relay control circuit 1 so that the counter selection signal transmission line may be immediately charged to its stray capacitance prior to the energization of the relay coil. Thus the response of the relays R.sub.1 through R.sub.n may be considerably improved.