MIS Switching Circuit Capable of Enduring High Voltage

This invention relates to an MIS switching circuit capable of enduring a high voltage, incorporated in a semiconductor integrated circuit.

In general, the gate-drain voltage of an insulated-gate field-effect transistor (hereafter referred to as MISFET or simply FET) at which the drain junction breaks down, is as low as about 20V. The drive voltage for the display elements of an electronic desk computer is as high as 25 - 50V so that the display elements cannot be driven by an ordinary switching circuit using MISFETs.

Therefore, there has been proposed a switching circuit in which a switching FET is connected in series to a protective FET and in which the drain of the protective FET is connected through a load resistor to a voltage source while the source of the switching FET is connected to a common potential source. However, since the load resistor is externally connected to the semiconductor integrated circuit including the switching and the protective FETs, this switching circuit is not preferable from a viewpoint of reliability and reduction of the number of component parts.

The main object of this invention is to provide an MIS switching circuit capable of enduring a high voltage, having a high reliability and a high integration density.

According to this invention, the load for the switching FET is constituted by a plurality of series-connected FETs. The number of the series-connected FETs is preferably comparable, and especially equal, to the sum of the numbers of the switching and the protective FETs.

Other objects and advantages of this invention will be apparent from the following description of embodiments of this invention, taken in conjunction with the attached drawings, in which:

FIG. 1 shows an example of a conventional switching circuit; and

FIGS. 2 to 4 show switching circuits as preferred embodiments of this invention.

First of all, the conventional switching circuit will be briefly described with the aid of FIG. 1.

As seen from FIG. 1, a switching circuit comprises a load resistor R connected to a voltage source V.sub.H and a switching FET M.sub.1 and a protective FET M.sub.2 connected in series with each other and arranged in an integrated circuit configuration. In FIG. 1, the enclosure by broken line indicates the integrated circuit configuration. With this structure, the high voltage V.sub.H is distributed across the series-connected FETs M.sub.1 and M.sub.2 as well as the load resistor R such that an output voltage of about 40V can be derived. However, the switching circuit shown in FIG. 1 is not preferable in view of the improvement in reliability and the requirement that the number of parts should be decreased, since the load resistor must be connected externally to the integrated circuit.

One method to solve this problem is to use an FET as the load. However, if an FET is used as such a load, there arise two other problems as follows. First, a heavy current flows through the FET as a load since a high voltage is applied between the gate and the source of the FET. Accordingly, to restrict the magnitude of current, the channel of the FET must be sufficiently long. Hence, the longer is the channel length, the smaller is the integration density. Secondly, since a high voltage is applied across the FET, there is a need for a means for protecting the FET from the high voltage.

Now, an embodiment of this invention will be described with the aid of FIG. 2. As shown in FIG. 2, series-connected enhancement type FETs M.sub.3 and M.sub.4, each having its gate and drain short-circuited, form a load means. The drain of the FET M.sub.4 is connected to a high voltage source V.sub.H and the source of the FET M.sub.3 is connected to a series circuit of a protective FET M.sub.2, to the gate of which a DC bias voltage V.sub.GG is applied, and a switching FET M.sub.1 driven by an input signal V.sub.in. The DC bias voltage V.sub.GG is provided for an IC into which the switching circuit is incorporated. An output voltage V.sub.out is taken at the junction point of the load means and the protective FET M.sub.2.

With this structure, it is when the switching FET M.sub.1 is rendered conductive by an input signal V.sub.in applied and therefore the drain potential of the protective FET M.sub.2 is at the ground level (i.e., when the ground level is taken at the terminal V.sub.out), that the withstand voltages of the FETs used as the load means play major roles. On such an occasion, the voltage V.sub.H of the source is divided in accordance with the ratio of the impedances of the FETs M.sub.3 and M.sub.4 and the divided voltages are distributed respectively across the FETs M.sub.2 and M.sub.4. Accordingly, if the impedances of the FETs M.sub.3 and M.sub.4 are designed to be nearly equal to each other, the potential V.sub.A at the junction point of the FETs M.sub.3 and M.sub.4 with respect to ground is roughly equal to (1/2)V.sub.H. Since the drive voltage for an ordinary display element is at most 40V. So, if V.sub.H .ltoreq.40V, then V.sub.A .ltoreq.20V. Consequently, the gate-source voltages of the FETs M.sub.3 and M.sub.4 are not higher than 20V so that the load FETs M.sub.3 and M.sub.4 can well endure the source voltage V.sub.H.

Moreover, the load means described above as an embodiment of this invention, consisting of two series-connected enhancement type FETs, consumes less power than the load means formed of a single FET even when a higher source voltage is used. Namely, since, as is clear from the V.sub.GS -I.sub.D characteristic of the MISFET, the drain current increases with an increase in the gate-source voltage and since the gate-source voltage can be decreased according to this embodiment, then the current can be effectively limited without any increase in the channel length. It is, therefore, clear that if the design is made on the basis of a predetermined load current, the total area occupied in IC by the two FETs used in combination as a load means according to this invention is still smaller than that occupied by a single FET serving as a conventional load means. This means that the integration density can be improved by this invention.

This invention is by no means limited to the embodiment described above, but can permit of various modifications within its spirit and scope.

FIG. 3 shows a modification in which the load is constituted by two series-connected depletion type FETs M.sub.3 and M.sub.4, each having its gate and source short-circuited to each other.

FIG. 4 shows another modification in which the load is constituted by an enhancement type FET M.sub.3 with its gate and drain short-circuited to each other and a depletion type FET M.sub.4 with its gate and source short-circuited to each other, these FETs being connected in series. The circuit configuration shown in FIG. 3 or FIG. 4, where the depletion type FET performs a constant-current operation, consumes a smaller power than the circuit shown in FIG. 2, with its load constituted of enhancement type FETs, if the corresponding elements to be compared with each other have the same area. In any case, the important thing is to connect the FETs in such a manner that the high voltage V.sub.H is divided by the load FETs particularly when the output voltage is at the earth level.

In the above embodiments, the load means are those to which a voltage roughly equal to 40V is applied, but it is needless to say that more than two FETs may be used in a circuit for enduring higher voltages. In that case, more than one protective FET must be used so that the total number of the switching FET and the protective FETs may be comparable to, and preferably equal, to the number of the load FETs.

It is also clear that each load FET in the above embodiments may have its gate connected to an independent bias source instead of being short-circuited to its source or drain.

Moreover, the same result will be obtained if this invention is applied to the case where a load means is constituted by the recently developed FETs having higher withstand voltages with their drains formed through a double diffusion process.