Digital Carrier Wave Detect Circuitry

The invention is directed to digital carrier wave detect circuitry for digital receiving systems of the type described and illustrated in U.S. Pat. No. 3,571,712 to George A. Hellworth and Gardner D. Jones issued on Mar. 23, 1971 for "Digital FSK/PSK Detector".

The invention relates to the detection of the presence or absence of a modulated carrier wave, and it particularly pertains to detecting circuits for carrier waves modulated by digitalized binary signals, such as those transmitted in both directions through the use of modems.

Carrier detecting circuit arrangements are known. Most frequently, the known circuit arrangements are relatively simple detectors arranged for swamping out the modulation thereby leaving an electric level indicative of carrier being received. Frequently, the function is limited to one modulation product, for example, mark signal, in an attempt to lessen the effect of noise in the process. Examples of the digital demodulation and carrier detect are given in the following U.S. patents:

The patents to Breikss and to Maniere and Meile are directed to a digital FM discriminator circuitry using counting circuits for demodulating the signal wave for the information transmitted thereby. Clocking pulse trains are counted during intervals prearranged for conveying the information and for deriving control signals for operating this counting and evaluating circuitry. The components described are conventional and useable with carrier detect circuit schemes, but other than the resultant demodulation of the carrier borne signal, no carrier detect function is performed in either arrangement.

The patent to Ahmed and Glazer is directed to frequency dependent circuitry wherein phase lock circuits are tuned to mark signal frequency and mark/space signal frequencies, but other than for tuning there is no time measuring and/or counting function performed.

The patent to Thalimer and Son is directed to a carrier detection circuit and recognizes the noise problem. The circuit described, however, uses analog filter circuits for separating noise and signal and passes the signal with noise intact to a FSK receiver when mark signal overrides noise; no time measuring function is performed.

Accordingly to the invention, the objects indirectly referred to hereinbefore and those that will appear as the specification progresses obtain in electronic logical circuitry operating on the principle that a phase or frequency modulated data signal that has been bandpass filtered and limited will have a preponderance of transitions spaced within certain limits, while many of those produced by noise will be outside these limits.

The receiving circuit comprises an input bandpass amplifying and limiting stage. All of the signal transitions and some noise are delivered by this stage, but much of the noise present on the incoming circuit is eliminated or at least considerably attenuated. The signal transitions are presented to a counting circuit to which clocking pulse transitions of repetition rate relatively greater than the signal transition repetition rate are applied by a plural stage control circuit. Between input transitions, the counter will count to approximately

where

F is the clock frequency,

T is the time between transitions and

N is the number of flip-flop circuits in the control circuit.

Assuming there is phase continuity in switching, data transitions for either FM or PM waveforms will be (ideally) spaced by one of two time periods T.sub.1 and T.sub.2. Allowing a margin for noise and distortion, nearly all transitions of the received signal will be spaced between either

where K.sub.1 and K.sub.2 are constants dependent upon the transmission medium and ideal transition spacing, that is, a relatively quiet channel with low distortion would have K.sub.1 and K.sub.2 as small percentages of T.sub.1 and T.sub.2 respectively while a larger value would be required for a noisy and/or high distortion channel. The clock frequency F is chosen such that 1/F is much less than the minimum transition spacing. The number of clock pulses counted is defined by the formula

where T is the minimum and maximum transition spacings (T.sub.1 .+-. K.sub.1 and T.sub.2 .+-. K.sub.2). If the time between any two transitions falls between these limits, the circuit is arranged to indicate "interval ok" and another counter will be incremented by one count; if not, the second counter will decrement by N counts. Carrier detect will be indicated when second counter has counted to

where n is the number of stages of the second counter.

The second counter will continue to count up to the maximum count (2.sup.n - 1) as additional properly spaced transitions are detected. A number of improperly spaced transitions can then occur without resulting in lowering the electric level indicative of "carrier detect". It is seen that the logic has an integrating effect in that occasional bursts of noise and/or temporary excessive distortion of the data signal will not change the state of "carrier detect". In a like manner, a number of properly spaced transitions may occur when no message is being received without causing the "carrier detect" level to go up.

In order that full advantage of the invention obtain in practice, a preferred embodiment thereof, given by way of example only, is described hereinafter with reference to the accompanying drawing, forming part of the specification, and in which:

FIG. 1 is a functional diagram of carrier detect circuitry according to the invention; and

FIG. 2 is a graphical representation of waveforms useful in an understanding of the carrier detect circuitry according to the invention.

A functional logical diagram of carrier detect circuitry according to the invention is shown in FIG. 1. For ease of understanding, a conventional source of complementary clocking pulse waves is shown as a binary flip-flop circuit 70 for applying complementary waves at terminals 72 and 74. An input signal is applied at input terminals 20,22. The input signal is normally processed in analog circuitry (not shown) in the form of conventional bandpass amplifying circuitry and conventional limiting circuitry connected in cascade. The input terminal 20 is connected directly to an Exclusive OR (XOR) gating circuit 210 and indirectly through a delay element 212 to that same XOR gating circuit. The delay element 212 is arranged to delay the signal sufficiently to allow setting the flip-flop circuit 214 and may be any suitable conventional time delay device. Two or four inverter circuits connected in series form but one of many suitable delay arrangements. The output of the XOR 210 is applied to the set terminals of a flip-flop circuit 214 serving as a latch. The Q output terminal of this latching flip-flop circuit 214 is connected to the succeeding one 216 of a number of concatenated leading edge triggered data-clocked (D-C) flip-flop circuits 216,218,220 and 224 as shown. The actual number of the latter flip-flop circuits is dependent upon the particular modulation scheme employed, the noise encountered and the properties of the signal transmission medium, as those skilled in the art will recognize. Because the operation of the carrier detect circuit will be described for two flip-flop circuits 216,224, the intermediate states are shown in broken lines. The Q output terminal of the final concatenated flip-flop circuit 224 is connected to an AND gating circuit 228 to which another input lead is connected to the complementary clock pulse input terminal 74. The AND gating circuit 228 is connected to reset terminals of a multi-(nine) stage counting circuit 230. The input count terminals of the latter are arranged to accept a number of criteria by means of an AND gating circuit 232. One input lead of the AND gating circuit 232 is connected to the complementary clock pulse train input terminal 74 while another input lead of the AND gating circuit 232 is supplied with an electric level representative of the condition in which all flip-flop circuits 216 . . . 220 are reset. This is achieved where there are more than the one stage 216 by means of another AND gating circuit 234 connected to the P output terminals of all the concantenated flip-flop circuits 216 . . . 220 and the AND gating circuit 232. For but two D-C flip-flop stages, the P terminal of the first flip-flop circuit 216 is connected directly to the AND gating circuit 232. Four AND gating circuits 242,244,246 and 248 have multiple input leads connected to pertinent stages of the counter 230 in conventional fashion for delivering electric levels at the output of these AND gating circuits representative of four different counts. The output of one of these AND gating circuits 244 is applied through an inverting input circuit terminal 250 to the input of the AND gating circuit 232. The connection is made to inhibit further counting after the maximum acceptable count has been reached. The output lead of the AND gating circuit 242 is connected to an OR gating circuit 252. The AND gating circuit 244 is connected to another OR gating circuit 256. Similarly, the AND gating circuit 246 is connected to the first OR gating circuit 252 while the final AND gating circuit 248 is connected to the other OR gating circuit 256. The four AND gating circuits 242,244,246 and 248 are enabled simultaneously by a connection to the direct clock pulse train input terminal 72. The OR gating circuit 256 has an additional lead connected to the output lead of the AND gating circuit 228. A flip-flop circuit 258 serving as a latch has the set terminal connected to the output lead of the OR gating circuit 252, while the reset terminal is connected to the OR gating circuit 256. The Q output terminal of the flip-flop circuit indicates that the time interval between transitions is O.K. when the electric level at the latter is up. The Q output of the flipflop circuit 258 is connected to the input terminal of an AND gating circuit 262 having the output lead connected to the up-count terminal of the counter 260. The counter 260 is conventional and as shown has internal connections to conventional circuitry shown here as a NAND gating circuit 264 for developing a zero output level indicative of counter 260 being in the all ones condition. This condition is transmitted to the input of the AND gating circuit 262. Similarly, the complementary P output terminals of the flip-flop circuit 258 are connected to an AND gating circuit 268 to which a level representative of not all zeros is also presented by way of a NAND gating circuit 270. The output of the NAND gating circuit 268 is connected to the down-count terminal D of the counter 260. For enabling the counter 260, the complementary P output terminal of the flipflop circuit 258 is connected to an AND gating circuit 274 to which the output of NAND gating circuit 235 is also connected. The latter NAND gating circuit 235 is connected to the P output terminal of the flip-flop circuit 224 and the P terminals of the flip-flop circuits 216,218 and 220 through the AND gating circuit 234. The output of the AND gating circuit 274 is connected through an OR gating circuit 276 to another AND gating circuit 278. The clock pulse input terminals 72 are connected through another delay element 280, similar to the delay element 212, to the input terminals of the AND gating circuit 278 for enabling the count of the counter 260. The counter 260 has a reset terminal which is connected to reset pulse input terminals 76. This terminal is deactivated in order for the carrier detect circuitry to operate, and activated only for resetting the counter. After the reset terminal R is raised to reset the counter and 32 input pulses are counted, the output terminals 92,94 connected to the last (6th) stage of the counter 260 go up indicating that 32 properly spaced transitions have been received whereby "carrier" is present.

FIG. 2 is a graphical representation of idealized waveforms resulting in the operation circuitry according to the invention for one example with properly spaced transitions and another example where the transitions are improperly spaced. For this example N=2, thus flip-flop circuits 216 and 224 are interconnected, and flip-flop circuits 218 and 220 and the AND gating circuit 234 are not required. The direct input to the XOR gating circuit 210 is represented by a curve 310. The erect timing wave at the terminal 72 is represented by the following curve 320. The waveform appearing at the Q output terminal of the latching flip-flop circuit 214 is represented by a curve 330 while the following curve 340 represents a wave appearing at the Q output terminal of the following flip-flop circuit 216. The waveform appearing at the Q output terminal of the flip-flop circuit 224 is then represented by a curve 350. The output of the AND gating circuit 228 for resetting the nine-stage counter 230 and the flip-flop circuit 258 is represented by a curve 360. The output at the Q output terminal of the flip-flop circuit 258 is represented for the two cases by the "interval OK" Up and Down level curves 370 and 370' respectively. The output of the AND gating circuit 278 is represented for the two cases by curves 390 and 390' respectively. Curves 380 and 380' represent the waveform at the up U and the down D count terminals respectively for the two cases illustrated.

In operation, conventional input circuitry drive input terminals 20 and 22 in order to filter out all frequencies outside the frequency band of the received data signal for optimum signal-to-noise ratio and for rejection against distortions and echoes. The carrier detect logical circuitry serves to disable the receiver when no data signal is being received. As mentioned hereinbefore, the carrier detect logical circuitry operates on the principle that a phase (or frequency) modulated signal that has been filtered and limited will have a preponderance of transitions spaced within certain limits while many of those produced by noise will be outside these limits. An ideal binary phase modulated data signal using an 1800 Hz carrier and switching at zero will have zero crossings spaced by either 278 or 555 microseconds. Allowing a reasonable margin for the effects of distortion and noise, nearly all the transitions of this input signal can be assumed to be spaced by either 195 to 361 microseconds or 430 to 681 microseconds if a data signal is being received. If either condition is met, the "interval OK" electric level at the Q output terminal of the flip-flop circuit 258 will be up when the up/down counter 260 receives its clock input and the counter will increment by one count. If neither condition is met, the counter 260 will decrement by two counts. About 9 milliseconds after the beginning of the reception of a data signal, the count will reach 32 and the "carrier detect" electric level at terminals 92,94 will go up. Additional properly spaced transitions will result in counting higher (to a maximum count of 63). A number of improperly spaced transitions can then occur without resulting in lowering the "carrier detect" electric level. Thus, it is seen that the logic employed imparts an integrating effect whereby occasional bursts of noise or excessive distortion of the data signal will not change the state of the "carrier detect" level. In a like manner, a number of properly spaced transitions may occur when no message is being received without causing the "carrier detect" to go high.

Referring to FIG. 1, the AND gating circuits 246,248,242 and 244 are connected to the stages of the counter 230 for sensing counts respectively corresponding to T.sub.1min, T.sub.1max, T.sub.2min and T.sub.2max respectively. For the circuit as described hereinbefore counts of 118,220,261 and 418 respectively are sensed. For this count only the two flip-flop stages 216 and 224 are required and they are wired directly together from the Q terminal of the first stage 216 to the D terminal of the stage as described earlier; the intermediate stages 218 and 220 and the AND gating circuit 234 are unnecessary here.

The carrier detect circuit as described hereinbefore has been built and tested as part of a modem used for transmitting and receiving data over telephone lines. The input signal was a 1200 baud phase modulated, 1800 Hz carrier signal which has been filtered and limited. The clock period is 1.63 microseconds for the frequency F of 614.4 KHz; T.sub.1 and T.sub.2 are 277.8, 555.6 microseconds; K.sub.1 and K.sub.2 are 83.3 and 124.9 microseconds respectively, and N was 2 (the latching circuit 214 is not counted for evaluating N) which accounts for only the three waveforms 330,340 and 350 in FIG. 2.

The circuit is particularly well suited for semiconductor fabrication, especially the Large Scale Integration (LSI) implementation.

While the invention has been described and illustrated in terms of a preferred embodiment, and some alternative structure has been offered, it is to be clearly understood that those skilled in the art will make additional changes without departing from the spirit and scope of the invention as defined in the appended claims concluding the specification.