Method and Apparatus for Synchronizing Data and Clock Signals

The present invention relates to a method and apparatus for synchronizing data and clock signals, and it more particularly relates to a method and apparatus for synchronizing data signals from a computer in a data transmission system with clock pulses from a local data set so that the data signals can be transferred synchronously to a remotely located data set.

Data transmission systems have been employed for transferring data from a computer to a local data set or modem eliminator and from there via a transmission line, such as a telephone line, to a remotely located data set. The data can then be utilized at the remote location in different manners, such as displaying the information on an IBM 2260 cathode ray tube display unit via an IBM 2848 control unit or other such line compatible type equipment. Thus, a single centrally located computer can transfer its data to many different remote locations in an efficient and convenient manner. In such a system, the local computer and line controller, for example, might be an IBM 360 computer with an IBM 2701 or an IBM 2702 controller, which are expensive and complex computer equipment for generating isochronous data. Isochronous data is data which is synchronously transmitted asynchronous data, and in this regard, asynchronous data is one having start and stop bits at the beginning and end of the serial data which is at the same time synchronized with clock pulses associated with the data sets. In such a system, the data sets or modem eliminators are synchronously controlled units, and the remotely located data utilizing equipment, such as the IBM 2848 control unit is asynchronous equipment using clocking information supplied by the remote data set or modem eliminator. Therefore, while such a system is satisfactory for some applications, it would be highly desirable to have a less complex computer for some applications and still be able to utilize the data at the remote location in the same manner. In this regard, it would be desirable to have a less sophisticated and less expensive computer such as the Honeywell 716 computer, which supplies asynchronous data, while utilizing the data at a remote location in an inexpensive and yet reliable manner.

Therefore, the principal object of the present invention is to provide a new and improved method and apparatus for synchronizing data signals with a train of clock pulses, such as those produced by a local data set or modem eliminator.

Briefly, the above and further objects of the present invention are realized by providing a method and apparatus for synchronizing data signals with clock pulses, by storing the data signals from a computer in a receiving register, and transferring the data signals from the receiving register to a transmitting register for storage therein. The data signals are transferred from the receiving register to the transmitting register and from the transmitting register to a local data set under the control of logic circuits in response to the clock signals. Other circuits respond to the clock signals for synchronizing the data signals with the clock pulses as the data signals are stored in the receiving register. The data signals are transferred from the transmitting register to the local data set under the control of the logic circuits in synchronism with the clock signals.

Other objects and advantages of this invention will become apparent from the following description when taken in connection with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a data transmission computer system incorporating the principles of the present invention;

FIG. 2 is a schematic functional block diagram of an interface circuit used in the system of FIG. 1 and incorporating the principles of the present invention;

FIG. 3 is a schematic and symbolic block diagram of a phase locked clock circuit of the interface circuit of FIG. 2;

FIG. 4 is a schematic and symbolic block diagram of an error display unit of the interface circuit of FIG. 2;

FIG. 5 is a schematic and symbolic block diagram of the control logic of FIG. 2; and

FIG. 6 is a signal diagram useful in understanding the operation of the control logic of FIG. 5.

Referring now to the drawings, and more particularly to FIG. 1 thereof, there is shown a data transmission computer system 10 including an interface circuit 12 which incorporates the principles of the present invention and which synchronizes data signals from a computer 14 with clock pulses from a local data set 16. The computer or data processor 14 may be a Honeywell 716 mini-computer or similar type of computer which generates asynchronous data. Asynchronous data is data transmitted in serial form with start and stop bits. The local data set 16 is a synchronous type data set using E.I.A. standards RS-232-C mode of operation. The synchronous mode of operation means that separate clock signals are transmitted with the data signals so that the data signals can be synchronized with the clock signals associated therewith. A transmission line, such as the telephone line 18, interconnects the local data set 16 with a remotely located data set 20 for receiving in a synchronous manner the asynchronous serial data generated by the computer 14 and transmitted from the local data set 16 via the interface circuit 12. In order to utilize the data received at the remotely located data set 20, a utilization device, such as a cathode ray tube display unit 22 responds to the data signals received via the data set 20 under the control of a control unit 24. The local data set 16 modulates the data information received from the computer 14 via the interface 12 to send the modulated information over the telephone line 18 to the terminal or remotely-located data set 20 which in turn demodulates the data information and converts it into binary information for the control unit 24. The control unit 24 operates asynchronously to prepare the information for the cathode ray tube display unit 22. The system 10 perferably employs a speed of transmission at the rate of 2400 bits per second, but as hereinafter described in greater detail, higher bit rates may also be accommodated by the system 10. The cathode ray tube display unit 22 may be an IBM 2260 and the control unit 24 may be an IBM 2848, the data sets employing a 201B compatible modem or a suitable modem eliminator. A request for an information display is transmitted via the data sets back to the computer 14 in asynchronous format via a connection (not shown) between the local data set 16 and the computer 14 independent of the interface circuit 12. Thus, in accordance with the present invention, a computer, such as the Honeywell 716 mini-computer, can communicate with a control unit 24 at a remote location by sending asynchronous serial information over the telephone line 18 between the synchronously operated data sets. Thus, a less expensive and less complex computer may be employed in the place of a more expensive computer, such as the IBM 2701 or the IBM 2702 which generate asynchronous serial data in a synchronous manner with the local data set. Such data information may be referred to as isochronous data--both synchronous and asynchronous at the same time. Such isochronous information would be required to be transmitted via the synchronous data sets to the control unit 24, such as the IBM 2848 unit which operates in an asynchronous mode of operation. The interface circuit 12 of the present invention thus serves as an isochronous line adapter to enable the asynchronous data signals from the computer 14 to be synchronized with the clock pulses of the local data set 16.

Considering now the interface circuit 12 with reference to FIG. 2 of the drawings, there is shown the interface circuit 12 which includes a terminal receiver integrated circuit 26 having a shift register 28 for receiving and storing the serial data in asynchronous form from the computer 14 via a receiver gate 31 which has its input connected to the output of the computer 14 via a lead 33 and has its output connected to the pin 3 of the terminal receiver integrated circuit 26. In order to synchronize the data pulses received from the computer 14 with the clock pulses from the local data set 16, a phase locked clock 35 is driven in phase with clock pulses received from the local data set 16 via a lead 37 through a receiver gate 39 to the phase locked clock 35 via a lead 41. The output of the clock 35 is supplied to the pin 1 of the terminal receiver 26 via a lead 43. An internal clock generator 45 of the terminal receiver 26 has its input connected to pin 1 for synchronizing the clock pulses with the data signals for controlling the shift register 28. An asynchronous clock synchronizer 47 of the terminal receiver 26 has its input responsive to the input data signals received from the gate 31 and has its output connected to an input of the internal clock generator 45, whereby the internal clock generator 45 and the asynchronous clock synchronizer serve to synchronize the incoming data signals from the computer 14 with the clock pulses of the local data set 16. As hereinafter described in greater detail, the phase locked clock 35 supplies 64 phase locked clock pulses for each data bit time. The internal clock generator 45 and the asynchronous clock synchronizer 47 cause a single cycle input signal to be gated out of the clock generator 45 at the center of a data bit. This signal from the internal clock generator 45 is the internal clock signal which samples the data and provides the internal timing for the terminal receiver 26. Only the pertinent portion of the terminal receiver 26 is shown and described herein to enable one skilled in the art to understand the principles of the present invention. The terminal receiver integrated circuit 26 may be purchased from Motorola Semiconductor Products, Inc., Box 20912, Phoenix, Ariz. 85036, under the designation terminal receiver MC2259L.

A buffer storage 49 of the terminal receiver 26 receives and stores temporarily the data received in serial form in the shift register 28, the data being transferred from the shift register 28 to the buffer storage 49 in a parallel manner. A similar buffer storage 52 of a terminal transmitter integrated circuit 54 receives and temporarily stores the data signals in a parallel manner from the buffer storage 49. In order to facilitate the transfer of information, as hereinafter described in greater detail, a control logic circuit 55 under the control of the phase locked clock 35 via a lead 57 enables the data to be transferred from the receiver 26 to the transmitter 54 in a controlled manner in response to, among other things as hereinafter described, a signal BUFFER FULL from a status register 56 of the terminal receiver 26. The status register 56 responds to the buffer storage 49 containing the data signals to generate the signal BUFFER FULL, which is supplied to the control logic 55 via a lead 59 to cause in turn the generation of the signal DATA STROBE to enable the data to be transferred to the buffer storage 52. A set of transfer logic gates 58 includes a NAND gate 60 which has one of its inputs responsive to an output lead 61 of the control logic 55 and has its output connected through an inverter gate 62 to pin 21 of the terminal transmitter 54 for generating a signal LOAD STROBE for the buffer storage 52. The signal LOAD STROBE is generated in response to the control logic 55 by the output of the gate 62 to enable the buffer storage 52 to receive the data from the buffer storage 49. An output lead 63 of the control logic 55 is connected to the pin 20 of the receiver terminal 26 to supply a DATA STROBE signal to the buffer storage 49, whereby once the buffer storage 49 is filled, it thereafter transfers its contents to the buffer storage 52 as hereinafter described in greater detail.

A synchronous word counter 64' of the terminal receiver 26 responds to the internal clock generator 45 and controls a transfer timing circuit 66 of the terminal receiver 26 for the purpose of controlling the number of characters being transferred from the shift register 28 to the buffer storage 49. In this regard, 8 bit characters are transferred at a time from the shift register 28 to the buffer storage 49.

A master reset switch 68 normally supplies ground potential to the shift register 28 via pin 27 of the terminal receiver 26, but for the purpose of resetting the shift register 28, the switch 68 can be activated to supply +5 volts DC through resistor 71 to the pin 27 of the receiver terminal 26. Similarly, a lead 73 connects the master reset switch 68 to the display unit 64 so that when the master reset switch 68 is actuated to supply the +5 volt potential, the display unit 64 is reset as hereinafter described in greater detail. A lead 75 in a similar manner connects the master reset switch 68 to pins 9 and 7 of the terminal transmitter 54 to reset a shift register 77 of the terminal transmitter 54.

Considering now the terminal transmitter integrated circuit 54 in greater detail, the pertinent portions of the terminal transmitter will now be described. The terminal transmitter integrated circuit 54 may be purchased from the same manufacturer as the one mentioned above in connection with the terminal receiver. Only the portions of the terminal transmitter integrated circuit 54 will now be described to enable one skilled in the art to understand the principles of the present invention. A lead 79 connects the output of the gate 39 to the pin 8 of the terminal transmitter 54 which in turn is connected to an internal clock generator 80 of the terminal transmitter so that the clock pulses from the local data set 16 are supplied to the terminal transmitter for controlling the transmitting of serial data from the shift register 77 to the local data set 16 in a synchronous manner. It should be understood that the data signals being transferred in a serial manner from the shift register 77 to the local data set 16 is in the form of asynchronous information. A transfer timing circuit 82 of the terminal transmitter 54 is connected to pin 15 which in turn is connected to a system timing logic circuit 84 for generating the signal SYSTEM READY. The system timing logic circuit 84 includes a NAND gate 86 which has one of its inputs energized by a signal BUFFER EMPTY generated by the buffer storage 52 via pin 20 of the terminal transmitter 54. The other input to the gate 86 is connected through a biasing resistor 88 to a +5 volts DC. An inverter gate 89 generates the signal SYSTEM READY and has its input connected to the output of the gate 86.

In order to enable the control logic 55 to control the transfer of data between the terminal receiver 26 and the terminal transmitter 54, a lead 90 supplies the signal SYSTEM READY to the control logic 55. The signal SYSTEM READY comes true when the signal BUFFER EMPTY comes true, indicating that the data previously stored in the buffer storage 52 has been transferred into the shift register 77 and that the terminal transmitter 54 is ready to accept new data from the terminal receiver 26. As hereinafter described in greater detail, when a signal BUFFER FULL becomes true, indicating that the data has been transferred from the shift register 28 to the buffer storage 49 and is ready to be transferred to the terminal transmitter 54, the control logic 55 causes the generation of a signal DATA STROBE, which signal enables the execution of the data transfer operation under the control of the clock signals supplied on lead 57 to the control logic 55.

The output of the terminal transmitter 54 at pin 19 is connected over lead 101 to an input of a driver gate 92 and over resistor 103 to a -12 volts DC potential. The driver gate 92 has its output connected to a lead 94 for supplying the output data signals from the shift register 77 to the local data set 16. A capacitor 96 is connected from the lead 94 to ground. The receiver gate 31, the transmitter clock gate 39, and the driver gate 92 are adapted to the RS-232-C standards.

Considering now the phase locked clock 35, which is shown in FIG. 3 of the drawings, the phase locked clock 35 includes a phase locked loop circuit 105, such as the type SN565, commercially available from National Semiconductor, and a frequency divider circuit 113. The phase locked loop 105 includes a voltage controlled oscillator 107, a phase comparator 115 and an amplifier 117. The input of the phase comparator circuit 115 at pin 2 is connected to the data set 16 over series connected capacitor 119 and resistor 120 and lead 41. A pair of resistors 122 and 124 are connected between inputs of the phase comparator 115 at pins 2 and 3, respectively, and ground.

The output of the phase comparator 115 is connected through amplifier 117 to the voltage controlled oscillator 107 to control its output to keep it in step with the clock pulses of the local data set 16. Control clock pulses provided at pin 8 of the divider 143 are extended to the control logic 55 over lead 57.

The output of the voltage controlled oscillator 107 at pin 4 is fed back to an input of the phase comparator 115 over the frequency divider circuit 113. The frequency divider circuit 113, which is interposed between the output of the voltage controlled oscillator at pin 4 of the device 105 and the input of the phase comparator circuit 115 at pin 5 of the device 105, divides the output of the voltage controlled oscillator 107 and supplies the resulting signal to the input of the phase comparator 115 of the phase locked loop 105. The output of the voltage controlled oscillator 107 at pin 4 of the phase locked loop 105 is connected to one input of a NAND gate 109 and over 4.7K resistor to +5 volts DC. Gate 109 has another input connected through a resistor 111 to +5 volts DC. The output of the gate 109 is connected to the lead 43 extending to the terminal receiver 26 and to an input of the frequency divider circuit 113 at pin 1 thereof.

The divider circuit 113 includes a divider state 143 which divides the signal output of the gate 109 by sixteen and a divider stage 145 which divides the signal output of the divider stage 143 by four. The signal output of the divider stage 145 at pin 5 is connected over lead 147 to an input of the phase comparator 115 at pin 5 of the phase locked loop 105 to supply a signal at the bit rate frequency of the data being transmitted to the phase comparator 115.

The voltage controlled oscillator 107 which operates at a frequency that is 64 times the bit rate of the data being transmitted enables the phase locked clock 35 to operate at 64 times the bit rate and is phase locked to the modem clock of the local data set 16. The phase locked clock 35 operates at 64 times the bit rate of the local data set clock pulse rate so that the terminal receiver 26 can use these phase locked pulses to synchronize with the incoming data signals.

In the exemplary embodiment, the phase locked loop clock 35 operates at either 2400 bits per second or 4800 bits per second, as a function of the setting of a manual switch 126 which selects either one of the two rates by connecting frequency determining components to inputs of the voltage controlled oscillator at pins 8 and 9 of the phase locked loop. In the position as shown in the drawings, a capacitor 128 is connected through the switch 126 to the pin 9 of the phase locked loop 105 and a fixed resistor 130 and a variable resistor 132 are connected in series between +5 volts DC through the switch 126 to the pin 8 of the phase locked loop 105, a capacitor 134 being connected between pin 8 and pin 7 of the phase locked loop 105. In the position as shown in the drawings, the clock 35 operates for a 2400 bits per second mode of operation, and in the other position of the switch 126, the clock 35 operates at 4800 bits per second. In the latter position, a capacitor 136 is connected from ground through the switch 126 to the pin 9, and a fixed resistor 138 is connected in series with a variable resistor 141 connect +5 volts DC through the switch 126 to the pin 8.

Considering now the display panel unit 64 in greater detail with reference to FIG. 4 of the drawings, the error display unit 64 includes three JK flip-flops 151, 153 and 155 which have their K inputs connected to three of the leads respectively designated PARITY, OVER-RUN and BREAK from the status register 56 of the terminal receiver 26 of FIG. 2 so that when any one of these error conditions is generated by the status register 56, they are latched in the flip-flops of the error display unit 64. The Q outputs of the flip-flop 151, 153 and 155 are connected through respective inverter gates 157, 159 and 162 to a series of three light emitting diodes 164, 166, and 168, respectively, which in turn are connected through a series of three resistors 169, 170 and 172 to +5 volts DC. As a result, when the flip-flops 151, 153 or 155 become set, the respective light emitting diodes are energized to provide a visual error indication.

A lead 174 connects the lead 43 from the phase locked clock 35 to the clock inputs of the flip-flops 151, 153 and 155 to serve to clock them when the setting signals occur. The lead 73 from the master reset switch of FIG. 2 is connected to the DC reset inputs for the flip-flops 151, 153 and 155 to reset them. A switch 176 normally connects ground potential to the J inputs to the flip-flops, but when it is switched into its other position +5 volts DC is connected through a resistor 178 to the J inputs of the flip-flops for resetting them at the error display unit 64.

In connection with both the terminal receiver 26 and the terminal transmitter 54, all of the outputs have 6.8K ohms resistors connected to -12 volts DC, and all of their inputs unless otherwise shown or described are left open circuited.

Considering now the control logic 55 in greater detail with reference to FIGS. 5 and 6 of the drawings, the control logic 55 includes a pair of JK flip-flops 191 and 187, a latch circuit 181, comprising NAND gates 183 and 185, and a NAND gate 189. Flip-flop 191 is set in response to the first clock pulse received via the clock lead 57 from the phase locked clock 35 after the signal SYSTEM READY, received via the lead 90, becomes true. The flip-flop 191 is reset by the next clock pulse after the signal SYSTEM READY goes false.

The signal DATA STROBE is supplied via the lead 63 to the pin 20 of the receiver unit 26 for enabling the data stored in the buffer storage 49 to be gated to the outputs of the buffer storage 49 for transfer to the buffer storage 52 of the terminal transmitter 54. Flip-flop 187, when set, causes the signal LOAD STROBE to be generated by the circuit 58 by supplying a signal from the Q output of the flip-flop 187 over lead 61 to an input of gate 60 (FIG. 2). NAND gate 189 is enabled to respond to the signal BUFFER FULL from the status register 56 via the lead 59 to set the latch circuit 181 to cause the generation of the signal DATA STROBE when the signal BUFFER FULL becomes true.

Considering now the operation of the control logic 55 with particular reference to FIG. 6, the clock pulses supplied on the lead 57 are represented in FIG. 6, it being understood that the shape of the clock pulses, as well as the frequency thereof, being well known to those skilled in the art. Also, if desired either trailing edge or leading edge triggering may be employed as is well known in the art. Thus, the signal on lead 57, as illustrated in FIG. 6, is shown for information purposes only to facilitate the understanding of the operation of the present invention, and it is to be understood that other waveforms and triggering may also be employed as is well known in the art.

Assuming that the buffer storage 52 for the terminal transmitter 54 is empty so that signals BUFFER EMPTY and SYSTEM READY are true, that flip-flop 191 is set, and that data has just been received in the shift register 28 via gate 31, such data is then transferred to the buffer storage 49. After the information is received in the buffer storage 49, the signal BUFFER FULL is generated and is supplied via the lead 59 from the status register 56 to the gate 189, to enable gate 189 causing the latch 181 to be set. The setting of the latch 181 causes the generation of the signal DATA STROBE which gates the data to inputs of the buffer storage 52. The access of data in the buffer storage register 49 by means of the signal DATA STROBE resets the buffer status output and signal BUFFER FULL goes false. It is pointed out that the duration of signal BUFFER FULL, while shown by way of illustration, to by approximately one-fourth the width of the clock pulses on line 57, actually represents the delay before an internal latch of the status register is reset by signal DATA STROBE, and the duration of signal BUFFER FULL would typically be on the order of 500 NS.

When the next positive transition of the clock pulse occurs on lead 57, the flip-flop 187 is set by the outputs of latch 181. The setting of the flip-flop 187 causes the gates 60 and 62 to generate the signal LOAD STROBE to enable the buffer storage 52 to receive the information from the buffer storage 49. In this regard, the signals DATA STROBE and LOAD STROBE cause the information to be transferred between the two buffer storage areas. It should be noted that due to the timing of the control logic 55, the data strobe signal is generated before the load strobe signal. It is advantageous to have such a delay, and thus control logic provides a controlled transfer of the data.

When the signal LOAD STROBE becomes true, the buffer empty latch is reset by the signal LOAD STROBE and the signal BUFFER EMPTY becomes false after a delay corresponding to the reset time for the buffer empty latch, so that the signal SYSTEM READY becomes false. In response thereto, the gate 60 is inhibited to terminate the signal LOAD STROBE. The data from the receiver 26 is gated into the transmitter buffer storage 52 at the trailing edge of the signal LOAD STROBE. While, for purposes of illustration, the duration of the signal LOAD STROBE is also shown to be approximately one fourth the width of the clock pulses, a typical value for the duration of such pulse is 750 NS. After the signal SYSTEM READY becomes false, the flip-flop 191 is reset upon the next positive transition of the clock signal on lead 57 causing the latch 181 to reset via an input to gate 185 thereof to terminate the signal DATA STROBE. Also, while flip-flop 191 is reset, the gate 189 is inhibited from responding to the signal BUFFER FULL to again set the latch 181. The flip-flop 187 is reset upon the next positive transition of the clock signal on the lead 57.

When the information is transferred from the buffer storage 52 to the shift register 77, for transmission to the data set 16, the signal BUFFER EMPTY is then generated to cause the signal SYSTEM READY on the lead 90 to become true to permit the flip-flop 191 to be set, thereby removing the inhibit from the gate 189. Thereafter, another data transfer operation may be effected. It should be noted that the signal LOAD STROBE terminates prior to the termination of the signal DATA STROBE to insure the proper sequencing of the operation of the data transfer operation.

The following is a list of components which may be used for the interface circuit 12 of the present invention.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the true spirit and scope of the present invention.