US 4,064,468 AGrant
Low Voltage Compensator for Power Supply in a Complementary MOS Transistor Crystal Oscillator Circuit
Issue Date:1977-12-20
•4 Claims
•2 Drawing Sheets
Abstract
A resistor is connected to the source of a C-MOS inverter included within a crystal oscillator circuit in order to reduce the power dissipation in the crystal oscillator circuit. A switching transistor responsive to the voltage reduction of a power supply source is connected to said resistor in a parallel fashion, thereby shunting the resistor when the power supply level is below a predetermined value.
Metadata
Assignee
- Sharp Kabushiki Kaisha
Inventor
- Kiyoshi Kumata
Application Information
Application Number:US 7180691
Filing Date:1976-08-26
Priority Date:1975-08-29
Art Unit:252
Classifications
IPC:
H03B 536
Field of Search:
33158116 R;18523 R;23 A;23 AC
Patent Drawings (2 sheets)
Description
Background of the Invention
The present invention relates to a complementary MOS transistor crystal oscillator circuit and, more particularly, to a low voltage compensator the power supply in a complementary M0S transistor crystal oscillator circuit.
A C-MOS circuit is conventionally used in an electronic device which requires low power dissipation, especially, in an electronic wristwatch employing a battery of low capacitance.
In an electronic timepiece, a C-MOS crystal oscillator circuit is usually employed, wherein a large part of power in the total power dissipation is consumed, because the C-MOS crystal oscillator circuit operates at very high frequencies in an electronic timepiece. Thereafter, it is required to reduce the power dissipation in the C-MOS crystal oscillator circuit in order to minimize the total power dissipation in the electronic timepiece.
To this end, it has been proposed to connect a resistor to the source of the transistor included within a C-MOS inverter employed in the crystal oscillator circuit, thereby limiting the current flowing through the C-MOS inverter. However, a voltage V.sub.D applied to the C-MOS inverter is unavoidably decreased by a voltage reduction V.sub.S at the resistor. That is, V.sub.D = V.sub.DD - V.sub.S, when a power supply level is V.sub.DD and the V.sub.SS is maintained at ground potential. Therefore, the permissible low voltage for the C-MOS inverter must be selected at a level lower than that of the crystal oscillator circuit by the voltage reduction V.sub.S at the resistor connected to the source of the C-MOS inverter. This results in a requirement that the gain of the C-MOS inverter must be considerably high.
Objects and Summary of the Invention
Accordingly, an object of the present invention is to provide a complementary MOS transistor crystal oscillator circuit with low power characteristics.
Another object of the present invention is to provide a complementary MOS transistor crystal oscillator circuit which can stably operate without regard to the variation of the power supply voltage.
Still another object of the present invention is to provide a low voltage compensator for the power supply in a complementary MOS transistor crystal oscillator circuit employed in an electronic wristwatch.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
To achieve the above objects, pursuant to an embodiment of the present invention, a switching transistor responsive to the voltage reduction of a power supply source is connected, in a parallel fashion, to a resistor connected to the source of a transistor included within a C-MOS inverter employed in a crystal oscillator circuit.
The switching transistor is maintained off when a power source voltage V.sub.DD is above a predetermined value, thereby limiting the current flowing through the C-MOS inverter with the use of the resistor connected to the source of the transistor included within the C-MOS inverter. When a power source voltage v.sub.DD is below the predetermined value, the switching transistor is closed, thereby shunting the resistor connected to the source of the transistor included within the C-MOS inverter. At this moment, the C-MOS inverter is connected directly to receive the power source voltage V.sub.DD.
Brief Description of the Drawings
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein,
FIG. 1 is a circuit diagram of an embodiment of a complementary MOS transistor crystal oscillator circuit of the present invention; and
FIG. 2 is a circuit diagram of another embodiment of a complementary MOS transistor crystal oscillator circuit of the present invention.
Description of the Preferred Embodiments
Referring now to FIG. 1, there is illustrated an embodiment of the present invention, a complementary MOS transistor crystal oscillator circuit of the present invention mainly comprising a crystal oscillation circuit A and a switching circuit B.
The crystal oscillation circuit A comprises a C-MOS inverter 2, a resistor 1 connected to the source of the N-channel transistor included within the C-MOS inverter 2, a quartz crystal vibrator 3 connected between input and output terminals of the C-MOS inverter 2, a feedback circuit connected between the input and output terminals of the C-MOS inverter 2, said feedback circuit including a load capacitor 4 and an input site capacitor 5, and a feedback resistor 6 connected, in a parallel fashion, to the feedback circuit for controlling the switching level of the C-MOS inverter 2.
The switching circuit B comprises a switching transistor 7, a controlling transistor 8, a pull up resistor 9, and resistors 10 and 11 for determining the switching level. The switching transistor 7 is connected to the crystal oscillation circuit A in parallel to the source resistor 1.
When the resistance values of the resistors 10 and 11 are selected at R.sub.1 and R.sub.2, respectively, a gate level V.sub.G of the controlling transistor is calculated as follows in the case where V.sub.SS = 0V.
when the gate level V.sub.G is above the threshold level of the controlling transistor 8, the controlling transistor 8 in ON and, hence, the switching transistor 7 is OFF because the gate level of the transistor 7 is pulled down to 0V. Therefore, the current flowing through the crystal oscillation circuit A is limited by the source resistor 1.
When the gate level V.sub.G of the controlling transistor 8 is below its threshold level due to the reduction of the power supply voltage V.sub.DD, the controlling transistor 8 is OFF and, hence, the gate level of the switching transistor 7 is pulled up toward the power supply voltage V.sub.DD. This places the gate level of the switching transistor 7 above its threshold level and, therefore, the switching transistor 7 becomes ON. At this moment, the power supply voltage V.sub.DD is applied directly to the C-MOS inverter 2, since the ON-resistance of the transistor 7 is considerably lower as compared with the resistance value of the source resistor 1.
It will be clear from the foregoing description that the crystal oscillation circuit A can operate well even when the power supply voltage V.sub.DD is undesirably reduced. Moreover, the C-MOS inverter 2 can be made of transistors of low gain.
In the foregoing embodiment, the resistor 10 is made of a variable resistor in order to facilitate the setting of the switching level. However, the resistors 10 and 11 can be made of fixed resistors. In this case the switching circuit B can be easily incorporated within an LSI circuit.
FIG. 2 shows another embodiment of the present invention, wherein resistors are connected to the sources of the two transistors included within the C-MOS inverter in order to stabilize the operation of the C-MOS inverter. Like elements corresponding to those of FIG. 1 are indicated by the like numerals.
The crystal oscillation circuit A comprises the C-MOS inverter 2, quartz crystal vibrator 3, the feed back loop including the capacitors 4 and 5, and the feedback resistor 6. The crystal oscillation circuit A further comprises the resistor 1 connected to the source of the N-channel transistor included within the C-MOS inverter 2, and another resistor 1' connected to the source of the P-channel transistor included within the C-MOS inverter 2. The resistors 1 and 1' function, in combination, to limit the current flowing through the C-MOS inverter 2 and stabilize the operation point of the C-MOS inverter 2.
The switching circuit B comprises the N-type switching transistor 7 connected to the source of the N-channel transistor of the C-MOS inverter 2 in parallel to the source resistor 1, a P-type switching transistor 7' connected to the source of the P-channel transistor of the C-MOS inverter 2 in parallel to the source resistor 1', a controlling transistor 8, another controlling transistor 8', a pull up resistor 9, a pull down resistor 9', and resistors 10 and 11 for determining the switching level.
When the power supply voltage V.sub.DD is sufficiently high, the gate level of the controlling transistor 8 is above its threshold level and, hence, the transistor 8 is ON. The gate levels of the transistors 7 and 8' are pulled toward the V.sub.SS and, therefore, the transistor 7 is OFF and the transistor 8' is ON. The gate level of the transistor 7' is pulled toward the power supply voltage V.sub.DD and, hence, the transistor 7' is OFF. The source resistors 1 and 1' are inserted in the circuit, since the transistors 7 and 7' are OFF, thereby limiting the current flowing through the C-MOS inverter 2.
Conversely, when the gate level of the controlling transistor 8 is below its threshold level due to the reduction of the power supply voltage V.sub.DD, the controlling transistor 8 is OFF and, hence, the gate levels of the transistors 7 and 8' are pulled toward the power supply voltage V.sub.DD. Therefore, the switching transistor 7 is ON, and the controlling transistor 8' is OFF. The gate level of the switching transistor 7' is pulled toward V.sub.SS because the controlling transistor 8' is OFF and, therefore, the switching transistor 7' becomes ON. Under these conditions, the source resistors 1 and 1' are shunted, whereby the power supply voltage V.sub.DD is applied directly to the C-MOS inverter 2.
In still another form, the switching levels of the controlling transistors 8 and 8' can be selected at different values, thereby controlling the resistance value connected to the C-MOS inverter 2 at two different values.
The abovementioned crystal oscillator circuit of the present invention is effectively applied to an electronic apparatus of which the power supply voltage is unavoidably variable over a considerably large range, such as in an electronic wristwatch having an LED display or an illumination lamp for a liquid crystal display.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.
Claims
What is claimed is:
1. In a complementary MOS transistor crystal oscillator circuit including two power supply terminals, a C-MOS inverter connected across said two power supply terminals, a quartz crystal vibrator connected between an input terminal and an output terminal of said C-MOS inverter, and a source resistor connected between the source of one transistor of the C-MOS inverter and one of said two power supply terminals, the improvement comprising: switching means connected in parallel with the source resistor for shunting said source resistor when said switching means is closed; and control means for closing the switching means when the power supply voltage is below a predetermined value.
2. The crystal oscillator circuit of claim 1, wherein the source resistor is connected between the source of an N-channel transistor of the C-MOS inverter and a grounded power supply terminal, and the switching means is an N-type transistor.
3. In a complementary MOS transistor crystal oscillator circuit including two power supply terminals, a C-MOS inverter connected across said two power supply terminals, a quartz crystal vibrator connected between an input terminal and an output terminal of said C-MOS inverter, a first source resistor having one end connected to the source of the N-channel transistor of the C-MOS inverter and the other end connected to one of said power supply terminals, and a second source resistor having one end connected to the source of the P-channel transistor of the C-MOS inverter and the other end connected to the other power supply terminal, the improvement comprising: a first switching means connected in parallel with said first source resistor for shunting said first source resistor when said switching means is closed; a second switching means connected in parallel with said second source resistor for shunting said second source resistor when said second switching means is closed; and control means for closing said first and second switching means when the power supply voltage is below a predetermined value.
4. The crystal oscillator circuit of claim 3, wherein the first switching means is an N-type transistor, and the second switching means is a P-type transistor.
Patent Citations (2)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3725822 | 1973-04-01 | Eaton, Jr. | |
| US3855549 | 1974-12-01 | Huener et al. |