Process for Block Quantizing an Electrical Signal and Device for Implementing Said Process

Digital systems of data transmission are being used more and more in the transmission of signals because of the various advantages they provide. The analog signal representing the information to be transmitted is sampled and is quantized in amplitude. The continuous scale of the values presented by the signal is replaced by a sequence of discrete values which are normally coded in binary code. Thus, the analog signal to be transmitted is converted to a binary sequence which will not be appreciably affected by the length of the transmission path. Only a binary decision has to be taken by the signal repeaters provided along the transmission path and this makes their design and operation easier. Also, such digital processing of the signals permits a simple and economical application of the time multiplexing principle being used in the telephone networks. Finally, it enables the samples to be stored in a computer bulk memory from which they can be selectively fetched as required.

The major systems using digital signal quantization are based on pulse coded modulation (PCM), delta modulation, or differential pulse coded modulation (DPCM). In these systems, either the sample or the variation of the signal from one sample to the next is coded by rounding the value to be coded to the closest quantization level.

Whatever type of coding is in use, the quantization involves a difference between the coded signal and the original signal. This difference appears as a quantization noise which should be reduced to a minimum to obtain the best representation of the coded signal.

Various systems and methods for reducing this noise are known in the art.

In general, these systems do not provide a simple and economical quantizer able to operate in real time on current information signals, which is the principal object of this invention.

Therefore, it is an object of this invention to code samples at a relatively low bit rate while ensuring a low quantization noise.

Another object of this invention is to reduce the bit rate required for coding samples taken by blocks, with each block defining a section of the signal to be coded.

These and other objects, advantages and features of the present invention will become more readily apparent from the following specification when taken in conjunction with the drawings.

FIG. 1 is a functional diagram of the invention for a 1-bit coding.

FIGS. 2 and 3 are detailed diagrams of the computing device shown on FIG. 1.

FIG. 4 (4A and 4B) are diagrams for explaining the multi-bit coding.

FIG. 5 is a functional diagram of the invention as applied to a differential coder.

In the described system, the signal to be coded appears as successive blocks of samples. For instance, in the case of a voice signal, the samples are delivered at a rate of 8000 per second and are fed to the coder in blocks of 64 units (N=2.sup.6). For an initial description, it will be assumed that each sample is to be quantized with the use of only one bit and that a search is to be made to find the characteristics which are to be assigned to the quantizing device to enable the sequence of bits transmitted after quantization to be as close as possible to the signal section which is defined by the block of N samples. Let Sn (n=1 to N) be the samples of the original signal (direct or differential) to be quantized, Sn is the reconstructed signal, Q is the selected quantization step, Fn is the sequence of relative integers defining the quantization of the block of samples and Cn is the value of a reference polynomial, then,

The initial search is for the values of Cn, Q and Fn which will optimize the quantization within a block, thereby minimizing, with respect to a given criterion, the overall error E between the original signal and the reconstructed signal, namely: ##EQU1## in which the symbol .vertline. .vertline. represents the absolute value of the term in consideration and p can theoretically be any integer value equal to or exceeding unity. In practice, it will be sufficient to determine the mean quadratic error wherein p=2: ##EQU2##

It can be shown that E is a function of parameters Cn and Q and its only minimum is that which is determined by cancelling out the partial derivatives, i.e., by setting ##EQU3## from which ##EQU4## and ##EQU5##

The equation system incorporating

FIG. 1 represents the functional diagram of a device operating to implement the method for optimizing the quantization of signals Sn. The N samples of each block of data to be coded are applied to the input of a delay line 10 of length NT, T being the sample period of the signal to be coded, from an input 11 through a gate 12 and an OR logic circuit 13. The output of delay line 10 is fed back to its input through a second gate 14 also driving an input of OR circuit 13. A control signal G on a lead 15 opens gate 12 when signal G is present and by means of an inverter 16 provided between lead 15 and gate 14, it opens gate 14 for recirculation of data at all other times. This circuit enables the introduction of the N samples of a data block into delay line 10 and then recirculates them as many times as is required by the iterative method. If S.sub.n.sup.o are the non-coded original samples, said samples are, first of all, applied to the input of adder 19 performing a subtraction between the samples S.sub.n.sup.o and a reference signal Cn which is initially taken as equal to zero. Then, the output of adder 19 provides a sequence S.sub.n.sup.l of terms to the input of a quantization device 20 which provides a sequence of terms F.sub.n.sup.l. At the start of operations, the terms of C.sub.n.sup.o can be identified as zero, and the terms of Fn can be equal to the signs of the terms of S.sub.n.sup.l. These two sequences F.sub.n.sup.l and S.sub.n.sup.l are applied to a computing device 21 which determines the values of parameters C.sub.n.sup.l and Q.sup.1 needed for satisfying expressions (1) and (2).

Of course, these parameter values can be determined either by using a particular or microcoded computer or by using a circuit to be described later on.

The new values of Cn and Q, i.e., C.sub.n.sup.1 and Q.sup.1, are entered into delay lines 22 and 23 which provide a delay NT to the transmission of parameters Q.sup.1 and C.sub.n.sup.1.

When sequence S.sub.n.sup.o is applied the second time to adder 19, the adder also receives series C.sub.n.sup.1 and provides S.sub.n.sup.2 = S.sub.n.sup.o - C.sub.n.sup.1. The S.sub.n.sup.2 term is applied to quantizer 20 which is also receiving information Q.sup.1. Device 20 provides an output sequence F.sub.n.sup.2, for instance by detecting the sign of S.sub.n.sup.o - C.sub.n.sup.1. Sequences F.sub.n.sup.2 and S.sub.n.sup.2 are used in comparator 21 to determine Q.sup.2 and C.sub.n.sup.2. This method is carried for a number of iterations to have at the (i+1).sup.st iteration:

and sequences S.sub.n.sup.i+1 and F.sub.n.sup.i+1 provide Q.sup.i+1 and C.sup.i+1 on output lines 25 and 26 respectively.

In general, after a certain number of iterations, Cn varies only slightly and it is then possible to consider that an optimum quantization is obtained. Sequence Fn and the final values of terms Cn and Q define digitally the parameters of the signal block coded with a minimum mean square error.

Actually, it would have been possible to carry out the iterations by using the following relation:

In this case, term Cn to be associated with the final sequence Fn and to Q, would have been obtained by accumulating the Cn's of the successive iterations. Furthermore, the iterations would have led to a null final Cn which, in principle, can be more interesting. In practice, the process is stopped after the execution of a given number of iterations (10, for instance) which number has been found to result in a satisfactory minimum error.

It was indicated above that Cn is a reference polynomial. In general, a polynomial of order 0 (Cn = C where C is a constant) or of the first order (Cn = n .times. C) is sufficient. In the first case, expressions (1) and (2) give: ##EQU6##

In other words: ##EQU7##

The computing device 21, FIG. 1, for multi-digit coded samples can be embodied as schematically shown in FIG. 2. It should be noted that in FIGS. 2 to 5, symbol .times. is used for referencing a series-parallel multiplier, + for referencing a series adder, D for a series-parallel divider and T for a time delay element. The input line 27 receiving S.sub.n.sup.i+1 is connected to the input of a multiplier 30 and to one of the inputs of an adder 31. The input 32 receiving F.sub.n.sup.i+1 is connected to both inputs of a multiplier 33 and to the second input of multiplier 30. Input 32 for signals F.sub.n.sup.i+1 is also linked to the input of an adder 34. The outputs of adders 31 and 34 are fed back to their respective second inputs through time delays 35 and 36 respectively, each delay having a time delay equal to one sample time T, whereby assemblies 31, 35 and 34, 36 each operate as an accumulator. The outputs of multipliers 30 and 33 each has an assembly of an adder 37 and 38 and a time delay 39 or 40 acting as an accumulator connected thereto to provide the terms .SIGMA. Sn .multidot. Fn and .SIGMA. F.sub.n.sup.2. The output of adder 31 is also connected to one input of each of multipliers 44 and 45; the output of adder 37 is fed to adder 47 and a multiplier 48; the output of adder 34 is supplied to multiplier 48, to the two inputs of a multiplier 49 and to the other input of multiplier 44. The output of adder 38 is connected as an input to multiplier 45 and to an adder 50. The output of multiplier 44 is connected subtractively to an input of adder 47 whose output is the numerator input of a divider 52. The output of multiplier 48 is subtractively connected to an input of adder 53 and the output of multiplier 45 is another input of adder 53 whose output is the numerator input of divider 54. The output of multiplier 49 is subtractively connected to adder 50 whose output is connected to the denominator inputs of dividers 54 and 52, the outputs of which provide the terms C.sup.i+1 and Q.sup.i+1, respectively. Adders 31, 32, 34 and 38 and multiplier 49 respectively provide the terms: ##EQU8##

The adders 47, 50, and 53 actually perform subtractions. They provide, respectively, (it is implied here that summing indicia n varies from 1 to N thus by writing .SIGMA. we mean ##EQU9##

Then, one obtains C.sup.i+1 at the output 26 of divider 54 and Q.sup.i+1 at the output 25 of divider 52.

When a quantization of the first order is to be carried out, Cn = n .times. C. The mean square error then becomes: ##EQU10## and the values of C and Q which are to be used to minimize E are: ##EQU11##

These new parameters C and Q can thus be determined as functions of n, Fn and Sn. FIG. 3 shows an embodiment of the computing device 21 of device FIG. 1 for a quantizer of the first order. It is shown as including two additional inputs, one carries an n term and is referenced 60 and the second one (two inputs) has the .SIGMA.n.sup.2 term and is referenced 61. For the first input 60, the n term can be derived from a counter 62, counting from 1 to N at the same rate as the introduction of the samples of each group into the quantizer 20. As to .SIGMA.n.sup.2, it can be obtained by feeding n to the two inputs of a multiplier the output of which is fed into an adder-accumulator of the above-described type. The overall circuit is generally similar to that shown on FIGS. 2 and it is not considered necessary to provide a detailed description of the circuits shown on FIG. 3. The accumulators 63 to 66 respectively supply .SIGMA.Fn.sup.2 ; .SIGMA.n .multidot. Fn; .SIGMA.n .multidot. Sn and .SIGMA. Fn .multidot. Sn. Multipliers 68, 69, 70, 71, 72 and 73 provide the respective terms .SIGMA.n.sup.2 .multidot. .SIGMA.Fn.sup.2 ; .SIGMA.n Sn .multidot. .SIGMA.n.sup.2 ; (.SIGMA.n Fn).sup.2 ; .SIGMA.n Fn .multidot. .SIGMA.n Sn; .SIGMA.n Fn .multidot. .SIGMA.Fn Sn and .SIGMA.n.sup.2 .multidot. .SIGMA.Fn Sn to adder subtractors 74, 75, and 76 which have as outputs the terms

Dividing the outputs of adders 75 and 76 by the output of adder 74 in dividers 77 and 78 provides the signals C.sup.i+1 and Q.sup.i+1 on outputs 26 and 25 respectively.

Up to now, it has been assumed that the quantization step computed for a group, remains the same for all the samples of the group. In another embodiment which is slightly more sophisticated, it is possible to take a quantization step (for instance, a multiple of Q) selected from within a group according to a criterion previously defined and taking into account the previous variations of Fn within the same signal section. This possibility provides the system with an adaptive property which tends to reduce coding noise.

In the above, a one-bit quantizing code was used which means that Fn consists of a sequence of ones and zeros, each bit representing the quantization of a Sn. When the algorithm for determining Fn is defined from the sign of Sn-Cn, Cn forms a decision level and all the samples exceeding the value Cn are encoded one and the samples lower in value than Cn are encoded zero. All one bits are represented by the Cn+Q value after decoding, while all the levels encoded as zero are represented by the Cn-Q value, as indicated on FIG. 4A. Such a one-bit coding can be insufficient for certain applications, mainly in PCM modulation. It will be evident that the quantizer optimizing process, an object of this invention, applies perfectly for a multi-bit coding of the quantizer level. For this showing, an example of a two-bit coding defining four coding levels of Sn will be set out. Assume, as shown on FIG. 4B, that these levels are bounded by the C1, C2 and C3 magnitudes. Thus, three amplitude bands are defined: the first one including levels between the minimum level of the signal to be encoded and C2, the second band between C1 and C3 and the third one between C2 and the maximum level of the signal to be encoded. In order to have an optimum coding, it is necessary that levels C1, C2 and C3 be correctly located for each section of the signal to be quantized. These new terms (C1, C2 and C3) will be level adjusted within each of said bands, in the same manner as the term Cn in the one-bit coding was. It should be noted that this description relates to a zero order quantization for a better understanding of the invention, but the process applies also to a different order of quantization (for instance, first or higher order). At the beginning, the N sample set is 1-bit quantized and this coding is optimized by applying the above indicated process. This provides the value of optimum decision level C2. Level C2--Q is chosen for the level C1 and level C2+Q for level C3. The above indicated bands bearing references 1, 2 and 3 on the figure are therefore defined. Samples Sn are split into three groups Sn 11, Sn 21 and Sn 31 according to the amplitude band to which they belong with some samples being in two groups. The three groups are separately processed: each group is one-bit quantized to provide Fn 11, Fn 21 and Fn 31. The iteration process is applied on sequences (Sn 11, Fn 11), (Sn 21, Fn 21) and (Sn 31, Fn 31) taken separately and generates optimum values for C11, C21 and C31. These new values replace the previous values of C1, C2 and C3, and thus define three new bands. Then, the original samples are split as before into three new groups Sn 12, Sn 22 and Sn 32 and the one-bit iterative process is again applied on each band, which provides new values of C, etc., until the relations C1 + Q1 = C2 - Q2 and C2 and C2 + Q2 = C3 - Q3 are approximately satisfied. Finally, the samples can be conventionally two-bit encoded according to their position with respect to optimum decision levels C1, C2 and C3. For instance, the samples lower than C1 are coded by the binary value 00, the ones included between C1 and C2 are coded 01, the ones included between C2 and C3 are coded 10, and those exceeding C3, are coded as 11.

Up to this point, nothing has been specified about the definition samples Sn. In the case of a PCM coding, the Sn's are the actual values of the samples Xn of the signal to be quantized. But also, they can be differences between samples as in a DPCM system.

In DPCM modulation, only the signal increments or decrements are encoded. Since the quantizing noise appears on each increment, the overall error introduced in a sample of order m (in which N .gtoreq. m .gtoreq. 1) thus includes the accumulation of the quantization errors of the m previous samples. If the encoded value (encoded as 1 bit or more) of the sample of order m of any block bears reference f.sub.m, the quantization error to be minimized is: ##EQU12## and by assuming that: ##EQU13## one retrieves the same expressions as above, which shows that the optimizing process of the quantizer of this invention also applies to the DPCM modulation. However, expression (3) should also be considered which requires use of a system of the type shown in FIG. 5. In accordance with the previous notations, the increment to be quantized bears reference Sn. If Xn is the sample of order n of the signal to be encoded and X.sub.n-1 is the preceding reconstructed sample, then

Therefore, the device can include a front recycling section similar to the input shown on FIG. 1 and comprising elements 10 to 16. The Xn output of delay 10 is fed to a subtractor 80 performing the subtraction of expression (4). A decoding device 81 reconstructs samples Xn from terms Fn, Cn and Q on inputs 82, 83, and 84 respectively. Also, the DPCM sequence to be transmitted should be derived from Fn, which is the reason for the circuit bearing reference 85 and including an element 86 introducing a time delay T and a subtractor 87 whereby F.sub.n.sup.i+1 =F.sub.n.sup.i - F.sub.n.sup.i+1. The decoding circuit 81 reconstructs signal X.sub.n which satisfies the expression:

The circuit 81 will add in adder 89 a term Q.multidot.Fn which will be provided by a multiplier 90 included in decoder 81 and fed the terms of Q and Fn over leads 82 and 84 to the terms of Cn on input 83, in order to obtain X.sub.n.

A delay element 92 connected to the output of decoder 81 provides a time delay of one sample period to convert the X.sub.n output to the X.sub.n-1 input required by expression (4). The remainder of the structure of FIG. 5 corresponds to the similarly referenced structure of FIG. 1 except for the output 84 of delay line 23 which is returned to quantizer 20 through decoder 81 and adders 80 and 19 rather than directly as in FIG. 1.

The quantizer 20 can of course be of any order and more specifically as above described can be of order zero or of the first order. For the zero order, Cn is chosen constant for a block of N samples. For the first order quantizer, Cn varies linearly with n (Cn = n.multidot.C). It is obvious that Cn can be chosen at an even higher order by taking more terms of the polynomial expression for Cn, i.e.,

however, the computation of C.sub.0, C.sub.1, C.sub.2, . . . , for such higher order polynomials would use complex matrix inversion methods not justified in practice by the additional improvement provided.

However, for both such DPCM cases, the above described iterative process enables optimization of the quantization process. Since the parameters Cn and Q keep varying, X.sub.n is adjusted on each iteration, which ensures a minimization of the coding errors due to the cumulated quantization noise.

While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes of form and detail may be made therein without departing from the spirit and scope of the invention.