Phase Locked Loop Synthesizer

1. FIELD OF THE INVENTION

This invention relates to a phase locked loop (hereinafter referred to as PLL) synthesizer.

2. DESCRIPTION OF THE PRIOR ART

FIG. 1 is a block diagram showing the construction of a PLL synthesizer as most commonly used.

In FIG. 1, 1 denotes a reference signal oscillator which employs usually a crystal vibrator and supplys a stable reference frequency f.sub.0. 2 denotes a phase detector which compares the phases of the signal with a frequency f.sub.0 from the signal oscillator 1 and an output with a frequency (f.sub.1 -f.sub.2)/N from a below-mentioned programmable counter and detects the phase difference. A d.c. voltage is generated corresponding to this phase difference. 3 denotes an integrator which integrates and smooths the output voltage of the phase detector 2. A continuous voltage component proportional to the phase difference is picked up and fed to the input terminal of a voltage controlled oscillator 4 of the next stage. The oscillation frequency f.sub.1 of the voltage controlled oscillator 4 is controlled to higher and lower values in proportion to an increase and a decrease of the controlled d.c. voltage applied to its input terminal respectively. 6 is a local oscillator. 7 is a mixer which mixes the output frequency f.sub.1 of the voltage controlled oscillator 4 and the output frequency f.sub.2 of the local oscillator 6 to obtain the frequencies f.sub., f.sub.1 + f.sub.2 and f.sub.1 - f.sub.2. In the prior art construction of this kind, a low pass filter 8 is employed in order to pass only the difference frequency f.sub.1 - f.sub.2 of the mixer signals 7 to the input terminal 51 - 20 of the programmable counter 51, which is operated with the input with the frequency f.sub.1 - f.sub.2. 5 denotes a programmable counter means consisting of a programmable counter 51 and a means for setting the frequency division ratio N. By switching the switch group 521-1, 521-2 . . . 521-n (n is an integer with n .gtoreq. 2) and supplying "0" or "1" digital input data to the input terminals 51-1, 51-2, 51-3, 51-4, . . . 51-n respectively, the counter means 5 can set the frequency division ratio to an arbitrary integer value within a certain range. If we assume that the figures of the input data terminals 51-1, 51-2, 51-3, 51-4, . . . 51-n increase in this order, the frequency division ratio N increases or decreases by 1 by switching the input data to the terminal 51-1 from "0" to "1" or from 1 to 0 respectively. The ratio N increases or decreases by 2 if the input data to the terminal 51-2 is changed from 0 to 1 or from 1 to 0 respectively. The ratio N increases or decreases by 4 if the input data to the terminal 51-3 is switched from 0 to 1 or from 1 to 0 respectively. It is so weighted that the ratio N increases or decreases by 2.sup.n-1 if the input data to the terminal 51-n is switched from 0 to 1. The output of the counter 51 having a frequency of (f.sub.1 - f.sub.2)/N is supplied to the phase detector. The system so operates as to cancel the phase difference and determine the output of the voltage controlled oscillator. Since the art is well known, detailed explanation of it will be omitted. For example, USP at. no. 3,845,394 may be referred to.

The prior art PLL synthesizer as shown in FIG. 1 has a defect that the difference frequency of the mixer 7 or the operating frequency of the programmable counter 51 can not be pulled up to the maximum operating frequency. In another word, it is difficult that the counter 51 operates at its maximum frequency. The reason is as follows. Although the programmable counter 51 is designed to be operable with an input having a maximum frequency of about 15 MHz, when such an input comes into the counter 51 by way of a conventional low pass filter 8, it is by-passed to the earth through stray capacitance. The amount of signal by-passed increases with frequency and causes a large attenuation of the input to the counter 51. No amplitude large enough to operate the counter 51 (at least IV) can be obtained. Hence, generally the maximum operating frequency of the counter is set at 10MHz for the TTL (transistor transistor logic). In a usual circuit construction, the operating frequency below which an amplitude enough to operate the counter 51 is obtained is set at 7 or 8 MHz.

Therefore, when the output frequency of the voltage controlled oscillator 4 increases, and hence the difference frequency f.sub.1 - f.sub.2 of the output of the mixer 7 or the operation frequency of the counter 51 increases above e.g. 10 MHz, the counter 51 stops its operation. In such a case, a complicated countermeasure should be necessary, i.e., either the oscillation frequency of the local oscillator 6 should be switched down so that the mixed difference between the frequencies of the voltage controlled oscillator 4 and the local oscillator 6 becomes less than 10 MHz, i.e., to about 7 or 8 MHz, or a frequency multiplier should be provided after the voltage controlled oscillator 4 so that the mixed difference frequency of the mixer 7 is so controlled as described above.

An object of the present invention is to provide a PLL synthesizer capable of pulling up the difference frequency of the mixer or the programmable counter to the maximum operation frequency.

Another object of this invention is to provide a PLL synthesizer capable of giving a stable and sufficiently large amplitude to the difference frequency or the operation frequency of the programmable counter.

A further object of this invention is to provide a PLL synthesizer relatively favorable in view of cost.

In order to attain the above-mentioned objects, this invention comprises a tuning means which tunes to the difference frequency of the mixer and leads the frequency to the programmable counter means; and a control means which detects a part of the frequency division ratio setting digital input data of the programmable counter means and controls the tuning frequency of the above tuning means in accordance with the detected signal; wherein only the output signal with a prescribed frequency of the mixer is selectively picked up and fed to the programmable counter.

According to this invention, since the tuning to the prescribed frequency is done at the output stage of the mixer and the tuned frequency is supplied without loss to the programmable counter, the operation frequency of the counter can be pulled up to the maximum operation frequency (15 MHz) of the counter. In another word, the counter is operable even if the difference frequency f.sub.1 - f.sub.2 of the mixer is 15 MHz. Furthermore, the programmable counter can obtain a stable and sufficiently large amplitude input at its operation frequency.

The convenience of this invention is that the control of the tuning frequency at the tuning means is automatically done.

Still another favor of this invention from a point of cost is that the circuit construction is simple.

FIG. 1 is a block diagram showing a prior art PLL synthesizer.

FIG. 2 is a block diagram of the connection of a PLL synthesizer according to one embodiment of this invention.

FIG. 3 is a characteristic curve for the explanation of the embodiment of FIG. 2.

FIG. 4 is a block diagram showing a PLL synthesizer according to another embodiment of this invention.

FIG. 5 is a block diagram showing an example of the application of FIG. 4.

Explanation of the embodiments of this invention will be made hereinafter in conjunction with the drawings. FIG. 2 is a block diagram of a PLL synthesizer according to one embodiment of this invention. In FIG. 2, like reference numerals are used to denote like parts as used in FIG. 1. 100 denotes a frequency mixing and extracting means comprising a mixer 110 of a transistor 111 which mixes the outputs from the voltage controlled oscillator 4 and the local oscillator 6, a tuner which tunes to the difference frequency f.sub.1 - f.sub.2 of the output frequencies of the mixer 110, and an amplifier 130 of transistor 131 which amplifies the output having the tuned frequency and leads it to the programmable counter 51. The base of the mixing transistor 111 of the mixer 110 is connected to the output stage of the voltage controlled oscillator 4 through a coupling capacitor 101 and also connected to the output stage of the local oscillator 6 through a coupling capacitor 102. The base of the transistor 111 is further connected to a power supply +Vcc through the resistors 112 and 113 and to earth through the resistor 114. The emitter of the transistor 111 is connected directly to the earth. The collector is connected to the power supply +Vcc through an inductance element (coil) 121 of the tuning means 120 and the resistor 113, and further connected to earth through a capacitor 122. The collector of the transistor 111 is also connected through a capacitor 123 to the cathode of a reactance element or a variable capacitance diode 124 whose reactance varies with a d.c. applied voltage. The anode of the diode 124 is directly connected to earth. Further, the collector of the transistor 111 is connected to the base of the amplifying transistor 131 through capacitors 123 and 103. The base of the transistor 131 is connected to the power supply +Vcc through a resistor 132 and also connected to earth through a resistor 133. The emitter of the transistor 131 is directly connected to earth, further to the power supply +Vcc through a resistor 134 and to the input terminal 51-20 of the programmable counter 51. 200 denotes a digital-analog converter provided with the same number of input terminals (in this embodiment ten terminals) as that of the digital input data terminals of the counter 51, and one output terminal. The input terminals 200-1, 200-2, 200-3, . . . 200-10 are connected respectively to the input terminals 51-1, 51-2, 51-3 . . . 51-10 of the counter 51. Therefore, each input terminal of the converter 200 receives a part of the digital input data going from the frequency division ratio setting means 52 to the counter 51. The converter 200 converts its digital signal to an analog signal or a d.c. voltage and leads it to the output terminal 200-30. The output terminal 200-30 is connected to the cathode of the variable capacitance diode 124 in the tuning means 120. The d.c. voltage appearing at the terminal 200-30 is applied to the variable capacitance diode 124 as a reverse bias voltage and varies the reactance of the diode 124 in accordance with the value of the applied voltage. The tuned frequency of the tuning means 120 in this case is given by ##EQU1## where ##EQU2## and L.sub.121 is the inductance of the inductance element 121, C.sub.122 is the capacitance of the capacitor 122, C.sub.123 is the capacitance of the capacitor 123, and C.sub.124 is the capacitance of the variable capacitance diode.

Next, we will assume, in the circuit of FIG. 2, that the oscillation frequency f.sub.0 of the reference signal oscillator 1, the oscillation frequency f.sub.1 of the voltage controlled oscillator 4, and the oscillation frequency f.sub.2 of the local oscillator 6 as

f.sub.0 = 20 KHz,

f.sub.1 = 125 - 135 MHz,

f.sub.2 = 120 MHz.

Table 1 shows an example with five digital input terminals 51-1, 51-2, 51-3, 51-4 and 51-5 of the counter 51.

Here, an up-counter of binary code is used as the programmable counter. The digital-analog converter supplies an output d.c. voltage in accordance with the tuning curve as shown in FIG. 3.

FIG. 3 shows a characteristic curve showing the relation between the tuned frequency f and the d.c. voltage applied to the variable capacitance diode, and the capacitance c of the diode at the tuning.

As described above, by controlling in such a manner that a part of digital input data of the programmable counter means 5 is detected and then converted to an analog voltage in accordance with the level thereof and then the analog d.c. voltage is applied to the variable capacitance diode 124 in the tuning means 120 provided at the output stage of the mixer 110, with the capacitance being controlled so as to adjust the tuning frequency to the difference frequency of the mixer 110, the signal with the mixed difference frequency can have a stable and sufficiently large amplitude. Moreover, since the tuned frequency is controlled to be tuned at the difference frequency of the mixer 110 in accordance with the digital input data of the counter means 5, the difference frequency of the mixer 110 to the operation frequency of the counter can be pulled up to its maximum operation frequency.

FIG. 4 is a block diagram of a PLL synthesizer showing another embodiment of this invention. In FIG. 4, the like reference numerals are used to denote like parts as used in FIGS. 1 and 3. 120' denotes a tuning means. The collector of the mixing transistor 111 of the mixer 110 is connected to the earth through a capacitor 123 of the tuning means 120' and a capacitor 124' (with a capacitance C.sub.124'), which serves as the variable capacitance diode 124 of FIG. 2, and also through a series circuit of the capacitance 123 and inductances 120'-1 (inductance L.sub.1), 120'-2(L.sub.2) -- 120'-11(L.sub.11). 300 denotes a switch group having a plurality of switching transistors 301, 302, . . . 310. The bases of these switching transistors 301 to 310 are connected to earth through capacitors 321 to 330 respectively, and also connected to the input data terminals 51-1 . . . 51-10 through resistors 341 to 350 respectively, and the connecting points between these input data terminals and the frequency division ratio setting switches 521-1 to 521-10 respectively. The emitters of the transistors 301 to 310 are directly connected to earth. The collectors are connected to the power supply +Vcc through resistors 361 to 370 respectively, and further connected to the earth sides of the inductors 120'-1 to 120'-10 respectively. These switching transistors are switched by stepwise inputs of the digital data from the frequency division setting means 52 and the counter 51.

In the circuit construction shown in FIG. 4, when a digital signal 1 is being supplied from the frequency division ratio setting means 52 to the data input terminal 51-1 of the counter 51, a part of the digital signal is also supplied to the base of the transistor 301 to make the transistor on. By this switching, the inductor 120'-1 works as an inductance element of the tuning means 120'. Since inductors 120'-2 to 120'-11 are short-circuited by the transistor 301, their effect as an inductance element is lost. Therefore, the tuned frequency f of the tuning means 120' is given by ##EQU3## where L.sub.1 is the inductance of the inductor 120'-1 and C.sub.124' is the capacitance of the capacitor 124'.

In a similar way, if the switching transistor 301 is off and 302 is on, the inductances 120'-1 and 120'-2 work as the inductance element of the tuning means 120'. Since other inductors are short-circuited, their effect as an inductance is lost. Then, the tuned frequency f of the tuning means 120' is given by ##EQU4## where L.sub.2 is the inductance of the inductor L.sub.2. In a similar way, when the switching transistor 302 is off and 303 is on; and 302 is off and 304 is on etc. -- the inductance of the tuning means 120' becomes L.sub.1 + L.sub.2 + L.sub.3 + L.sub.4 + etc. -- whereby the tuned frequency becomes ##EQU5## Each frequency thus obtained is set at each central frequency of the difference frequencies of the mixer 110.

As described above, by detecting the presence of the input to the digital input data terminals 51-1 to 51-10 of the counter 51, making on and off the switching transistors 301 to 310 in accordance with the presence and absence of the detected signals, switching the inductors 120'-1 to 120'-11 of the tuning means 120' provided at the output stage of the mixer in accordance with the on and off of the transistors and controlling the tuning frequency of the means 120' to be tuned at the difference frequency of the mixer, the same effect as that of the embodiment shown in FIG. 2 may be obtained economically.

Although in the embodiment of FIG. 4 the inductors are switched in series, it is apparent that they may be switched in parallel or replaced by capacitors. If the input data of the counter 51 are given by the connect and disconnect of a switch, the inductors of the tuning means 120' may be switched in gang therewith. Further, it may be possible to give a weight to the values of inductors or capacitors and vary their combination.

FIG. 5 shows an example of the application of FIG. 4. In FIG. 5, the base of switching transistor 301 is connected to the cathodes of diodes 381 and 382 through a resistor 341. The anode of the diode 381 is connected to the input data terminal 51-3 of the counter 51 while the anode of the diode 382 is connected to the input data terminal 51-1 of the counter 51. The base of the transistor 302 is connected to the input data terminal 51-1 of the counter through a resistor 342, while the base of the transistor 303 is connected to the cathodes of diodes 383 and 384. The anode of the diode 383 is connected to the input data terminal 51-3 while the anode of the diode 384 is connected to the input data terminal 51-2 of the counter 51. Other parts are the same as those of FIG. 4, and like reference numerals are used to denote like parts as used in FIG. 4. No detailed explanation of these parts will be made.

In the circuit construction of FIG. 5, if the logical product of the inputs of terminals 51-1 and 51-2 of the counter 51 is 1, the transistor 301 is switched on and the inductance elements 120'-2 (inductance L.sub.2), 120'-3 (L.sub.3) and 120'-4 (L.sub.4) are short-circuited. The tuned frequency of the tuning means 120' becomes ##EQU6##

If the input to the terminal 51-1 is 1 and the input to the terminal 51-2 is 0, the transistor 302 is switched on and the inductors 120'-3 (L.sub.3) and 120'-4 (L.sub.4) are short-circuited. The tuned frequency of the tuning means 120' becomes ##EQU7##

In a similar way, if the input to the terminal 51-1 is 0 and the logical product of the inputs to the terminals 51-2 and 51-3 is 1, the transistor 303 is switched on and the inductor 120'-4 (L.sub.4) is short-circuited. The tuned frequency f of the tuning means 120' becomes ##EQU8##

Table 2 shows an example of setting in the above case.

The capacitance of the capacitor 124' is C.sub.124' = 10 PF, and L.sub.1 = 13.1, L.sub.2 = 6, L.sub.3 = 12.8, L.sub.4 = 31.3 (.mu.F). By the above setting, the same functional effect may be obtained as that of the above embodiment.