Low-Frequency Power Amplifier

1. Field of the Invention

Our present invention relates to a low-frequency power amplifier of the operational type, with a noninverting and an inverting input terminal and with a feedback resistor inserted between its inverting input terminal and its output terminal.

2. Background of the Invention

In commonly owned U.S. Pat. No. 3,828,265 there has been disclosed a three-stage power amplifier in the form of an integrated-circuit module or chip with a multiplicity of transistors, resistors and diodes. The various external connections of this IC module include, besides the aforementioned input and output terminals, a supply terminal connected to the live (e.g. positive) pole of a d-c supply, a ground lead and several ancillary terminals, one of the latter being tied to a junction of two resistors inserted as a voltage divider between the supply terminal and ground in series with one of two twin transistors forming part of a voltage-stabilizing circuit. The last-mentioned ancillary terminal can be grounded through a shunt capacitor (though that is not described in the patent) for the purpose of smoothing fluctuations of the supply voltage which could have an adverse effect upon the signal appearing on the output terminal.

The gain of such an operational amplifier is determined, as is well known, by the ratio of the magnitude of the aforementioned feedback resistor to an external impedance inserted between the inverting input terminal and ground; as shown in the prior patent referred to, this external impedance may comprise another resistor in series with a condenser. If the capacitance of this condenser is large enough to be negligible in the range of operating (e.g. audio) frequencies of the amplifier, the amplification factor A is given by the well-known formula

wherein R.sub.1 and R.sub.2 respectively represent the internal feedback resistor and the external resistor in series therewith. Resistor R.sub.1, therefore, is generally made much larger than resistor R.sub.2.

In the system of the prior patent, the second twin transistor of the voltage-stabilizing circuit draws current through the internal feedback resistor (referred to above as R.sub.1) so that the voltage drop thereacross varies with the stabilizing current. Thus, unavoidable tolerances in the magnitude of this internal resistor among a multiplicity of mass-produced monolithic chips affect both the amplification factor A and the mean voltage of the output terminal, intermediate the supply voltage and ground, in the case of identical external circuitry. While the gain-determining ratio R.sub.1 /R.sub.2 can be re-established by a proper dimensioning of the external and therefore readily accessible resistor R.sub.2, such an adjustment has virtually no effect upon the mean output voltage inasmuch as the capacitance in series with resistor R.sub.2 blocks the flow of direct current therethrough.

An object of our present invention is to provide simplified circuitry for a low-frequency power amplifier, or similar semiconductive devices, obviating the need for a separate terminal to be capacitively grounded in order to absorb supply-voltage fluctuations.

Another object is to provide, in an amplifier of the general type disclosed in prior U.S. Pat. No. 3,828,265, a single external circuit for voltage-stabilizing and gain-controlling purposes.

We realize these objects, in accordance with the present invention, by connecting a resistive voltage divider between the output and ground terminals, a tap on that voltage divider being returned to the inverting input terminal by way of a capacitor substantially compensating the effect of any supply-voltage fluctuations upon the voltage of the output terminal.

Advantageously, for reasons more fully discussed hereinafter, the voltage divider comprises a larger first resistance between the tap and the output terminal and a smaller resistance between the tap and the ground terminal. On the other hand, the magnitude of the internal feedback resistor (R.sub.1) should substantially exceed the first resistance of the divider.

The above and other features of our invention will now be described in detail with reference to the accompanying drawing in which:

FIG. 1 is a circuit diagram of a conventional power amplifier generally similar to that shown in prior U.S. Pat. No. 3,828,265; and

FIG. 2 is a circuit diagram showing the same kind of amplifier incorporating our present invention.

FIG. 1 represents a simplified presentation of an amplifier of the type disclosed in U.S. Pat. No. 3,828,265, including a monolithic chip IC with a number of terminals 1- 6 giving access to its internal circuitry. That circuitry includes a transistorized amplification network with three cascaded stages, the first two stages being represented schematically by a block 10. The third or power stage includes a pair of NPN output transistors T.sub.1, T.sub.2 serially connected between a live (positive) bus bar 11 and a ground bus bar 12, bus bar 11 being tied to terminal 5 for connection to a d-c power supply (not shown) delivering a voltage V.sub.S to the network; bus bar 12 is tied to terminal 2. Power transistors T.sub.1 and T.sub.2 are controlled, in respective Darlington connections, by a pair of pilot transistors T.sub.6 and T.sub.7 of opposite conductivity types (NPN and PNP, respectively); the bases of these pilot transistors are biased by an output lead 13 of a current-limiting circuit G (details of which are shown in the aforementioned patent) with interposition of a low resistance, in the form of three cascaded diodes D.sub.1 - D.sub.3, between the bases of transistors T.sub.6 and T.sub.7. The current flow in lead 13 is determined by the second or intermediate amplification stage in block 10, under the control of a signal applied to terminal 1 which constitutes the noninverting input of the amplifier, and is modified by a voltage-stabilizing circuit including an NPN transistor T.sub.4 whose collector is connected to another output of circuit G via a lead 14. The emitter of transistor T.sub.4 is grounded through a resistor R.sub.5 while its base is tied to the collector of another NPN transistor T.sub.3 with a grounded emitter; a twin T.sub.5 of transistor T.sub.3, also with a grounded emitter, has its collector tied to terminal 3 which is the inverting input of the amplifier. The interconnected bases of twin transistors T.sub.3 and T.sub.5 are joined by way of a diode D.sub.4 to the collector of transistor T.sub.3 and thus to the base of transistor T.sub.4 ; the current drawn by transistor T.sub.5 substantially duplicates that drawn by its twin T.sub.3.

A feedback resistor R.sub.1, which like resistor R.sub.5 forms part of the integrated chip IC, lies between inverting input terminal 3 and terminal 4 which constitutes the output of the amplifier and which feeds a load connected between this terminal and ground, the load being here shown as a microphone Z in series with a coupling condenser C.sub.3.

Two other resistors R.sub.3 and R.sub.4, also monolithically integrated in the chip IC, form a voltage divider connected between positive bus bar 11 and the collector of transistor T.sub.3. The junction of resistors R.sub.3 and R.sub.4 is tied to terminal 6 which is grounded for alternating current through a capacitor C.sub.1 designed to smooth any fluctuations of supply voltage V.sub.S. Another external capacitor C.sub.2 is inserted between ground and inverting input terminal 3 in series with an external resistor R.sub.2 forming a gain-determining voltage divider with internal resistor R.sub.1 as discussed above. The capacitance C.sub.2 is negligible at the operating frequencies of the system but blocks the flow of direct current through resistor R.sub.2.

It will be seen that the current drawn by transistor T.sub.5, which matches the current passing through transistor T.sub.3, traverses the resistor R.sub.1 and thus affects the d-c potential V.sub.o existing on output terminal 4 in the absence of a signal. It will also be apparent that the magnitude of resistor R.sub.2 has virtually no influence upon this d-c potential representing the mean output voltage.

Reference will now be made to FIG. 2 showing a generally similar power amplifier whose internal circuitry, within chip IC, differs from that shown in FIG. 1 by the omission of resistor R.sub.4 and of the connection leading from resistor R.sub.3 to an external capacitance C.sub.1 via an ancillary terminal 6. Output terminal 4, furthermore, is grounded through a voltage divider consisting of resistors R.sub.6 and R.sub.7 in series; a tap on this voltage divider, i.e. the junction of its two resistors, is returned to inverting input terminal 3 through a capacitance C.sub.4.

A comparison between FIGS. 1 and 2 shows that capacitance C.sub.4 and resistor R.sub.7 play the part of elements C.sub.2 and R.sub.2 of the conventional amplifier lying in series with feedback resistor R.sub.1. Thus, resistor R.sub.7 in FIG. 2 determines the amplification factor A according to equation (1), it being therefore desirable that R.sub.1 be considerably larger than R.sub.7.

If .DELTA.I.sub.5 is the fluctuation of the collector current of transistor T.sub.5 due to a fluctuation .DELTA.V.sub.S of the supply voltage V.sub.S, we may write

(neglecting the collector-emitter resistances of conducting transistors T.sub.3 and T.sub.5) in view of the substantial equality of the current flow through the twin transistors. The influence of this current fluctuation .DELTA.I.sub.5 upon the output voltage V.sub.o can be represented, neglecting the small flow through the large feedback resistor R.sub.1, as follows: ##EQU1##

With R.sub.6 > R.sub.7, and with substitution of equation (2) into equation (3), the output-voltage fluctuation .DELTA.V.sub.o is given by the simplified equation (neglecting the minus sign) ##EQU2##

In the latter equation the fluctuation .DELTA.V.sub.o becomes a small fraction of .DELTA.V.sub.S if R.sub.6 < R.sub.3 and X.sub.4 < R.sub.6, X.sub.4 being the impedance of capacitor C.sub.4 at the operating frequencies.

Thus, with impedance X.sub.4 negligible for the signal currents, terminal 3 is linked with terminal 4 by two essentially resistive parallel branches R.sub.1, R.sub.6 and is grounded through resistor R.sub.7. With R.sub.1 > R.sub.6, the ratio between an input voltage V.sub.i at terminal 1 (which is essentially duplicated at terminal 3) and the corresponding output voltage V.sub.0 is given by ##EQU3## whence the amplification factor A is given by ##EQU4##

It will thus be seen that the gain of the amplifier of FIG. 2 is determined by two external resistance elements R.sub.6 and R.sub.7 which can be easily adjusted to the desired values independently of the circuit constants of chip IC. With elimination of terminal 6 shown in FIG. 1, our improved amplifier may be mounted on a socket or supporting strip with five terminals (including ground terminal 2) from which the external connections can be extended with the aid of a 5-tongue lead frame of the type described in commonly owned application Ser. No. 508,951 filed Sept. 23, 1974 by Raimondo Paletto.

It will further be noted that in contradistinction to the system of FIG. 1, which comprises two external capacitances C.sub.1, C.sub.2 and one external resistance R.sub.2, our improved system has two external resistances R.sub.6, R.sub.7 and one external capacitance C.sub.4 which can be more economically produced. The elimination of resistor R.sub.4 within chip IC further simplifies the structure.

Our present invention is not limited to a power amplifier of the type discussed but is applicable to other semiconductive devices, especially those of the integrated-circuit type, in which fluctuations of a supply voltage are to be compensated to minimize their effect upon the output of an amplification stage.