Method and Apparatus for Measuring the Speed at Which a Tape Was Recorded

1. Field

The invention relates to video tape recorder/reproducer speed control circuits, and particularly to a speed measuring circuit for identifying the speed at which the tape was previously recorded.

2. Prior Art

Tape speed on playback is normally set by manual means on video tape recorder/reproducers (VTR) since in the past most television stations operated at the standard tape speed of 15 inches/second (ips). However, since video tape has become more expensive, and has been improved to allow broadcast quality recording at video bandwidths with slower tape speeds, a larger number of broadcasters are employing the 71/2 ips standard. As a result, a mixture of tapes recorded at both 71/2 and 15 ips are being used, and an automatic switching method is desirable to preclude operator error during playback of the tapes.

The pre-recorded control track on a video tape is an expeditious means for sensing the speed used for recording the tape. However, on quadruplex VTRs the standard control track is a composite signal of multiple frequencies and includes a 240 Hz signal with a large component of third harmonic distortion, frame pulses, etc. Thus it is difficult to extract the 240 Hz signal recorded in the composite control track with any degree of accuracy, over the range of tape speeds encountered when rapidly moving tape.

The present invention provides a tape speed measuring circuit which circumvents the problems associated with extracting a precise control track signal over the full range of operating speeds, while allowing instant identification, upon playback, of the speed at which the tape was recorded. To this end, the control track is divided down to frame rate which provides an averaging period. During each of the time periods, a selected number of capstan tach pulses will be counted for a 15 ips recording, which is greater than the number of pulses which are counted for a 71/2 ips recording. If a threshold pulse count is selected halfway between the number of pulses counted for a 15 ips recording and a 71/2 ips recording, counting the number of pulses during tape motion will provide means for determining the recording speed. To this end, a divider counts the number of tach pulses during playback, whereby if the number exceeds the threshold count the recording was made at 15 ips, and vice versa. A resulting logic level output is then utilized to automatically set the speed of the VTR upon playback of the video tape.

FIG. 1 is a block diagram of an embodiment of the invention combination.

FIG. 2 is a schematic diagram of the circuit of FIG. 1.

The measuring circuit of the invention utilizes the relationship of the quadruplex VTR that the capstan tach is 3.84 kHz at 15 ips playback speed. This is 16 times the control track frequency of 240 Hz. At 71/2 ips playback speed, the capstan tach frequency is 1.92 kHz, or 8 times the control track frequency. By measuring the ratio of control track frequency relative to the capstan tach frequency, the recorded tape speed can be determined.

Although the invention is herein described with respect to a quadruplex VTR employing a 525-line NTSC format and associated control track, tach, etc., frequencies, it is to be understood that the concept can be employed with other video, audio, etc., recorder/reproducers having multiple frequency control tracks, and/or with 625-line PAL or SECAM formats.

Referring to FIG. 1, there is shown a section of video tape 12 which is driven via a capstan 14. A standard quadruplex control track 16 is recorded on the video tape 12 and is read via a control track head 18. A capstan tach means 20 is coupled to the capstan and generates a tach signal indicative of the rotation of the capstan 14. The control track head 18 generates a control track signal indicative of the movement of the video tape past the VTR head means (not shown). The control track signal is introduced to a multiple capacitor filter 22 of a commutating filter means 24. The tach signal is introduced to a divide-by-16 divider 26 of the commutating filter means 24, as well as to a divider 28. The commutating filter means 24 is described more fully in FIG. 2, as well as in the articles in "ELECTRONIC DESIGN", Vol. 16, Aug. 2, 1974, pages 96-101, and Vol. 23, Nov. 8, 1974, pages 116-120.

The control track signal is not a pure sine wave, but is instead the composite of a 240 Hz frequency recorded at tape saturation which causes severe third harmonic distortion, with the addition of a frame pulse at the frame rate. Therefore, the commutating filter means 24 provides a filter which will track the control track signal at all tape speeds. As shown in FIG. 1, the filter is clocked by the capstan tach signal via divider 26. The resulting filtered control track signal is introduced to a divide-by-8 divider 30, which generates a 30 Hz frame rate which, in turn, is delivered to a monostable multivibrator 32 for generating a 5 microsecond pulse. A second monostable multivibrator 34 is coupled to multivibrator 32 and generates a second 5 microsecond pulse.

AND gate 36 is coupled to the 32 and 64 count outputs of divider 28 and thence to the input of a "D" type flip-flop 38. The flip-flop 38 functions as a memory, which remembers its last state until clocked again via the 5 microsecond pulse from the monostable multivibrator 32. The divider 28 is reset via the 5 microsecond pulse from the monostable 34 at the end of the averaging period during which tach pulses are being counted via divider 28. The output of flip-flop 38 is delivered to output terminal 40, and comprises a high or low logic level representative of the standard 15 or 71/2 ips recording tape speed, respectively.

By way of example, during an averaging period selected by dividing down the control track signal via the divider 30, there should be 128 capstan tach pulses counted by divider 28 if the video tape 12 was recorded at 15 ips, or 64 tach pulses if the tape was recorded at 71/2 ips. The threshold count is selected as half-way between the 128 and 64 number of tach pulses, or at 96 pulses. If the divider 28 counts a number of tach pulses during the averaging period which exceeds 96, a high logic level is clocked into the "D" flip-flop 38, thereby identifying a standard 15 ips recording. If the number of counts in an averaging period is less than 96 tach pulses, a low logic level is clocked into the flip-flop 38, identifying a standard 71/2 ips recording. The averaging period is determined by the clock to the memory flip-flop 38, and is reset via the reset pulses from monostable 34 to the divider 28.

FIG. 2 shows in greater detail the schematic diagram of the circuit of FIG. 1. The control track signal is introduced via head 18 to the sectioned filter 22 of the commutating filter means 24 via an input amplifier 42. The resulting sampled control track signal is introduced to a buffer 44 defined by a voltage follower circuit, and thence to an amplifier 46. A low pass filter 48 with frequency characteristics outside the band pass of the control track signal removes switching noise introduced via the commutating filter means 24. The filtered control track signal is then introduced to a squarer circuit 50, which functions as a zero crossing detector for generating a square wave from the crossover points of the filtered control track signal sine wave, and thence to a monostable multivibrator 52 to provide a clean pulse to the divider 30. The latter is coupled to the multivibrators 32, 34, wherein multivibrator 32 provides the clock pulse to the flip-flop 38 via an AND gate 54. Multivibrator 34 provides a clear pulse to a monostable multivibrator 56, which acts as a latch circuit. The pins of divider 28 corresponding to 32 and 64 counts are coupled to AND gate 36, which herein comprises a pair of AND gates in series, coupled in turn to the monostable multivibrator 56. The latter is coupled to the flip-flop 38 and thence to the output terminal 40.

The filtered control track signal from low pass filter 48 is introduced to the AND gate 54 via AC coupling 60, detector diodes 62 for providing peak detection of the signal, and a threshold detector 64. The components 62, 64 provide means for detecting the absence of the control track, thereupon disabling the AND gate 54 and the flip-flop 38, to maintain the latter in its last experienced state.